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Presenter: Dilip VasudevanSupervisor: Dr.Aristides Efthymiou
University of Edinburgh
1 September 2008
20th UK Async Forum
Manchester
Partial Scan Test Generation for Asynchronous Circuits Based on Breaking
Global Loops
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Introduction
Test Methodology
Working Example
Results
Conclusion
Synopsis
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Introduction
Main challenges faced by applying ATPG technique to the asynchronous circuits are
•Asynchronous circuits have loops which makes them cyclic circuit
•Asynchronous circuits consist of memory element(C-element) other than latches.
•The operation of C-element cannot be controlled during their normal operation compared to normal latch controlled by clock.
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Contribution
Effective handling of cyclic asynchronous circuits to accommodate them for the usual synchronous test generation flow
Partial scan element selection based on Breaking global loops
Global Loops broken by finding Strongly Connected Components
Automatic Test Pattern Generation for the partial scan design generated
The contribution of the project AGLOB is
A Graph is Strongly Connected if there is a path from each vertex in the graph to every other vertex.
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AGLOB
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AGLOB – A Partial Scan Test generation for Asynchronous Circuits Based on Global
LOop Breaking
•Partial scan selection -Finding Strongly Connected Components
•Global loops are broken by partial scan selection
•Local loops are broken by applying cyclic to acyclic conversion
•Fault simulation and test generation –Synopsys Tetramax
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Cyclic Circuits with loops
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Cyclic Circuits with loops
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AGLOB Test Methodology
Scan Selection
AcyclicConverter
Acyclic Netlist
Tetramax Patterns
DFT Netlist
Fault Simulation
FaultCoverage
DUT Netlist
Processing Local Loops
GlobalLoopsBroken
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L(1) 1 2
L(2) 2 3
L(3) 3 4 6
L(4) 3 4 6 7
First Pass Second Pass
Scan Elements = {3}
Scan Elements = {1,3}
L(1) 1 2
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Test generation C-element – (LOCAL LOOP)
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Global loop in the ramreadsbuf
Gates Constituting the loop in ramreadsbuf
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88.23100
76.1976.6777.7889.1991.2392.7776.7896.3476.7896.2590.36
-1009785.710097.196.9100 10010010010094.9
-40.087.921.410097.196.910010010010010059.3
2622484025565460 82 90 62110 94
C-elementHalfHazarddffrcv-setupchu150chu133mp-forw-packnak-param-read-bufrpdftsbuf-ram-writesbuf-send-ctrl
Proposed[SS]E
Fault coverageNo of faults
Benchmark
Results – AGLOB
E – Eichelberger's
SS - Spin-Sim
TABLE IFault Coverage Comparison of proposed method
with Eichelberger's method and Spin SIM
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Results - AGLOB
TABLE IIResult – Fault Coverage Comparison of proposed methods
with Latch Free, latch based designs
3 local 90.36 94.16 16.20Sbu-send-ctrl
2 local96.2595.0022.79sbuf-ram-write
1g,2local96.3493.2940.71ram-read-buf
1g,1local92.7795.18 69.57mp-forward-packet
2 local89.1990.1523.33chu150
1 local91.2385.7145.56chu133
LoopsProposed FC (%)
Full-scanFC (%)
Latch freeFC (%)
Benchmark
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0102030405060708090100
chu1
33
chu1
50
mp-
forw
ard-
pkt
ram
-rea
d-bu
f
sbuf
-ram
-w
rite
sbuf
ctrl
Fullscan
Proposed Partial Scan
Fig 9. Scan latch Overhead Reduction in percentage
Results - AGLOB
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CONCLUSIONS
• A Partial Scan based ATPG method for was introduced
• Fault coverage - 76- 100%
• Scan Area Overhead reduction - 0 – 66% (compared to full scan)
• Future work - Transistor Level Test Generation with new Fault Model
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Thank You!
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