ISTANBUL TECHNICAL UNIVERSITY
DEPARTMENT OF ELECTRICAL ENGINEERING
POWER ELECTRONIC CIRCUITSFALL 2008, CRN: 11473
ASST. PROF. DENİZ YILDIRIM
PROJECT REPORT
MINI PROJECT 3
DC Chopper
GROUP MEMBERS
040050437040050442040060450
BURAK BEŞERELİF KÖKSALBİROL ÇAPA
SUBMISSION DATE: December 25, 2008
1. Purpose
The purpose of this project is designing an “DC Chopper” that controls the
speed of a permanent magnet DC motor.
This project consists of three main steps, designing an DC Chopper,
simulating the circuit by using PSIM, and construction the circuit. After the
construction step, the circuit will be tested for some conditions to see if it obeys
the simulation results.
The controller of the chopper needs 18V DC supply voltage. At the controller
part, after producing a PWM signal at a suitable frequency, a MOSFET triggered,
so that the motor.
In conclusion, by changing the duty cycle of the PWM by a potentiometer, the
speed of the motor can be adjusted.
2. Design
Figure 2.1 - Circuit of a DC chopper
A typical DC chopper circuit is shown in figure-1.1. The control signal of the
motor which comes from a MOSFET is producing by a PWM controller. By
regulating the PWM duty cycles using R2 resistor, span of MOSFET’ s triggering
changes. R1 is used to adjust the frequency of the PWM. After producing the
signal, a gate driver is used for produce the necessary current for the MOSFET’ s
capacitor’ s. The supply voltage of the control part is 18V DC, which comes from
2 9 volt batteries.
A control circuit is shown in figure 2.2. As seen in the circuit UC3525A, an
PWM regulator, unit is used. Instead of UC3525A, SG3524, shown in figure 2.3,
can be used also. Inside of the unit a saw tooth signal is produced by an
oscilloscope. The frequency is adjusted by Rt resistor and Ct capacitor. 5 V DC,
which is regulated by the unit again, is adjusted at an designed ratio with a resistor
at the non inverting pin. By an comparator the DC signal and the saw tooth signal
are compares. As a result an PWM signal is produced.
Figure 2.2 - The control circuit
Figure 2.3 - SG3524 PWM regulator
The PWM signal can be seen at both 11th pin and 14th pin, but the signal at
14th pin is shifted by π. So, instead of having waveforms at the oscillation
frequency and a much more effective, the outputs are connected together via 2
resistors.
The output collector current of SG3524 is about 100mA. That ratio is not
suitable for charge the capacitors of the MOSFET. For getting couple of amps
dual high speed power MOSFET driver is used. TC4427 is suitable. 1.5 A output
current comes from both 5th pin and 7th pin. By connecting them, necessary
current is reached. Rg resistor is put for the capacitors’ charging and discharging
correctly at “0” and “1”. Diodes are for saving the MOSFET.
The MOSFET frequency is required to be 50 kHz. According to the formula
in the datasheet of SG3425, Rt and Ct values are calculated for frequency at each
output.
1.18
25
10
4.7
T T
T
T
fR C
f kHz
C nF
R k
3. SimulationIn order to simulate the circuit PSIM is used due to its reliability and
simplicity. The gate driver and PWM controller is simulated with square wave
voltage source and an on-off controller. The motor is simulated as a series of a
constant DC voltage (for the electromotive force voltage), resistance and
inductance. The simulation design is seen in Figure 3.1.
Figure 3.1 – Simulation circuit of the project
For Vin, R, L and EMF the values are chosen 24V, 0.01Ω, 0.1mH and 22V
respectively. With these proper values source current Iin, motor current Ia, motor
voltage Va, MOSFET’s drain current ID and gate controller’s voltage Vg are
sketched. Figure 3.2 – 3.5 are the graphs of these values for %25, %50, %75 and
%100 of duty cycle values respectively.
Figure 3.2 – Relationship and values of Vg, Va, Ia, Iin and ID at %25 duty cycle
Figure 3.3 – Relationship and values of Vg, Va, Ia, Iin and ID at %50 duty cycle
Figure 3.4 – Relationship and values of Vg, Va, Ia, Iin and ID at %75 duty cycle
Figure 3.5 – Relationship and values of Vg, Va, Ia, Iin and ID at %99 duty cycle
As it is seen, waveforms of Vg, Va, Ia, Iin and ID changes with duty cycle.
When the span of duty cycle increase, the time, which Vg and Va are equal zero,
decreases. Also the values of Ia, Iin and ID get bigger.
Simulations are run at steady-state region in order that transient-time region is
a very short term (approximately 0.3ms). As PSIM cannot perform simulation at
%100 value of duty cycle, the last simulation is held at %99 value of duty cycle.
4. Construction and Testing
While testing the circuit a 24 V permanent magnet DC motor is driven. By
chancing the duty cycle with a 220 kΩ potentiometer, the speed controlled.
The following figures are shapes of different duty cycles.
Figure 4.1 - Output of 10% duty cycle
Figure 4.2 - Output of 40% duty cycle
Figure 4.3 - Output of 70% duty cycle
Figure 4.4 - Output of 10% duty cycle
In table 4.1, measured values according to the duty cycle are seen.
Duty cycle Va[V] Ia[A] Motor Speed
[RPM]
10% 2.096 0.75 45.4
20% 3.921 0.75 127.3
30% 6.48 0.78 239.8
40% 8.96 0.8 349.4
50% 11.64 0.81 451.6
60% 13.95 0.81 561.2
70% 16.68 0.82 679.8
80% 19.01 0.85 777.3
90% 21.64 0.9 898.3
95% 22.88 0.92 947.2
Table 4.1 - Measured values due to the duty cycle
Graphic 4.1 – Va due to the duty cycle
Graphic 4.2 – Ia due to the duty cycle
Graphic 4.3 – RPM due to the duty cycle
While testing, Va, Ia and RPM values are measured. The graphic are Va, Ia
and RPM changes due to the duty cycle span. As expected, when duty cycle span
increases, Va and Ia are increase. So the RMP increases and motor runs faster.
5. Conclusion
In this project a DC chopper designed. With an analogue circuit, PWM
signal was obtained. A DC motor controlled by 2 9 V batteries. The circuit
worked properly and controlled the DC motor successfully.
In conclusion, by using low powers, powerful motors can be controlled.
6. Equipments
SG3524 PWM REGULATOR
TC4427 MOSFET DRIVER
IRF540N MOSFET
10nF capacitor
3*0.1uF capacitor
47 uF capacitor
2*UF4007 diode
2*zener diode
UF5408 diode
220 kΩ potentiometer
10 kΩ potentiometer
2*1 kΩ resistor
7. References
1. Vishay Semiconductors (2002). UF5400 thru UF5408. Retrieved
December 24, 2008, from http://www.datasheetcatalog.com/
2. Fairchild Semiconductor Corporation (2001). UF4001 - UF4007.
Retrieved December 24, 2008, from
http://www.datasheetcatalog.com/
3. Fairchild Semiconductor Corporation (2002). IRF540N. Retrieved
December 24, 2008, from http://www.datasheetcatalog.com/
4. Texas Instruments (2003). SG3524. Retrieved December 24, 2008, from
http://www.datasheetcatalog.com/
5. Microchip Technology Inc. (2004). TC4426/TC4427/TC4428. Retrieved
December 24, 2008, from http://www.datasheetcatalog.com/
8. Appendix
Appendix 1 - SG3524 datasheet
Appendix 2 - TC4427 datasheet
Appendix 3 - IRF540 datasheet
Appendix 4 - UF4007 datasheet
Appendix 5 - UF5408 datasheet
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Complete Pulse-Width Modulation (PWM)Power-Control Circuitry
Uncommitted Outputs for Single-Ended orPush-Pull Applications
Low Standby Current . . . 8 mA Typ
Interchangeable With Industry StandardSG2524 and SG3524
description/ordering information
The SG2524 and SG3524 incorporate all thefunctions required in the construction of aregulating power supply, inverter, or switchingregulator on a single chip. They also can be usedas the control element for high-power-outputapplications. The SG2524 and SG3524 weredesigned for switching regulators of either polarity, transformer-coupled dc-to-dc converters, transformerlessvoltage doublers, and polarity-converter applications employing fixed-frequency, pulse-width modulation(PWM) techniques. The complementary output allows either single-ended or push-pull application. Each deviceincludes an on-chip regulator, error amplifier, programmable oscillator, pulse-steering flip-flop, two uncommittedpass transistors, a high-gain comparator, and current-limiting and shutdown circuitry.
ORDERING INFORMATION
TINPUT
REGULATION PACKAGE† ORDERABLE TOP-SIDETA REGULATION
MAX (mV)PACKAGE† ORDERABLE
PART NUMBERTOP-SIDEMARKING
PDIP (N) Tube of 25 SG3524N SG3524N
0°C to 70°C 30 SOIC (D)Tube of 40 SG3524D
SG35240°C to 70°C 30 SOIC (D)Reel of 2500 SG3524DR
SG3524
SOP (NS) Reel of 2000 SG3524NSR SG3524
PDIP (N) Tube of 25 SG2524N SG2524N
–25°C to 85°C 20SOIC (D)
Tube of 40 SG2524DSG2524SOIC (D)
Reel of 2500 SG2524DRSG2524
† Package drawings, standard packing quantities, thermal data, symboliztion, and PCB design guidelines areavailable at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated ! "#$ ! %#&'" ( $)(#" ! " !%$"" ! %$ *$ $! $+! ! #$ !! (( , -) (#" %"$!!. ($! $"$!!'- "'#($ $! . '' %$ $!)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN–IN+
OSC OUTCURR LIM+CURR LIM–
RTCT
GND
REF OUTVCCEMIT 2COL 2COL 1EMIT 1SHUTDOWNCOMP
SG2524 . . . D OR N PACKAGESG3524 . . . D, N, OR NS PACKAGE
(TOP VIEW)
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
T COL 2
OSC OUTEMIT 2
EMIT 1
COL 1
Vref
ReferenceRegulator
Comparator
Oscillator
SHUTDOWN
Error Amplifier
1
2
9
4
5CURR LIM–
CURR LIM+
GND8
10
+
–
+
–
NOTE A: Resistor values shown are nominal.
12
1113
143
IN–
IN+
COMP
1 kΩ10 kΩ
15
RT
CT
REF OUT16
6
7
Vref
Vref
Vref
Vref
VCC
Vref
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Notes 1 and 2) 40 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collector output current, ICC 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference output current, IO(ref) 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current through CT terminal –5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Notes 3 and 4): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.2. The reference regulator may be bypassed for operation from a fixed 5-V supply by connecting the VCC and reference output
(REF OUT) pin both to the supply voltage. In this configuration, the maximum supply voltage is 6 V.3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operation at the absolute maximum TJ of 150°C can impact reliability.4. The package thermal impedance is calculated in accordance with JESD 51-7.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditionsMIN MAX UNIT
VCC Supply voltage 8 40 V
Reference output current 0 50 mA
Current through CT terminal –0.03 –2 mA
RT Timing resistor 1.8 100 kΩ
CT Timing capacitor 0.001 0.1 µF
TA Operating free air temperatureSG2524 –25 85
°CTA Operating free-air temperatureSG3524 0 70
°C
electrical characteristics over recommended operating free-air temperature range, VCC = 20 V,f = 20 kHz (unless otherwise noted)
reference section
PARAMETER TEST CONDITIONS†SG2524 SG3524
UNITPARAMETER TEST CONDITIONS†MIN TYP‡ MAX MIN TYP‡ MAX
UNIT
Output voltage 4.8 5 5.2 4.6 5 5.4 V
Input regulation VCC = 8 V to 40 V 10 20 10 30 mV
Ripple rejection f = 120 Hz 66 66 dB
Output regulation IO = 0 mA to 20 mA 20 50 20 50 mV
Output voltage change with temperature TA = MIN to MAX 0.3% 1% 0.3% 1%
Short-circuit output current§ Vref = 0 100 100 mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values, except for temperature coefficients, are at TA = 25°C§ Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula:
N
n1
(xn X)2
N 1
oscillator section
PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT
fosc Oscillator frequency CT = 0.001 µF, RT = 2 kΩ 450 kHz
Standard deviation of frequency§ All values of voltage, temperature, resistance,and capacitance constant
5%
∆fFrequency change with voltage VCC = 8 V to 40 V, TA = 25°C 1%
∆fosc Frequency change with temperature TA = MIN to MAX 2%
Output amplitude at OSC OUT TA = 25°C 3.5 V
tw Output pulse duration (width) at OSC OUT CT = 0.01 µF, TA = 25°C 0.5 µs
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values, except for temperature coefficients, are at TA = 25°C§ Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula:
N
n1
(xn X)2
N 1
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
error amplifier section
PARAMETERTEST SG2524 SG3524
UNITPARAMETERTEST
CONDITIONS† MIN TYP‡ MAX MIN TYP‡ MAXUNIT
VIO Input offset voltage VIC = 2.5 V 0.5 5 2 10 mV
IIB Input bias current VIC = 2.5 V 2 10 2 10 µA
Open-loop voltage amplification 72 80 60 80 dB
VICR Common-mode input voltage range TA = 25°C1.8 to
3.41.8 to
3.4V
CMMR Common-mode rejection ratio 70 70 dB
B1 Unity-gain bandwidth 3 3 MHz
Output swing TA = 25°C 0.5 3.8 0.5 3.8 V
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values, except for temperature coefficients, are at TA = 25°C
output sectionPARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT
V(BR)CE Collector-emitter breakdown voltage 40 V
Collector off-state current VCE = 40 V 0.01 50 µA
Vsat Collector-emitter saturation voltage IC = 50 mA 1 2 V
VO Emitter output voltage VC = 20 V, IE = –250 µA 17 18 V
tr Turn-off voltage rise time RC = 2 kΩ 0.2 µs
tf Turn-on voltage fall time RC = 2 kΩ 0.1 µs
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values, except for temperature coefficients, are at TA = 25°C.
comparator sectionPARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT
Maximum duty cycle, each output 45%
V Inp t threshold oltage at COMPZero duty cycle 1
VVIT Input threshold voltage at COMPMaximum duty cycle 3.5
V
IIB Input bias current –1 µA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values, except for temperature coefficients, are at TA = 25°C.
current limiting sectionPARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT
VI Input voltage range (either input) –1 to1 V
V(SENSE) Sense voltage at TA = 25°CV(IN ) V(IN ) ≥ 50 mV V(COMP) 2 V
175 200 225 mV
Temperature coefficient of sense voltageV(IN+) – V(IN–) ≥ 50 mV, V(COMP) = 2 V
0.2 mV/°C‡ All typical values, except for temperature coefficients, are at TA = 25°C.
total devicePARAMETER TEST CONDITIONS MIN TYP‡ MAX UNIT
Ist Standby currentVCC = 40 V, IN–, CURR LIM+, CT, GND, COMP, EMIT 1, EMIT 2 grounded,IN+ at 2 V, All other inputs and outputs open
8 10 mA
‡ All typical values, except for temperature coefficients, are at TA = 25°C.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0.1 µF
2 kΩ
10 kΩ
RT
1 W2 kΩ
8
4
2
1
9
6
7
10
11
14
16
3
12
13
(Open)
Outputs
VCC = 8 V to 40 V
15
SHUTDOWN
CT
RT
COMP
IN–
IN+
CURR LIM+ COL 2
COL 1
OSC OUT
REF OUT
EMIT 2
EMIT 1
GND
SG2524 or SG3524
VCC
CT
2 kΩ
1 W2 kΩ
2 kΩ10 kΩ
1 kΩ
5CURR LIM–
VREF
VREF
Figure 1. General Test Circuit
≈0 V
≈VCC
VOLTAGE WAVEFORMS
90%
10%10%
90%
trtf
TEST CIRCUIT
Circuit Under Test
Output
2 kΩ
VCC
Output
Figure 2. Switching Times
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Frequency – Hz
–10
0
10
20
30
40
50
60
70
80
90
Op
en-L
oo
p V
olt
age
Am
plif
icat
ion
of
Err
or
Am
plif
ier
– d
B
10 M1 M100 k10 k1 k100
RL is resistance from COMP to ground
ÏÏÏÏÏÏÏÏÏÏ
RL = 300 kΩ
ÏÏÏÏRL = 1 MΩ
ÏÏÏÏÏÏÏÏÏÏ
RL = 100 kΩ
ÏÏÏÏÏÏÏÏ
RL = 30 kΩ
OPEN-LOOP VOLTAGE AMPLIFICATIONOF ERROR AMPLIFIER
vsFREQUENCY
VCC = 20 VTA = 25°C
RL = ∞
Figure 3
1
– O
scill
ato
r F
req
uen
cy –
Hz
RT – Timing Resistance – kΩ
20 40 1007010742
OSCILLATOR FREQUENCYvs
TIMING RESISTANCE
VCC = 20 VTA = 25°C
1M
400 k
100 k
40 k
10 k
4 k
1 k
400
100
CT = 0.1 µF
CT = 0.01 µF
CT = 0.03 µF
CT = 0.003 µF
CT = 0
f osc
CT = 0.001 µF
Figure 4
OUTPUT DEAD TIMEvs
TIMING CAPACITANCE
1
10
4
0.001 0.01
Ou
tpu
t D
ead
Tim
e –
0.004 0.10.040.1
0.4
µs
CT – Timing Capacitance – µF
Figure 5
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION†
The SG2524 is a fixed-frequency pulse-width-modulation (PWM) voltage-regulator control circuit. The regulatoroperates at a fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor, CT. RTestablishes a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to thecomparator, providing linear control of the output pulse duration (width) by the error amplifier. The SG2524 containsan onboard 5-V regulator that serves as a reference, as well as supplying the SG2524 internal regulator controlcircuitry. The internal reference voltage is divided externally by a resistor ladder network to provide a reference withinthe common-mode range of the error amplifier as shown in Figure 6, or an external reference can be used. The outputis sensed by a second resistor divider network and the error signal is amplified. This voltage is then compared to thelinear voltage ramp at CT. The resulting modulated pulse out of the high-gain comparator then is steered to theappropriate output pass transistor (Q1 or Q2) by the pulse-steering flip-flop, which is synchronously toggled by theoscillator output. The oscillator output pulse also serves as a blanking pulse to ensure both outputs are never onsimultaneously during the transition times. The duration of the blanking pulse is controlled by the value of CT. Theoutputs may be applied in a push-pull configuration in which their frequency is one-half that of the base oscillator, orparalleled for single-ended applications in which the frequency is equal to that of the oscillator. The output of the erroramplifier shares a common input to the comparator with the current-limiting and shut-down circuitry and can beoverridden by signals from either of these inputs. This common point is pinned out externally via the COMP pin, whichcan be employed to either control the gain of the error amplifier or to compensate it. In addition, the COMP pin canbe used to provide additional control to the regulator.
APPLICATION INFORMATION†
oscillator
The oscillator controls the frequency of the SG2524 and is programmed by RT and CT as shown in Figure 4.
f 1.30RT CT
where: RT is in kΩCT is in µFf is in kHz
Practical values of CT fall between 0.001 µF and 0.1 µF. Practical values of RT fall between 1.8 kΩ and 100 kΩ.This results in a frequency range typically from 130 Hz to 722 kHz.
blanking
The output pulse of the oscillator is used as a blanking pulse at the output. This pulse duration is controlled bythe value of CT as shown in Figure 5. If small values of CT are required, the oscillator output pulse duration canbe maintained by applying a shunt capacitance from OSC OUT to ground.
synchronous operation
When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillatoroutput terminal. The impedance to ground at this point is approximately 2 kΩ. In this configuration, RTCT mustbe selected for a clock period slightly greater than that of the external clock.
† Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
synchronous operation (continued)
If two or more SG2524 regulators are operated synchronously, all oscillator output terminals must be tiedtogether. The oscillator programmed for the minimum clock period is the master from which all the otherSG2524s operate. In this application, the CTRT values of the slaved regulators must be set for a periodapproximately 10% longer than that of the master regulator. In addition, CT (master) = 2 CT (slave) to ensurethat the master output pulse, which occurs first, has a longer pulse duration and, subsequently, resets the slaveregulators.
voltage reference
The 5-V internal reference can be employed by use of an external resistor divider network to establish areference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers (see Figure 6), or an externalreference can be applied directly to the error amplifier. For operation from a fixed 5-V supply, the internalreference can be bypassed by applying the input voltage to both the VCC and VREF terminals. In thisconfiguration, however, the input voltage is limited to a maximum of 6 V.
To NegativeOutput Voltage
REF OUT
5 kΩR1
To PositiveOutput Voltage
R25 kΩ
REF OUT
+
–
+
–
5 kΩ
5 kΩ
R2
R1
VO 2.5 V R1 R2R1
VO 2.5 V 1 R2R1
2.5 V 2.5 V
Figure 6. Error-Amplifier Bias Circuits
error amplifier
The error amplifier is a differential-input transconductance amplifier. The output is available for dc gain controlor ac phase compensation. The compensation node (COMP) is a high-impedance node (RL = 5 MΩ). The gainof the amplifier is AV = (0.002 Ω–1)RL and easily can be reduced from a nominal 10,000 by an external shuntresistance from COMP to ground. Refer to Figure 3 for data.
compensation
COMP, as previously discussed, is made available for compensation. Since most output filters introduce oneor more additional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier,introduction of a zero to cancel one of the output filter poles is desirable. This can be accomplished best witha series RC circuit from COMP to ground in the range of 50 kΩ and 0.001 µF. Other frequencies can be canceledby use of the formula f ≈ 1/RC.
† Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
shutdown circuitry
COMP also can be employed to introduce external control of the SG2524. Any circuit that can sink 200 µA canpull the compensation terminal to ground and, thus, disable the SG2524.
In addition to constant-current limiting, CURR LIM+ and CURR LIM– also can be used in transformer-coupledcircuits to sense primary current and shorten an output pulse should transformer saturation occur. CURR LIM–also can be grounded to convert CURR LIM+ into an additional shutdown terminal.
current limiting
A current-limiting sense amplifier is provided in the SG2524. The current-limiting sense amplifier exhibits athreshold of 200 mV ±25 mV and must be applied in the ground line since the voltage range of the inputs is limitedto 1 V to –1 V. Caution should be taken to ensure the –1-V limit is not exceeded by either input, otherwise,damage to the device may result.
Foldback current limiting can be provided with the network shown in Figure 7. The current-limit schematic isshown in Figure 8.
VO
RsR2
R1EMIT 2
EMIT 1
SG2524
IO(max) 1
Rs200 mV
VO R2
R1 R2
IOS 200 mV
Rs
CURR LIM+
CURR LIM–
11
14
5
4
Figure 7. Foldback Current Limiting for Shorted Output Conditions
Constant-Current Source
CURR LIM+
COMP CT
Comparator
Error Amplifier
CURR LIM–
Figure 8. Current-Limit Schematic
† Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
output circuitry
The SG2524 contains two identical npn transistors, the collectors and emitters of which are uncommitted. Eachtransistor has antisaturation circuitry that limits the current through that transistor to a maximum of 100 mA forfast response.
general
There are a wide variety of output configurations possible when considering the application of the SG2524 asa voltage-regulator control circuit. They can be segregated into three basic categories:
Capacitor-diode-coupled voltage multipliers Inductor-capacitor-implemented single-ended circuits Transformer-coupled circuits
Examples of these categories are shown in Figures 9, 10, and 11, respectively. Detailed diagrams of specificapplications are shown in Figures 12–15.
D1
VI
VO
VI < VO
VI
D1
VO
VI > VO
D1
VI
–VO
| +VI | > | – VO |
Figure 9. Capacitor-Diode-Coupled Voltage-Multiplier Output Stages
† Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
VIVO
VI > VO
VI
VI < VO
VO
VI–VO
| +VI | < | – VO |
Figure 10. Single-Ended Inductor Circuit
VO
Push-Pull
VO
VI
Flyback
ÏÏVI
Figure 11. Transformer-Coupled Outputs
† Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
SG2524
COMP
.
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
GND
OSC OUT
CT
RT
REF OUT
IN+
IN–
0.01 µF
0.1 µF
5 kΩ
5 kΩ
2 kΩ
50 µF
–5 V20 mA
1N916
1N91620 µF
1N91615 kΩ
VCC = 15 V
VCC
CURR LIM–SHUTDOWN
+
1
2
16
6
7
10
3
11
12
13
14
4
5
9
8
15
5 kΩ
+
Figure 12. Capacitor-Diode Output Circuit
VCC = 5 V
0.1 µF1 MΩ
300 Ω
1N916
1N916
20T200 Ω
–15 V
20 mA
15 V
50 µF
50 µF
50T
50T
TIP29A
1 Ω
1N916620 Ω
510 Ω
2N2222
4.7 µF
0.001 µF
0.02 µF
5 kΩ
2 kΩ
100 µF
5 kΩ
5 kΩ
SG2524
VCC
OSC OUT
GNDCOMP
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
CURR LIM–
CT
RT
REF OUT
IN+
IN–
+
+
SHUTDOWN
25 kΩ
+
+
1
2
16
6
7
10
3
11
12
13
14
4
5
9
15
8
InputReturn
Figure 13. Flyback Converter Circuit
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003
13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION†
Input Return0.1 Ω
3 kΩ1N3880
500 µF
1 A5 V
0.9 mHTIP115
SG2524
VCC
OSC OUTGND
VCC = 28 V
0.001 µF
50 kΩ
5 kΩ
3 kΩ
0.1 µF
0.02 µF
5 kΩ
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
SHUTDOWN
CT
RT
REF OUT
IN+
IN–
CURR LIM–
COMP
1
2
16
6
7
10
3
11
12
13
14
4
5
9
15
8
5 kΩ
5 kΩ+
Figure 14. Single-Ended LC Circuit
5 kΩ
0.01 µF
0.1 µF
2 kΩ
5 kΩ
20 kΩ
1500 µF
0.1 Ω
100 µF
+
–5 A5 V
20T
20T
5T
5T
TIR101A
1 mH
TIP31A
100 Ω
100 Ω
TIP31A1W
1 kΩ
VCC = 28 V
GNDOSC OUT
VCC
SG2524
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
SHUTDOWN
CT
RT
REF OUT
IN+
IN–
CURR LIM–
COMP
1
2
16
6
7
10
3
11
12
13
14
4
5
9
15
8
5 kΩ
5 kΩ
0.001 µF
+
+
1W1 kΩ
Figure 15. Push-Pull Transformer-Coupled Circuit
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
MECHANICAL DATA
MCER002C – JANUARY 1995 – REVISED JUNE 1999
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
J (R-GDIP-T**) CERAMIC DUAL-IN-LINE
1
20
0.290
(7,87)0.310
0.975(24,77)
(23,62)0.930
(7,37)
0.245(6,22)
(7,62)0.300
1614PINS **
0.290
(7,87)0.310
0.785(19,94)
(19,18)0.755
(7,37)
0.310(7,87)
(7,37)0.290
0.755(19,18)
(19,94)0.785
0.245(6,22)
(7,62)0.300
A
0.300(7,62)
(6,22)0.245
A MIN
A MAX
B MAX
B MIN
C MIN
C MAX
DIM
0°–15°
Seating Plane
0.014 (0,36)0.008 (0,20)
4040083/E 03/99
C
8
7
0.020 (0,51) MIN
B
0.070 (1,78)0.100 (2,54)
0.065 (1,65)0.045 (1,14)
14 LEADS SHOWN
14
0.015 (0,38)0.023 (0,58)
0.100 (2,54)
0.200 (5,08) MAX
0.130 (3,30) MIN
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package is hermetically sealed with a ceramic lid using glass frit.D. Index point is provided on cap for terminal identification.E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, and GDIP1-T20
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
BB AC AD
0.325 (8,26)0.300 (7,62)
0.010 (0,25) NOM
Gauge Plane
0.015 (0,38)
0.430 (10,92) MAX
20
1.060(26,92)
0.940(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775(19,69)
(18,92)0.745
A MIN
DIM
A MAX
PINS **
(23,37)
(21,59)
Seating Plane
14/18 PIN ONLY20 pin vendor option
4040049/E 12/2002
9
80.070 (1,78)
A
0.045 (1,14)0.020 (0,51) MIN
16
1
0.015 (0,38)0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)0.260 (6,60)
M0.010 (0,25)
0.100 (2,54)
16 PINS SHOWN
MS-100VARIATION
AAC
D
D
D0.030 (0,76)
0.045 (1,14)
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE8 PINS SHOWN
8
0.197(5,00)
A MAX
A MIN(4,80)0.189 0.337
(8,55)
(8,75)0.344
14
0.386(9,80)
(10,00)0.394
16DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)0.010 (0,25)
0.010 (0,25)
0.016 (0,40)0.044 (1,12)
0.244 (6,20)0.228 (5,80)
0.020 (0,51)0.014 (0,35)
1 4
8 5
0.150 (3,81)0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).D. Falls within JEDEC MS-012
MECHANICAL DATA
MSOP002 – OCTOBER 1994
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NS (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040062/B 02/95
14 PINS SHOWN
2,00 MAX
A
0,05 MIN
Seating Plane
1,050,55
1
14
PINS **
5,605,00
7
8,207,40
8
A MIN
A MAX
DIM
Gage Plane
0,15 NOM
0,25
9,90 9,90
10,50
14
10,50
16
12,30 14,70
15,3012,90
20 24
0,10
1,27
0°–10°
M0,250,350,51
NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third–party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.
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Mailing Address:
Texas InstrumentsPost Office Box 655303Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
TC4426/TC4427/TC44281.5A Dual High-Speed Power MOSFET Drivers
Features
• High Peak Output Current – 1.5A
• Wide Input Supply Voltage Operating Range:- 4.5V to 18V
• High Capacitive Load Drive Capability – 1000 pF in 25 ns (typ.)
• Short Delay Times – 40 ns (typ.)
• Matched Rise and Fall Times• Low Supply Current:
- With Logic ‘1’ Input – 4 mA
- With Logic ‘0’ Input – 400 µA• Low Output Impedance – 7Ω• Latch-Up Protected: Will Withstand 0.5A Reverse
Current• Input Will Withstand Negative Inputs Up to 5V
• ESD Protected – 4 kV• Pin-compatible with the TC426/TC427/TC428• Space-saving 8-Pin MSOP and 8-Pin 6x5 DFN
Packages
Applications
• Switch Mode Power Supplies• Line Drivers
• Pulse Transformer Drive
General Description
The TC4426/TC4427/TC4428 are improved versionsof the earlier TC426/TC427/TC428 family of MOSFETdrivers. The TC4426/TC4427/TC4428 devices havematched rise and fall times when charging anddischarging the gate of a MOSFET.
These devices are highly latch-up resistant under anyconditions within their power and voltage ratings. Theyare not subject to damage when up to 5V of noise spik-ing (of either polarity) occurs on the ground pin. Theycan accept, without damage or logic upset, up to500 mA of reverse current (of either polarity) beingforced back into their outputs. All terminals are fullyprotected against Electrostatic Discharge (ESD) up to4 kV.
The TC4426/TC4427/TC4428 MOSFET drivers caneasily charge/discharge 1000 pF gate capacitances inunder 30 ns. These device provide low enoughimpedances in both the on and off states to ensure theMOSFET's intended state will not be affected, even bylarge transients.
Other compatible drivers are the TC4426A/TC4427A/TC4428A family of devices. The TC4426A/TC4427A/TC4428A devices have matched leading and fallingedge input-to-output delay times, in addition to thematched rise and fall times of the TC4426/TC4427/TC4428 devices.
Package Types
Note 1: Exposed pad of the DFN package is electrically isolated.
8-Pin DFN(1)
NC
IN A
GND
IN B
2
3
4 5
6
7
811
2
3
4
NC
5
6
7
8
OUT A
OUT B
NCIN A
GNDIN B
VDD
TC4426TC4427
TC4426 TC4427
NC
OUT A
OUT BVDD
TC4426TC4427
TC4428
NC
OUT A
OUT BVDD
TC4428 TC4428
NC
OUT A
OUT B
VDD
TC4426 TC4427
NC
OUT A
OUT B
VDD
TC4428
NC
OUT A
OUT B
VDD
8-Pin MSOP/PDIP/SOIC
2004 Microchip Technology Inc. DS21422C-page 1
TC4426/TC4427/TC4428
Functional Block Diagram
Effective Input C = 12 pF (Each Input)
TC4426/TC4427/TC4428
Output
Input
GND
VDD
300 mV
4.7V
Inverting
Non-Inverting
Note 1: TC4426 has two inverting drivers, while the TC4427 has two non-invertingdrivers. The TC4428 has one inverting and one non-inverting driver.
2: Ground any unused driver input.
1.5 mA
DS21422C-page 2 2004 Microchip Technology Inc.
TC4426/TC4427/TC4428
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage .....................................................+22V
Input Voltage, IN A or IN B..................................... (VDD + 0.3V) to (GND – 5V)
Package Power Dissipation (TA ≤ 70°C)DFN .............................................................. Note 3MSOP..........................................................340 mWPDIP ............................................................ 730 mWSOIC............................................................ 470 mW
Storage Temperature Range.............. -65°C to +150°C
Maximum Junction Temperature...................... +150°C
† Stresses above those listed under "Absolute MaximumRatings" may cause permanent damage to the device. Theseare stress ratings only and functional operation of the deviceat these or any other conditions above those indicated in theoperation sections of the specifications is not implied.Exposure to Absolute Maximum Rating conditions forextended periods may affect device reliability.
PIN FUNCTION TABLE
DC CHARACTERISTICS
Name Function
NC No Connection
IN A Input A
GND Ground
IN B Input B
OUT B Output B
VDD Supply Input
OUT A Output A
NC No Connection
Electrical Specifications: Unless otherwise noted, TA = +25ºC with 4.5V ≤ VDD ≤ 18V.
Parameters Sym Min Typ Max Units Conditions
Input
Logic ‘1’, High Input Voltage VIH 2.4 — — V Note 2
Logic ‘0’, Low Input Voltage VIL — — 0.8 V
Input Current IIN -1.0 — +1.0 µA 0V ≤ VIN ≤ VDD
Output
High Output Voltage VOH VDD – 0.025 — — V DC Test
Low Output Voltage VOL — — 0.025 V DC Test
Output Resistance RO — 7 10 Ω IOUT = 10 mA, VDD = 18V
Peak Output Current IPK — 1.5 — A VDD = 18V
Latch-Up ProtectionWithstand Reverse Current
IREV — > 0.5 — A Duty cycle ≤ 2%, t ≤ 300 µsVDD = 18V
Switching Time (Note 1)
Rise Time tR — 19 30 ns Figure 4-1
Fall Time tF — 19 30 ns Figure 4-1
Delay Time tD1 — 20 30 ns Figure 4-1
Delay Time tD2 — 40 50 ns Figure 4-1
Power Supply
Power Supply Current IS ——
——
4.50.4
mA VIN = 3V (Both inputs)VIN = 0V (Both inputs)
Note 1: Switching times ensured by design.2: For V temperature range devices, the VIH (Min) limit is 2.0V.
3: Package power dissipation is dependent on the copper pad area on the PCB.
2004 Microchip Technology Inc. DS21422C-page 3
TC4426/TC4427/TC4428
DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE)
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, over operating temperature range with 4.5V ≤ VDD ≤ 18V.
Parameters Sym Min Typ Max Units Conditions
Input
Logic ‘1’, High Input Voltage VIH 2.4 — — V Note 2
Logic ‘0’, Low Input Voltage VIL — — 0.8 V
Input Current IIN -10 — +10 µA 0V ≤ VIN ≤ VDD
Output
High Output Voltage VOH VDD – 0.025 — — V DC Test
Low Output Voltage VOL — — 0.025 V DC Test
Output Resistance RO — 9 12 Ω IOUT = 10 mA, VDD = 18V
Peak Output Current IPK — 1.5 — A VDD = 18V
Latch-Up ProtectionWithstand Reverse Current
IREV — >0.5 — A Duty cycle ≤ 2%, t ≤ 300 µsVDD = 18V
Switching Time (Note 1)
Rise Time tR — — 40 ns Figure 4-1
Fall Time tF — — 40 ns Figure 4-1
Delay Time tD1 — — 40 ns Figure 4-1
Delay Time tD2 — — 60 ns Figure 4-1
Power Supply
Power Supply Current IS ——
——
8.00.6
mA VIN = 3V (Both inputs)VIN = 0V (Both inputs)
Note 1: Switching times ensured by design.2: For V temperature range devices, the VIH (Min) limit is 2.0V.
Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V ≤ VDD ≤ 18V.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range (C) TA 0 — +70 °C
Specified Temperature Range (E) TA -40 — +85 °C
Specified Temperature Range (V) TA -40 — +125 °C
Maximum Junction Temperature TJ — — +150 °C
Storage Temperature Range TA -65 — +150 °C
Package Thermal Resistances
Thermal Resistance, 8L-6x5 DFN θJA — 33.2 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 8L-PDIP θJA — 125 — °C/W
Thermal Resistance, 8L-SOIC θJA — 155 — °C/W
DS21422C-page 4 2004 Microchip Technology Inc.
TC4426/TC4427/TC4428
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25ºC with 4.5V ≤ VDD ≤ 18V.
FIGURE 2-1: Rise Time vs. Supply Voltage.
FIGURE 2-2: Rise Time vs. Capacitive Load.
FIGURE 2-3: Rise and Fall Times vs. Temperature.
FIGURE 2-4: Fall Time vs. Supply Voltage.
FIGURE 2-5: Fall Time vs. Capacitive Load.
FIGURE 2-6: Propagation Delay Time vs. Supply Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.
t RIS
E (
nse
c)
4 6 8 10 12 14 16 18
100 pF
470 pF
2200 pF
1500 pF
100
1000 pF
80
60
40
20
0
VDD (V)
100 1000 10,000C (pF)LOAD
5V
10V
15V
100
80
60
40
20
0
t RIS
E (
nse
c)T
ime
(nse
c)
tRISE
Temperature (˚C)
C = 1000 pFLOADV = 17.5VDD
60
–55 –35 5 25 45 65 85 105 125–15
tFALL
50
40
30
20
10
t FA
LL
(n
sec)
4 6 8 10 12 14 16 18
100 pF
470 pF
1000 pF
2200 pF
1500 pF
100
80
60
40
20
0
VDD (V)
100 1000 10,000
5V
10V
C (pF)LOAD
100
80
60
40
20
0
t FA
LL
(n
sec)
15V
20253035404550556065707580
4 6 8 10 12 14 16 18
VDD (V)
Pro
pag
atio
n D
elay
(n
sec)
tD1
tD2
CLOAD = 1000 pF
VIN = 5V
2004 Microchip Technology Inc. DS21422C-page 5
TC4426/TC4427/TC4428
Note: Unless otherwise indicated, TA = +25ºC with 4.5V ≤ VDD ≤ 18V.
FIGURE 2-7: Propagation Delay Time vs. Input Amplitude.
FIGURE 2-8: Supply Current vs. Supply Voltage.
FIGURE 2-9: Output Resistance (ROH) vs. Supply Voltage.
FIGURE 2-10: Propagation Delay Time vs. Temperature.
FIGURE 2-11: Supply Current vs. Temperature.
FIGURE 2-12: Output Resistance (ROL) vs. Supply Voltage.
10
15
20
25
30
35
40
45
50
55
60
0 1 2 3 4 5 6 7 8 9 10 11 12
Input Amplitude (V)
Pro
pag
atio
n D
elay
(n
sec)
tD1
tD2
CLOAD = 1000 pF
VDD = 12V
4
I
(
mA
)Q
UIE
SC
EN
T
186 8 10 12 14 160.1
Both Inputs = 1
Both Inputs = 0
V DD
1
4 6 8 10 12 14 16 18V DD
RD
S(O
N) (
Ω)
20
25
15
10
5
Worst Case @ TJ = +150˚C
Typical @ TA = +25˚C
10
15
20
25
30
35
40
45
-55 -35 -15 5 25 45 65 85 105 125
Temperature (ºC)
Del
ay T
ime
(nse
c)
tD1
tD2
CLOAD = 1000 pFVIN = 5VVDD = 18V
TA (˚C)
I QU
IES
CE
NT (
mA
)
4.0
3.5
3.0
2.5
2.0–55 –35 –15 5 25 45 65 85 105 125
V = 18VDD
Both Inputs = 1
4 6 8 10 12 14 16 18
20
V DD
25
15
10
5
Worst Case @ TJ = +150˚C
Typical @ TA = +25˚C
RD
S(O
N) (
Ω)
DS21422C-page 6 2004 Microchip Technology Inc.
TC4426/TC4427/TC4428
Note: Unless otherwise indicated, TA = +25ºC with 4.5V ≤ VDD ≤ 18V.
FIGURE 2-13: Supply Current vs. Capacitive Load.
FIGURE 2-14: Supply Current vs. Capacitive Load.
FIGURE 2-15: Supply Current vs. Capacitive Load.
FIGURE 2-16: Supply Current vs. Frequency.
FIGURE 2-17: Supply Current vs. Frequency.
FIGURE 2-18: Supply Current vs. Frequency.
60
100 1000 10,000
I SU
PP
LY
(m
A)
2 MHz
600 kHz
200 kHz
20 kHz
900 kHz
C (pF)LOAD
V = 18VDD50
40
30
20
10
0
100 1000 10,000
2 MHz
600 kHz
200 kHz20 kHz
900 kHz
V = 12VDD
C (pF)LOAD
60
50
40
30
20
10
0
I SU
PP
LY
(m
A)
100 1000 10,000
2 MHz
200 kHz20 kHz
600 kHz900 kHz
V = 6VDD
C (pF)LOAD
60
50
40
30
20
10
0
I SU
PP
LY
(m
A)
10 100 1000FREQUENCY (kHz)
1000 pF
2200 pF
V = 18VDD
100 pF
60
50
40
30
20
10
0
I SU
PP
LY (m
A)
10 100 1000FREQUENCY (kHz)
1000 pF
2200 pF
100 pF
V = 12VDD
60
50
40
30
20
10
0
I SU
PP
LY
(m
A)
10 100 1000FREQUENCY (kHz)
1000 pF
2200 pF
100 pF
V = 6VDD
60
50
40
30
20
10
0
I SU
PP
LY (m
A)
2004 Microchip Technology Inc. DS21422C-page 7
TC4426/TC4427/TC4428
Note: Unless otherwise indicated, TA = +25ºC with 4.5V ≤ VDD ≤ 18V.
FIGURE 2-19: Crossover Energy vs. Supply Voltage.
4
A •
sec
186 8 10 12 14 16
876
5
4
3
2
10–9
10–8
9
V DD
Note: The values on this graph represent the lossseen by both drivers in a package during onecomplete cycle. For a single driver, divide thestated values by 2. For a single transition of asingle driver, divide the stated value by 4.
DS21422C-page 8 2004 Microchip Technology Inc.
TC4426/TC4427/TC4428
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE (1)
3.1 Inputs A and B
MOSFET driver inputs A and B are high-impedance,TTL/CMOS compatible inputs. These inputs also have300 mV of hysteresis between the high and lowthresholds that prevents output glitching even when therise and fall time of the input signal is very slow.
3.2 Ground (GND)
Ground is the device return pin. The ground pin(s)should have a low-impedance connection to the biassupply source return. High peak currents will flow outthe ground pin(s) when the capacitive load is beingdischarged.
3.3 Output A and B
MOSFET driver outputs A and B are low-impedance,CMOS push-pull style outputs. The pull-down and pull-up devices are of equal strength, making the rise andfall times equivalent.
3.4 Supply Input (VDD)
The VDD input is the bias supply for the MOSFET driverand is rated for 4.5V to 18V with respect to the groundpin. The VDD input should be bypassed with localceramic capacitors. The value of these capacitorsshould be chosen based on the capacitive load that isbeing driven. A value of 1.0 µF is suggested.
3.5 Exposed Metal Pad
The exposed metal pad of the 6x5 DFN package is notinternally connected to any potential. Therefore, thispad can be connected to a ground plane or other cop-per plane on a printed circuit board, to aid in heatremoval from the package.
8-Pin PDIP/ MSOP/SOIC
8-PinDFN
Symbol Description
1 1 NC No connection
2 2 IN A Input A
3 3 GND Ground
4 4 IN B Input B
5 5 OUT B Output B
6 6 VDD Supply input
7 7 OUT A Output A
8 8 NC No connection
— PAD NC Exposed Metal Pad
Note 1: Duplicate pins must be connected for proper operation.
2004 Microchip Technology Inc. DS21422C-page 9
TC4426/TC4427/TC4428
4.0 APPLICATIONS INFORMATION
FIGURE 4-1: Switching Time Test Circuit.
CL = 1000 pF
0.1 µF4.7 µF
Inverting Driver
Non-Inverting Driver
Input
VDD = 18V
Input
Output
tD1tF
tR
tD2Input: 100 kHz,square wave,
tRISE = tFALL ≤ 10 ns
Output
Input
Output
tD1tF
tR
tD2
+5V
10%
90%
10%
90%
10%
90%VDD
0V
90%
10%
10% 10%
90%
+5V
VDD
0V
0V
0V
90%
3
2 7
6
4 5
DS21422C-page 10 2004 Microchip Technology Inc.
TC4426/TC4427/TC4428
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
XXXXXXXXXXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
TC4427CPA256
0420
8-Lead SOIC (150 mil) Example:
XXXXXXXXXXXXYYWW
NNN
TC4428COA0420
256
8-Lead MSOP Example:
XXXXX
YWWNNN
4426C
420256
Legend: XX...X Customer specific information*Y Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line thus limiting the number of available charactersfor customer specific information.
* Standard device marking consists of Microchip part number, year code, week code, and traceabilitycode.
8-Lead DFN Example:
XXXXXXX
XXXXXXXXXYYWW
NNN
TC4426
EMF0420
256
2004 Microchip Technology Inc. DS21422C-page 11
TC4426/TC4427/TC4428
8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) – Saw Singulated
DS21422C-page 12 2004 Microchip Technology Inc.
TC4426/TC4427/TC4428
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
D
A
A1
L
c
(F)
α
A2
E1
E
p
B
n 1
2
φ
β
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037 REFFFootprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
βα
c
B
φ.003
.009
.006
.012
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016 .024
.118 BSC
.118 BSC
.000
.030
.193 TYP.
.033
MIN
p
n
Units
.026 BSC
NOM
8
INCHES
0.95 REF
-
-
.009
.016
0.08
0.22
0°
0.23
0.40
8°
MILLIMETERS*
0.65 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
.043
.031
.037
.006
0.40
0.00
0.75
MINMAX NOM
1.10
0.80
0.15
0.95
MAX
8
- -
-
15°5° -
15°5° -
JEDEC Equivalent: MO-187
0° - 8°
5°
5° -
-
15°
15°
--
- -
2004 Microchip Technology Inc. DS21422C-page 13
TC4426/TC4427/TC4428
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERSDimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8Pitch p .100 2.54Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68Base to Seating Plane A1 .015 0.38Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60Overall Length D .360 .373 .385 9.14 9.46 9.78Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43Lead Thickness c .008 .012 .015 0.20 0.29 0.38Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78Lower Lead Width B .014 .018 .022 0.36 0.46 0.56Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92Mold Draft Angle Top α 5 10 15 5 10 15Mold Draft Angle Bottom β 5 10 15 5 10 15* Controlling Parameter
Notes:Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
DS21422C-page 14 2004 Microchip Technology Inc.
TC4426/TC4427/TC4428
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot Angle φ 0 4 8 0 4 8
1512015120βMold Draft Angle Bottom1512015120αMold Draft Angle Top
0.510.420.33.020.017.013BLead Width0.250.230.20.010.009.008cLead Thickness
0.760.620.48.030.025.019LFoot Length0.510.380.25.020.015.010hChamfer Distance5.004.904.80.197.193.189DOverall Length3.993.913.71.157.154.146E1Molded Package Width6.206.025.79.244.237.228EOverall Width0.250.180.10.010.007.004A1Standoff §1.551.421.32.061.056.052A2Molded Package Thickness1.751.551.35.069.061.053AOverall Height
1.27.050pPitch88nNumber of Pins
MAXNOMMINMAXNOMMINDimension LimitsMILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
Lβ
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.JEDEC Equivalent: MS-012Drawing No. C04-057
§ Significant Characteristic
2004 Microchip Technology Inc. DS21422C-page 15
TC4426/TC4427/TC4428
NOTES:
DS21422C-page 16 2004 Microchip Technology Inc.
TC4426/TC4427/TC4428
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Device: TC4426: 1.5A Dual MOSFET Driver, InvertingTC4427: 1.5A Dual MOSFET Driver, Non-InvertingTC4428: 1.5A Dual MOSFET Driver, Complementary
Temperature Range: C = 0°C to +70°C (PDIP and SOIC only)E = -40°C to +85°CV = -40°C to +125°C
Package: MF = Dual, Flat, No-Lead (6X5 mm Body), 8-leadMF713 = Dual, Flat, No-Lead (6X5 mm Body), 8-lead
(Tape and Reel)OA = Plastic SOIC, (150 mil Body), 8-leadOA713 = Plastic SOIC, (150 mil Body), 8-lead
(Tape and Reel)PA = Plastic DIP (300 mil Body), 8-leadUA = Plastic Micro Small Outline (MSOP), 8-leadUA713 = Plastic Micro Small Outline (MSOP), 8-lead
(Tape and Reel)
PB Free: G = Lead-Free device *= Blank
* Available on selected packages. Contact your local sales representative for availability.
Examples:
a) TC4426COA: 1.5A Dual InvertingMOSFET driver,0°C to +70°CSOIC package.
b) TC4426EUA: 1.5A Dual InvertingMOSFET driver,-40°C to +85°C.MSOP package.
c) TC4426EMF: 1.5A Dual InvertingMOSFET driver,-40°C to +85°C,DFN package.
a) TC4427CPA: 1.5A Dual Non-InvertingMOSFET driver,0°C to +70°CPDIP package.
b) TC4427EPA: 1.5A Dual Non-InvertingMOSFET driver,-40°C to +85°CPDIP package.
a) TC4428COA713:1.5A Dual ComplementaryMOSFET driver,0°C to +70°C,SOIC package,Tape and Reel.
b) TC4428EMF: 1.5A Dual Complementary,MOSFET driver,-40°C to +85°CDFN package.
PART NO. X XX
PackageTemperatureRange
Device
XXX
Tape & Reel
X
PB Free
Data SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-72773. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification SystemRegister on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc. DS21422C-page 17
TC4426/TC4427/TC4428
NOTES:
DS21422C-page 18 2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding deviceapplications and the like is intended through suggestion onlyand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.No representation or warranty is given and no liability isassumed by Microchip Technology Incorporated with respectto the accuracy or use of such information, or infringement ofpatents or other intellectual property rights arising from suchuse or otherwise. Use of Microchip’s products as criticalcomponents in life support systems is not authorized exceptwith express written approval by Microchip. No licenses areconveyed, implicitly or otherwise, under any intellectualproperty rights.
2004 Microchip Technology Inc.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
DS21422C-page 19
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS21422C-page 20 2004 Microchip Technology Inc.
AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: 480-792-7627Web Address: www.microchip.com
AtlantaAlpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307
BostonWestford, MA Tel: 978-692-3848 Fax: 978-692-3821
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ASIA/PACIFICAustralia - SydneyTel: 61-2-9868-6733 Fax: 61-2-9868-6755
China - BeijingTel: 86-10-8528-2100 Fax: 86-10-8528-2104
China - ChengduTel: 86-28-8676-6200 Fax: 86-28-8676-6599
China - FuzhouTel: 86-591-750-3506 Fax: 86-591-750-3521
China - Hong Kong SARTel: 852-2401-1200 Fax: 852-2401-3431
China - ShanghaiTel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - ShenzhenTel: 86-755-8290-1380 Fax: 86-755-8295-1393
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China - QingdaoTel: 86-532-502-7355 Fax: 86-532-502-7205
ASIA/PACIFICIndia - BangaloreTel: 91-80-2229-0061 Fax: 91-80-2229-0062
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SingaporeTel: 65-6334-8870 Fax: 65-6334-8850
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Taiwan - TaipeiTel: 886-2-2500-6610 Fax: 886-2-2508-0102
Taiwan - HsinchuTel: 886-3-572-9526Fax: 886-3-572-6459
EUROPEAustria - WeisTel: 43-7242-2244-399Fax: 43-7242-2244-393Denmark - BallerupTel: 45-4420-9895 Fax: 45-4420-9910
France - MassyTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
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England - BerkshireTel: 44-118-921-5869Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
08/24/04
©2002 Fairchild Semiconductor Corporation
IRF540N Rev. C
IRF540N
33A, 100V, 0.040 Ohm, N-Channel, Power MOSFET
Packaging
Symbol
Features
• Ultra Low On-Resistance- r
DS(ON)
= 0.040
Ω,
V
GS
=
10V
• Simulation Models- Temperature Compensated PSPICE™ and SABER
©
Electrical Models
- Spice and SABER
©
Thermal Impedance Models- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
JEDEC TO-220AB
DRAIN (FLANGE)
DRAINSOURCE
GATE
IRF540N
D
G
S
PART NUMBER PACKAGE BRAND
IRF540N TO-220AB IRF540N
IRF540N UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
100 V
Drain to Gate Voltage (R
GS
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
100 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
20 V
Drain CurrentContinuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
3323
Figure 4
AA
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1200.80
WW/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for SolderingLeads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300260
o
C
o
C
NOTES:
1. T
J
= 25
o
C to 150
o
C.
CAUTION:
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet January 2002
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V (Figure 11) 100 - - V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 95V, V
GS
= 0V - - 1
µ
A
V
DS
= 90V, V
GS
= 0V, T
C
= 150
o
C - - 250
µ
A
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V - -
±
100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 10) 2 - 4 V
Drain to Source On Resistance r
DS(ON)
I
D
= 33A, V
GS
= 10V (Figure 9) - 0.033 0.040
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case R
θ
JC
TO-220 - - 1.25
o
C/W
Thermal Resistance Junction to Ambient
R
θ
JA
- - 62
o
C/W
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time t
ON
V
DD
= 50V, I
D
= 33AV
GS
=
10V,R
GS
= 9.1
Ω
(Figures 18, 19)
- - 100 ns
Turn-On Delay Time t
d(ON)
- 9.5 - ns
Rise Time t
r
- 57 - ns
Turn-Off Delay Time t
d(OFF)
- 40 - ns
Fall Time t
f
- 55 - ns
Turn-Off Time t
OFF
- - 145 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q
g(TOT)
V
GS
= 0V to 20V V
DD
= 50V,I
D
= 33A,I
g(REF)
= 1.0mA
(Figures 13, 16, 17)
- 66 79 nC
Gate Charge at 10V Q
g(10)
V
GS
= 0V to 10V - 35 42 nC
Threshold Gate Charge Q
g(TH)
V
GS
= 0V to 2V - 2.4 2.9 nC
Gate to Source Gate Charge Q
gs
- 5.4 - nC
Gate to Drain "Miller" Charge Q
gd
- 13 - nC
CAPACITANCE SPECIFICATIONS
Input Capacitance C
ISS
V
DS
= 25V, V
GS
= 0V,f = 1MHz(Figure 12)
- 1220 - pF
Output Capacitance C
OSS
- 295 - pF
Reverse Transfer Capacitance C
RSS
- 100 - pF
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
SD
I
SD
= 33A - - 1.25 V
I
SD
= 17A - - 1.00 V
Reverse Recovery Time t
rr
I
SD
= 33A, dI
SD
/dt = 100A/
µ
s - - 112 ns
Reverse Recovered Charge Q
RR
I
SD
= 33A, dI
SD
/dt = 100A/
µ
s - - 400 nC
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
PO
WE
R D
ISS
IPA
TIO
N M
ULT
IPL
IER
00 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
20
30
40
50 75 100 125 1500
25
I D, D
RA
IN C
UR
RE
NT
(A
)
TC, CASE TEMPERATURE (oC)
VGS = 10V
175
10
0.1
1
2
10-4 10-3 10-2 10-1 100 1010.01
10-5
t, RECTANGULAR PULSE DURATION (s)
ZθJ
C, N
OR
MA
LIZ
ED
TH
ER
MA
L IM
PE
DA
NC
E
SINGLE PULSENOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER0.50.20.10.05
0.010.02
100
600
20
10-4 10-3 10-2 10-1 100 10110-5
I DM
, PE
AK
CU
RR
EN
T (
A)
t , PULSE WIDTH (s)
TRANSCONDUCTANCEMAY LIMIT CURRENTIN THIS REGION
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURESABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:
VGS = 10V
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
10
100
10 300
300
1
1
100µs
10ms
1ms
VDS, DRAIN TO SOURCE VOLTAGE (V)
I D, D
RA
IN C
UR
RE
NT
(A
)
LIMITED BY rDS(ON)AREA MAY BEOPERATION IN THIS
TJ = MAX RATEDTC = 25oC
SINGLE PULSE
100
100
200
0.001 0.01 0.1 1
I AS
, AVA
LA
NC
HE
CU
RR
EN
T (
A)
tAV, TIME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)If R = 0
If R ≠ 0tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
10
0
20
40
60
2 3 4 6
I D, D
RA
IN C
UR
RE
NT
(A
)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µsDUTY CYCLE = 0.5% MAXVDD = 15V
TJ = 175oC
TJ = 25oC
TJ = -55oC
5
0
20
40
60
0 1 2 3 4
I D, D
RA
IN C
UR
RE
NT
(A
)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS =5V
PULSE DURATION = 80µsDUTY CYCLE = 0.5% MAX TC = 25oC
VGS = 7VVGS = 6V
VGS = 20VVGS = 10V
0.5
1.0
1.5
2.0
3.0
-80 -40 0 40 80 120 200
NO
RM
AL
IZE
D D
RA
IN T
O S
OU
RC
E
TJ, JUNCTION TEMPERATURE (oC)
ON
RE
SIS
TAN
CE
VGS = 10V, ID = 33APULSE DURATION = 80µsDUTY CYCLE = 0.5% MAX
160
2.5
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 200
NO
RM
AL
IZE
D G
AT
E
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
TH
RE
SH
OL
D V
OLT
AG
E
160
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves (Continued)
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 200
TJ, JUNCTION TEMPERATURE (oC)
NO
RM
AL
IZE
D D
RA
IN T
O S
OU
RC
EB
RE
AK
DO
WN
VO
LTA
GE
ID = 250µA
16016020
100
1000
4000
0.1 1.0 10 100
C, C
APA
CIT
AN
CE
(p
F)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≅ CDS + CGD
0
2
4
6
8
10
0 10 20 30 40
VG
S, G
AT
E T
O S
OU
RC
E V
OLT
AG
E (
V)
VDD = 50V
Qg, GATE CHARGE (nC)
ID = 33AID = 17A
WAVEFORMS INDESCENDING ORDER:
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDDRG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS90%
10%
tf
td(OFF)
tOFF
90%
50%50%
10%PULSE WIDTH
VGS
0
0
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
PSPICE Electrical Model .SUBCKT IRF540N 2 1 3 ; rev 19 July 1999
CA 12 8 1.95e-9CB 15 14 1.90e-9CIN 6 8 1.12e-9
DBODY 7 5 DBODYMODDBREAK 5 11 DBREAKMODDPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 112.8EDS 14 8 5 8 1EGS 13 8 6 8 1ESG 6 10 6 8 1EVTHRES 6 21 19 8 1EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9LGATE 1 9 6.19e-9LSOURCE 3 7 2.18e-9
MMED 16 6 8 8 MMEDMODMSTRO 16 6 8 8 MSTROMODMWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1RDRAIN 50 16 RDRAINMOD 2.00e-2RGATE 9 20 1.77RLDRAIN 2 5 10RLGATE 1 9 26RLSOURCE 3 7 11RSLC1 5 51 RSLCMOD 1e-6RSLC2 5 50 1e3RSOURCE 8 7 RSOURCEMOD 6.5e-3RVTHRES 22 8 RVTHRESMOD 1RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMODS1B 13 12 13 8 S1BMODS2A 6 15 14 13 S2AMODS2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE=(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*71),3.5))
.MODEL DBODYMOD D (IS = 1.20e-12 RS = 4.2e-3 XTI = 5 TRS1 = 1.3e-3 TRS2 = 8.0e-6 CJO = 1.50e-9 TT = 7.47e-8 M = 0.63)
.MODEL DBREAKMOD D (RS = 4.2e-1 TRS1 = 8e-4 TRS2 = 3e-6)
.MODEL DPLCAPMOD D (CJO = 1.45e-9 IS = 1e-30 M = 0.82)
.MODEL MMEDMOD NMOS (VTO = 3.11 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.77)
.MODEL MSTROMOD NMOS (VTO = 3.57 KP = 33.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.68 KP = 0.09 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 17.7 )
.MODEL RBREAKMOD RES (TC1 =1.05e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 9.40e-3 TC2 = 2.93e-5)
.MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 2.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -8.6e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.0e-3 TC2 =1.5e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.2 VOFF= -3.1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.1 VOFF= -6.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
1822
+ -
68
+
-
551
+
-
198
+ -
1718
68
+
-
58 +
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
138
1413
MWEAK
EBREAKDBODY
RSOURCE
SOURCE
11
7 3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 1621
8
MMED
MSTRO
DRAIN2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE20
+
-
+
-
+
-
6
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
SABER Electrical Model REV 19 July 1999
template IRF540N n2,n1,n3electrical n2,n1,n3var i iscld..model dbodymod = (is = 1.20e-12, cjo = 1.50e-9, tt = 7.47e-8, xti = 5, m = 0.63)d..model dbreakmod = ()d..model dplcapmod = (cjo = 1.45e-9, is = 1e-30, m = 0.82)m..model mmedmod = (type=_n, vto = 3.11, kp = 5, is = 1e-30, tox = 1)m..model mstrongmod = (type=_n, vto = 3.57, kp = 33.5, is = 1e-30, tox = 1)m..model mweakmod = (type=_n, vto = 2.68, kp = 0.09, is = 1e-30, tox = 1)sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -3.1)sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3.1, voff = -6.2)sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5)sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0)
c.ca n12 n8 = 1.95e-9c.cb n15 n14 = 1.90e-9c.cin n6 n8 = 1.12e-9
d.dbody n7 n71 = model=dbodymodd.dbreak n72 n11 = model=dbreakmodd.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9l.lgate n1 n9 = 6.19e-9l.lsource n3 n7 = 2.18e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1um.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1um.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5.0e-7res.rdbody n71 n5 = 4.2e-3, tc1 = 1.30e-3, tc2 = 8.0e-6res.rdbreak n72 n5 = 4.2e-1, tc1 = 8.0e-4, tc2 = 3.0e-6res.rdrain n50 n16 = 2.00e-2, tc1 = 9.40e-3, tc2 = 2.93e-5res.rgate n9 n20 = 1.77res.rldrain n2 n5 = 10res.rlgate n1 n9 = 26res.rlsource n3 n7 = 11res.rslc1 n5 n51 = 1e-6, tc1 = 3.5e-3, tc2 = 2.0e-6res.rslc2 n5 n50 = 1e3res.rsource n8 n7 = 6.5e-3, tc1 = 1e-3, tc2 = 1e-6res.rvtemp n18 n19 = 1, tc1 = -3.0e-3, tc2 = 1.5e-7res.rvthres n22 n8 = 1, tc1 = -1.8e-3, tc2 = -8.6e-6
spe.ebreak n11 n7 n17 n18 = 112.8spe.eds n14 n8 n5 n8 = 1spe.egs n13 n8 n6 n8 = 1spe.esg n6 n10 n6 n8 = 1spe.evtemp n20 n6 n18 n22 = 1spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amodsw_vcsp.s1b n13 n12 n13 n8 = model=s1bmodsw_vcsp.s2a n6 n15 n14 n13 = model=s2amodsw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations i (n51->n50) +=iscliscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/71))** 3.5))
1822
+ -
68
+
-
198
+ -
1718
68
+
-
58 +
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
138
1413
MWEAK
EBREAKDBODY
RSOURCE
SOURCE
11
7 3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 1621
8
MMED
MSTRO
DRAIN2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
IRF540N
©2002 Fairchild Semiconductor Corporation IRF540N Rev. C
SPICE Thermal Model
REV 26 July 1999
IRF540NT
CTHERM1 th 6 2.60e-3CTHERM2 6 5 8.85e-3CTHERM3 5 4 7.60e-3CTHERM4 4 3 7.65e-3CTHERM5 3 2 1.22e-2CTHERM6 2 tl 8.70e-2
RTHERM1 th 6 9.00e-3RTHERM2 6 5 1.80e-2RTHERM3 5 4 9.15e-2RTHERM4 4 3 2.43e-1RTHERM5 3 2 3.10e-1RTHERM6 2 tl 3.21e-1
SABER Thermal ModelSABER thermal model IRF540NT
template thermal_model th tlthermal_c th, tlctherm.ctherm1 th 6 = 2.60e-3ctherm.ctherm2 6 5 = 8.85e-3ctherm.ctherm3 5 4 = 7.60e-3ctherm.ctherm4 4 3 = 7.65e-3ctherm.ctherm5 3 2 = 1.22e-2ctherm.ctherm6 2 tl = 8.70e-2
rtherm.rtherm1 th 6 = 9.00e-3rtherm.rtherm2 6 5 = 1.80e-2rtherm.rtherm3 5 4 = 9.15e-2rtherm.rtherm4 4 3 = 2.43e-1rtherm.rtherm5 3 2 = 3.10e-1rtherm.rtherm6 2 tl = 3.21e-1
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
IRF540N
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHERNOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILDDOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCTOR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and isnot intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, or (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can bereasonably expected to result in significant injury to theuser.
2. A critical component is any component of a lifesupport device or system whose failure to perform canbe reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety oreffectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications forproduct development. Specifications may change inany manner without notice.
This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.
This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design.
This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.
Formative orIn Design
First Production
Full Production
Not In Production
OPTOLOGIC™OPTOPLANAR™PACMAN™POP™Power247™PowerTrenchQFET™QS™QT Optoelectronics™Quiet Series™SILENT SWITCHER
FASTFASTr™FRFET™GlobalOptoisolator™GTO™HiSeC™ISOPLANAR™LittleFET™MicroFET™MicroPak™MICROWIRE™
Rev. H4
ACEx™Bottomless™CoolFET™CROSSVOLT™DenseTrench™DOME™EcoSPARK™E2CMOSTM
EnSignaTM
FACT™FACT Quiet Series™
SMART START™STAR*POWER™Stealth™SuperSOT™-3SuperSOT™-6SuperSOT™-8SyncFET™TinyLogic™TruTranslation™UHC™UltraFET
STAR*POWER is used under license
VCX™
UF4001 - U
F4007
UF4001-UF4007, Rev. C2001 Fairchild Semiconductor Corporation
UF4001 - UF4007
Fast Rectifiers (Glass Passivated)
Absolute Maximum Ratings* TA = 25°C unless otherwise noted
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
Electrical Characteristics TA = 25°C unless otherwise noted
Features• Low forward voltage drop.
• High surge current capability.
• High reliability.
• High current capability. DO-41COLOR BAND DENOTES CATHODE
Thermal Characteristics
Symbol
Parameter
Device
Units 4001 4002 4003 4004 4005 4006 4007
VF Forward Voltage @ 1.0 A 1.0 1.7 V trr Reverse Recovery Time
IF = 0.5 A, IR= 1.0 A, IRR = 0.25 A 50 75 ns
IR Reverse Current @ rated VR TA = 25°C TA = 100°C
10 50
µA µA
CT Total Capacitance VR = 4.0 V, f = 1.0 MHz 17 pF
Symbol
Parameter
Value
Units 4001 4002 4003 4004 4005 4006 4007
VRRM Maximum Repetitive Reverse Voltage 50 100 200 400 600 800 1000 V IF(AV) Average Rectified Forward Current,
.375 " lead length @ TA = 75°C 1.0 A
IFSM Non-repetitive Peak Forward Surge Current 8.3 ms Single Half-Sine-Wave 30 A
Tstg Storage Temperature Range -65 to +150 °C TJ Operating Junction Temperature -65 to +150 °C
Symbol
Parameter
Value
Units PD Power Dissipation 2.08 W RθJA Thermal Resistance, Junction to Ambient 60 °C/W RθJL Thermal Resistance, Junction to Lead 15 °C/W
UF4001 - U
F4007
UF4001-UF4007, Rev. C2001 Fairchild Semiconductor Corporation
Typical Characteristics
PulseGenerator(Note 2)
50ΩNONINDUCTIVE
50ΩNONINDUCTIVE
DUT(-)
(+)OSCILLOSCOPE(Note 1)
50ΩNONINDUCTIVE
50V(approx)
NOTES:1. Rise time = 7.0 ns max; Input impedance = 1.0 megaohm 22 pf.2. Rise time = 10 ns max; Source impedance = 50 ohms.
Reverse Recovery Time Characterstic and Test Circuit Diagram
0 25 50 75 100 125 150 1750
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Ambient Temperature [ºC]Ave
rage
Rec
tifie
d Fo
rwar
d C
urre
nt, I
F [A
]
SINGLE PHASE HALF WAVE 60HZ RESISTIVE OR INDUCTIVE LOAD .375" (9.00mm) LOAD LENGTHS
1 2 5 10 20 50 1000
10
20
30
40
Number of Cycles at 60Hz
Peak
For
war
d Su
rge
Cur
rent
, IFS
M [
A]
0.1 0.5 1 2 5 10 20 50 100 5000
10
20
30
40
50
60
Reverse Voltage, VR [V]
Tota
l Cap
acita
nce,
CT
[pF]
UF4004-UF4007
UF4001-UF4003
0.2 0.4 0.6 0.8 1 1.2 1.40.001
0.01
0.1
1
10
Forward Voltage, VF [V]
Forw
ard
Cur
rent
, IF
[A]
T = 25 C ºJ Pulse Width = 300µµµµS 2% Duty Cycle
T = 25 C ºA
UF4001-UF4003 UF4005-UF4007
UF4004
1.0cm SET TIME BASE FOR
trr +0.5A
0
-0.25A
-1.0A 5/ 10 ns/ cm
0 20 40 60 80 100 120 1400.1
1
10
100
1000
Percent of Rated Peak Reverse Voltage [%]
Reve
rse
Curre
nt, I
R [m
A]
T = 25 C ºJ T = 25 C ºA
T = 125 C ºA
Figure 1. Forward Current Derating Curve Figure 2. Forward Voltage Characteristics
Figure 3. Non-Repetitive Surge Current Figure 4. Reverse Current vs Reverse Voltage
Figure 5. Total Capacitance
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHERNOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILDDOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCTOR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and isnot intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, or (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can bereasonably expected to result in significant injury to theuser.
2. A critical component is any component of a lifesupport device or system whose failure to perform canbe reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety oreffectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications forproduct development. Specifications may change inany manner without notice.
This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.
This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design.
This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.
Formative orIn Design
First Production
Full Production
Not In Production
OPTOLOGIC™OPTOPLANAR™PACMAN™POP™Power247™PowerTrenchQFET™QS™QT Optoelectronics™Quiet Series™SILENT SWITCHER
FASTFASTr™FRFET™GlobalOptoisolator™GTO™HiSeC™ISOPLANAR™LittleFET™MicroFET™MicroPak™MICROWIRE™
Rev. H4
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VCX™
UF5400 thru UF5408Vishay Semiconductorsformerly General Semiconductor
Document Number 88756 www.vishay.com14-Feb-02 1
Ultrafast Plastic RectifierReverse Voltage 50 to 1000V
Forward Current 3.0A
Maximum Ratings & Thermal Characteristics Ratings at 25°C ambient temperature unless otherwise specified.
UF UF UF UF UF UF UF UF UFParameter Symbols 5400 5401 5402 5403 5404 5405 5406 5407 5408 Units
Maximum repetitive peak reverse voltage VRRM 50 100 200 300 400 500 600 800 1000 V
Maximum RMS voltage VRMS 35 70 140 210 280 350 420 560 700 V
Maximum DC blocking voltage VDC 50 100 200 300 400 500 600 800 1000 V
Maximum average forward rectified current,0.375" (9.5mm) lead length at TA=55°C IF(AV) 3.0 A
Peak forward surge current8.3ms single half sine-wave superimposed IFSM 150 Aon rated load (JEDEC Method) at TA=55°C
Typical thermal resistance (1) RΘJA 20RΘJL 8.5 °C/W
Operating junction and storage temperature range TJ, TSTG -55 to +150 °C
Electrical Characteristics Ratings at 25°C ambient temperature unless otherwise specified.
UF UF UF UF UF UF UF UF UFParameter Symbols 5400 5401 5402 5403 5404 5405 5406 5407 5408 Units
Maximum instantaneous forward voltage at 3.0A (2) VF 1.0 1.7 V
Maximum DC reverse current TA = 25°C 10at rated DC blocking voltage TA =100°C IR 75 200 µA
Maximum reverse recovery time at IF = 0.5A, IR = 1.0A, Irr = 0.25A TJ = 25°C trr 50 75 ns
Typical junction capacitance at 4.0V, 1MHz CJ 45 36 pF
Notes:(1) Thermal resistance from junction to lead and from junction to ambient with 0.375" (9.5mm) lead length, both leads attached to heatsink(2) Pulse test: 300µs pulse width, 1% duty cycle
Dimensions in inches and (millimeters)
Features• Plastic package has Underwriters Laboratories
Flammability Classification 94V-0• Glass passivated chip junction• Low cost• Ultrafast recovery time for high efficiency• Low forward voltage, high current capability• Low leakage• High surge capability• High temperature soldering guaranteed:
250°C, 0.375" (9.5mm) lead length for 10 seconds,5 lbs. (2.3kg) tension
Mechanical DataCase: JEDEC DO-201AD molded plastic body overpassivated chipTerminals: Plated axial leads, solderable perMIL-STD-750, Method 2026Polarity: Color band denotes cathode endMounting Position: AnyWeight: 0.04 oz., 1.1 g
0.210 (5.3)0.190 (4.8)
Dia.
0.052 (1.32)0.048 (1.22)
Dia.
1.0 (25.4)Min.
0.375 (9.5)0.285 (7.2)
1.0 (25.4)Min.
DO-201AD
UF5400 thru UF5408Vishay Semiconductorsformerly General Semiconductor
www.vishay.com Document Number 887562 14-Feb-02
Ratings and Characteristic Curves (TA = 25°C unless otherwise noted)
Ambient Temperature (°C)
Fig. 1 – Maximum Forward CurrentDerating Curve
Ave
rage
For
war
d R
ectif
ied
Cur
rent
(A
)
Fig. 3 – Typical Instantaneous Forward Characteristics
Instantaneous Forward Voltage (V)
Inst
anta
neou
s F
orw
ard
Cur
rent
(A
)
Percent of Rated Peak Reverse Voltage (%)
Inst
anta
neou
s R
ever
se L
eaka
ge
Cur
rent
(µA
)
Fig. 4 – Typical Reverse Leakage Characteristics
Number of Cycles at 60 HZ
Fig. 2 – Maximum Non-Repetitive Peak Forward Surge Current
Pea
k F
orw
ard
Sur
ge C
urre
nt (
A)
Reverse Voltage (V)
Junc
tion
Cap
acita
nce
(pF
)
Fig. 5 – Typical JunctionCapacitance
20 40 60 80 100 120 140 1600
0.5
1.0
1.5
2.0
2.5
3.0
Resistive orInductive Load
Lead Length = 0.375" (9.5mm)
1 10 1000
25
50
75
100
125
150 TA = 55°C 8.3ms Single Half Sine-Wave (JEDEC Method)
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.01
0.1
1
10
100
TJ = 25°CPulse Width = 300µs1% Duty Cycle
UF5400 - UF5404
UF5405 - UF5408
0 20 40 60 80 1000.01
0.1
1
10
100
0.1 1 10 10020
40
60
80
100
120
140
160TJ = 25°Cf = 1.0MHZVsig = 50MVp-p
UF5400 - UF5404UF5405 - UF5408
TJ = 25°C
TJ = 100°C
TJ = 125°C
TJ = 100°C
TJ = 125°C
UF5400 - UF5404UF5405 - UF5408