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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 1
Memory organization
Memory test complexity
Faults and fault models
MATS+ march test
Address Decoder faults
Summary
References
Lecture 14altMemory Test(Alternative for Lecture 15)
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 2
RAM Organization
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 3
Test Time in Seconds(Memory Cycle Time 60ns)n bits
1 Mb4 Mb
16 Mb
64 Mb256 Mb
1 Gb2 Gb
n
0.060.251.01
4.0316.1164.43128.9
n log2
n
1.265.54
24.16
104.7451.01932.83994.4
n3/2
64.5515.41.2 hr
9.2 hr73.3 hr
586.4 hr1658.6 hr
n2
18.3 hr293.2 hr
4691.3 hr
75060.0 hr1200959.9 hr
19215358.4 hr76861433.7 hr
Size Number of Test Algorithm Operations
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 4
SRAM Fault ModelingExamples
SA0
AF+
SAF
SAF
SCF SCFSA0
SA0TFTF
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 5
DRAM Fault Modeling
ANDBridging
Fault (ABF)
SA1+SCFSA1
ABF
SCFSA0
ABF
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 6
SRAM Only Fault Models
Faults found only in SRAMOpen-circuited pull-up deviceExcessive bit line coupling capacitance
ModelDRFCF
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 7
DRAM Only Fault ModelsFaults only in DRAMData retention fault (sleeping sickness)
Refresh line stuck-at faultBit-line voltage imbalance faultCoupling between word and bit lineSingle-ended bit-line voltage shift
Precharge and decoder clock overlap
ModelDRF
SAFPSFCF
PSF
AF
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 8
Reduced FunctionalFaults
SAFTFCFNPSF
Fault
Stuck-at faultTransition faultCoupling faultNeighborhood Pattern Sensitive fault
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 9
Stuck-at Faults
Test Condition: For each cell, read a 0 and a 1. < / 0 > (< / 1 >)
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 10
Transition Faults Cell fails to make a 0 1 or 1 0 transition.
Test Condition: Each cell must have an transition
and a transition, and be read each time before
making any further transitions. < / 0 >, < / 1 >
< / 0 > transition fault
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 11
Coupling Faults Coupling Fault(CF): Transition in bitj(aggressor)
causes unwanted change in bit i(victim)
2-Coupling Fault: Involves 2 cells, special case ofk-Coupling Fault
Must restrict kcells for practicality
Inversion(CFin)and Idempotent(CFid) CouplingFaults special cases of 2-Coupling Faults
Bridgingand State Coupling Faultsinvolve any # ofcells
Dynamic Coupling Fault(CFdyn) read or write onjforces ito 0 or 1
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 12
State Transition Diagramof Two Good Cells, i and j
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 13
State Transition Diagramfor CFin < ; >
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 14
State Coupling Faults (SCF) Aggressor cell or linej is in a given state yand that
forces victim cell or linei into state x
< 0;0 >, < 0;1 >, < 1;0 >, < 1;1 >
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 15
March Test ElementsM0: { March element (w0) }
for cell := 0 to n - 1 (or any other order) do
write 0 to A [cell];
M1: { March element (r0, w1) }
for cell := 0 to n - 1 do
read A [cell]; { Expected value = 0}
write 1 to A [cell];
M2: { March element (r1, w0) }
for cell := n 1 down to 0 do
read A [cell]; { Expected value = 1 }
write 0 to A [cell];
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 16
March TestsAlgorithm
MATSMATS+
MATS++
MARCH X
MARCH C-
MARCH A
MARCH Y
MARCH B
Description
{ (w0); (r0, w1); (r1) }{ (w0); (r0, w1); (r1, w0) }
{ (w0); (r0, w1); (r1, w0, r0) }
{ (w0); (r0, w1); (r1, w0); (r0) }
{ (w0); (r0, w1); (r1, w0);(r0, w1); (r1, w0); (r0) }
{ (w0); (r0, w1, w0, w1); (r1, w0, w1);
(r1, w0, w1, w0); (r0, w1, w0) }
{ (w0); (r0, w1, r1); (r1, w0, r0); (r0) }{ (w0); (r0, w1, r1, w0, r0, w1);
(r1, w0, w1); (r1, w0, w1, w0);
(r0, w1, w0) }
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 17
Address Decoder Faults(ADFs) Address decoding error assumptions:
Decoder does not become sequential
Same behavior during both read and write
Multiple ADFs must be tested for
Decoders can have CMOS stuck-open faults
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 18
Theorem A March test satisfying conditions 1 & 2 detects all
address decoder faults.
... Means any # of read or write operations
Before condition 1, must have wxelement xcan be 0 or 1, but must be consistent in test
Condition
1
2
March element
(rx, , w x )
(r x , , wx)
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 19
March Test Fault CoverageAlgorithm
MATSMATS+MATS++MARCH XMARCH C-
MARCH AMARCH YMARCH B
SAF
AllAllAllAllAll
AllAllAll
ADF
SomeAllAllAllAll
AllAllAll
TF
AllAllAll
AllAllAll
CFin
AllAll
AllAllAll
CFid
All
CFdyn
All
SCF
All
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 20
March Test ComplexityAlgorithm
MATS
MATS+MATS++MARCH XMARCH C-MARCH AMARCH YMARCH B
Complexity4n
5n6n6n
10n15n8n
17n
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 21
MATS+ ExampleCell (2,1) SA0 Fault
MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 22
MATS+ ExampleCell (2, 1) SA1 Fault
MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 23
MATS+ ExampleMultiple AF: Addressed Cell NotAccessed; Data Written to Wrong Cell
Cell (2,1) is not addressable Address (2,1) maps onto (3,1), and vice versa Cannot write (2,1), read (2,1) gives random data
MATS+: { M0: (w0); M1: (r0, w1); M2: (r1), w0 }
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 24
Memory Test Summary Multiple fault models are essential
Combination of tests is essential:
March SRAM and DRAM
NPSF DRAM
DC Parametric Both
AC Parametric Both
Related areas of memory test
BIST standard practice for embedded memories
Repairable memories redundancy to enhance yield
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Copyright 2005, Agrawal & Bushnell VLSI Test: Lecture 14alt 25
References on Memory Test R. D. Adams, High Performance Memory Testing, Boston: Springer, 2002.
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing forDigital, Memory and Mixed-Signal VLSI Circuits, Boston: Springer, 2000.
K. Chakraborty and P. Mazumder, Fault Tolerance and ReliabilityTechniques for High-Density Random-Access Memories, Upper SaddleRiver, New Jersey: Prentice Hall PTR, 2002.
K. Chakraborty and P. Mazumder, Testing and Testable Design of High-
Density Random-Access Memories, Boston: Springer, 1996. D. Gizopoulos, editor, Advances in Electronic Testing Challenges and
Methodologies, Springer, 2006.
S. Hamdioui, Testing Static Random Access Memories: Defects, FaultModels and Test Patterns, Springer, 2004.
B. Prince, High Performance Memories, Revised Edition, Wiley, 1999.
A. K. Sharma, Semiconductor Memories: Testing Technology, andReliability, Piscataway, New Jersey: IEEE Press, 1997.
A. J. van de Goor, Testing Semiconductor Memories, Chichester, UK:Wiley Interscience, 1991, reprinted by ComTex, Gouda, The Netherlands(http://ce.et.tudelft.nl/vdgoor/).