P. J. TimansJTG Meeting, 2 February 2011
IEDM 2010 Short Course15nm CMOS
Innovation • Speed • Solutions2/10/2011 -- 1
Short Course Contents
• Course Organized by Kelin Kuhn, Intel• Presenters
– CMOS Technologies – Trends, Scaling and Issues (Thomas Skotnicki, ST)
– 15nm Device Challenges and Solutions (Mukesh Khare, IBM)– Lithography for the 15nm Technology Node (Sam Sivakumar,
Intel)– BEOL Technology toward the 15nm Technology Node
(Yoshihiro Hayashi, Renesas)– Device/Circuit Interactions at the 15nm Technology Node (Clive
Bittlestone, TI)
• Here we’ll focus on the 1st two tutorials
2/10/2011 -- 1
Innovation • Speed • Solutions2/10/2011 -- 2
Metrics for Success in Scaling
• Switching performance dominated by dynamic characteristics: Ieff metric, which depends on DIBL
• DIBL metric is especially relevant to low power applications
Innovation • Speed • Solutions2/10/2011 -- 3
Bulk Scaling Limit
• Limited scope for scaling planar device• Improvement possible through μ boost
– BUT - much of the feasible boost has already been used up
Innovation • Speed • Solutions2/10/2011 -- 4
III-V Channel: Hard to Scale & Keep Performance
Innovation • Speed • Solutions2/10/2011 -- 5
Fully-Depleted Devices Improve DIBL
Innovation • Speed • Solutions2/10/2011 -- 6
Performance Comparisons
Innovation • Speed • Solutions2/10/2011 -- 7
T. Skotnicki: Advocating Planar FDSOI
Innovation • Speed • Solutions2/10/2011 -- 8
M. Khare: Illustration of 15nm CMOS
Innovation • Speed • Solutions2/10/2011 -- 9
Scaling Challenges
Innovation • Speed • Solutions2/10/2011 -- 10
Gate Dielectric Scaling Has to Continue
Innovation • Speed • Solutions2/10/2011 -- 11
Junction Depths Have to Scale Too
Innovation • Speed • Solutions2/10/2011 -- 12
Underlap Optimization
Innovation • Speed • Solutions2/10/2011 -- 13
Vt Variability can be Improved
Innovation • Speed • Solutions2/10/2011 -- 14
Band-to-Band Tunnelling Issue for Low Power
Innovation • Speed • Solutions2/10/2011 -- 15
Pitch-Scaling: Loss of Strain
Innovation • Speed • Solutions2/10/2011 -- 16
SOI Progressing to Fully-Depleted Mode
Innovation • Speed • Solutions2/10/2011 -- 17
Finfets / Trigates: Parasitics Challenges
Innovation • Speed • Solutions2/10/2011 -- 18
Effort Continues to Reduce EOT
Innovation • Speed • Solutions2/10/2011 -- 19
Interface Layer Scaling
Innovation • Speed • Solutions2/10/2011 -- 20
M. Khare (IBM) - Conclusions