130
15.28 (contd)
Present State
Next StateW = 0 1
Output 0 1
S0 S0 S0 0 0S2 S4 S7 1 0S4 S7 S6 0 0S6 S2 S4 0 0S7 S6 S2 0 0
Present State
Next StateW = 0 1
Output 0 1
000 000 000 0 0100 111 101 1 0111 101 110 0 0110 100 111 0 0101 110 100 0 0
I. NoneII. (4, 7)ü (6, 7)ü (2, 4)ü (2, 6)ü Assignment:S0 = 000, S2 = 100, S4 = 111, S6 = 110, S7 = 101
15.29 By inspecting incoming arrows, we get:D0 = Q0
+ = X'Y'Q0 + XYQ3D1 = Q1
+ = XQ0 + Y'Q1 + XY'Q3D2 = Q2
+ = X'YQ0 + X'Q2 + X'YQ3D3 = Q3
+ = YQ1 + XQ2 + X'Y'Q3S = YQ1 + XQ2P = X'Y'Q3
By inspecting incoming arrows, we get:Q0
+ = D0 = X'YQ0 + Y'Q1 + X'YQ2Q1
+ = D1 = XY'Q0 + XYQ1 + Y'Q2Q2
+ = D2 = XYQ0 + X'Y'Q0 +X'YQ1 + XYQ2Z = X'YQ1 + XYQ2 + X'YQ2 = X'YQ1 + YQ2
15.30
S0
S2S1
S3
X'Y0
X0
XYS
XY'0
X'Y0XS
YS
P
Y'0
X'Y'
X'0
X'Y'0
S0
AB C 0 1
00
01
11
10
S2
S7
S4
S6
T input equations derived from the transition table using Karnaugh maps:TA = 0; TB = W'A; TC = WB + AB'; Z = W'AB'C'
Unit 16 Problem Solutions
16.15 See FLD p. 662 for solution.
16.17 (a) The state meanings are given in the following table:
Name MeaningS0 No 1’s have occurredS1 One 1 has occurred (an odd number < 2)S2 Two 1’s or an even number of 1’s > 2
have occurredS3 An odd number of 1’s > 2 has occurred.
16.16 See FLD p. 662 for solution.
1
1S31
S20
0
0S00
S10
00
1 1
16.1−16.14 See Lab Solutions in this manual.
131
i
i
xa
ax i
i'
'i+1a
ixai
i+1bib '
i+1bi+1a
Z
16.17 (b)
StateNext State
X = 0 X = 1 ZS0 S0 S1 0S1 S1 S2 0S2 S2 S3 0S3 S3 S2 1
I: (1, 3)II: (0, 1) (1, 2) (2, 3)Z
S0
0 10
1 S2
S1
S3
aibi
State aibi
ai+1bi+1X = 0 X = 1 Z
S0 00 00 10 0S1 10 10 01 0S2 01 01 11 0S3 11 11 01 1
xiai bi 0 1
00
01
11
10
0
0
1
1
1
1
0
0
ai+1 = xi'ai + xi ai'
ai+1 = xiai' + xi'ai
bi+1 = bi' + xiai
z = an+1bn+1
16.17 (c) Since no 1’s have occurred, a0 and b0 are the same as S0 or, a0 = 0; b0 = 0; ai = x0a0' + x0'a0 = x0; first cellbi = b0 + x0a0 = 0 }
OutputCircuitb
an+1
n+1Cell 1b
a1
1Cell nb
an
nCell 2b
a2
2 b
a3
3
x0 x1 x2 xn
0Z
16.17 (d)
xiai bi 0 1
00
01
11
10
0
1
0
1
0
1
1
1
bi+1 = bi + xi ai
Note: Solution on FLD p. 622 uses state assignment S0 = 00, S1 = 01, S2 = 10, S3 = 11.
16.18 (a) Ni = Qi+ = (Qi + FBi + CALLi)Ri' = QiRi' + FBiRi' + CALLiRi'
Clock
D
CallFB
RQ
ii
ii i Ni
132 133
16.18 (c) With the state assignment S0 = 00, S1 = 01, S2 = 10, S3 = 11, we have:D1 = FS2Q1'Q2 + FS1'Q1 + Q1Q2'; D2 = FS2'Q1'Q2 + FS1'Q1Q2 + N1'N2DCQ1'Q2' + N1N2'DCQ1Q2'R1 = FS1Q1Q2 + N1Q1'Q2'; R2 = FS2Q1'Q2 + N2Q1Q2'; UP =FS2'Q1'Q2 + N1'N2DCQ1'Q2'DOWN = FS1'Q1Q2 + N1N2'DCQ1Q2'; DO = FS2Q1'Q2 + FS1Q1Q2 + N1Q1'Q2' + N2Q1Q2'
16.19 (a)
S0000000
S7111111
S1001000
S2011000
S3111000
S6000111
S5000110
S4000100
L'R'H'H'H'
LH' LH' RH' RH'
L'H' LR'H'
L'H'
H -
H
H
H H
H
H
R'H'
L'RH' R'H'
Outputs: LC, LB, LA, RA, RB, RC
16.18 (b) Name MeaningS0 Staying on first floorS1 Moving from first to second floorS2 Staying on second floorS3 Moving from second to first floor
S0 S2
S1
S3
FS'2UP
FS2R2DO
N2R2DO,
N1N2'DC'0,N1'N2'
0N1N2'DC
DOWN
FS'1DOWN
N1R1DO,
N1'N2 DC'0,
N1'N2'0
N1'N2DCUP
FS1R1DO
16.19 (b) First, assign LC = Q1, LB = Q2, LA = Q3, RA = Q4, RB = Q5, RC = Q6. So S0 = 000000, S1 = 001000, S2 = 011000, etc.
This state machine has too many state variables to use Karnaugh maps. Instead, we will write down equations for each flip-flop by inspection.
First consider Q1. Q1 = 1 in states S3 or S7 only.• S7 is reached whenever H = 1 and we are not already in S7: H(Q1Q2Q3Q4Q5Q6)'. But S7 is the only state in which
both Q3 = 1 and Q4 = 1, so assuming we are always in a valid state, we can use H(Q3Q4)' = HQ3' + HQ4'. Note: Any combination of one left light and one right light will also work, i.e. HQ1' + HQ5'.
• S3 is reached whenever we are in S2 and L = 1 while H = 0: LH'Q1'Q2Q3Q4'Q5'Q6'. But Q3 = 1 whenever Q2 = 1, and Q4 = Q5 = Q6 = 0 whenever Q1 = 0. So we can use LH'Q1'Q2.
132 133
• So D1 = LH'Q1'Q2 + HQ3' + HQ4' = LQ1'Q2 + HQ3' + HQ4' (using X + X'Y = X + Y)Similarly Q2 = 1 in states S3, S2, and S7 only.
• S3 and S2 are reached whenever we are in S2 or S1 and L = 1 while H = 0.LH'Q1'Q2Q3Q4'Q5'Q6' + LH'Q1'Q2'Q3Q4'Q5'Q6' = LH'Q1'Q3Q4'Q5'Q6'But again, Q4 = Q5 = Q6 = 0 whenever Q1 = 0, so D2 = LQ1'Q3 + HQ3' + HQ4' We can also get by inspection: D3 = LQ1'Q4' + HQ3' + HQ4'; D4 = RQ3'Q6' + HQ3' + HQ4'; D5 = RQ4Q6' + HQ3' + HQ4'; D6 = RQ5Q6' + HQ3' + HQ4'
16.19 (b) (contd)
I. (S0, S1, S2, S3, S4, S5, S6) for S7 in LRH = 001, 011, 101(S1, S2, S3, S6, S7) for S0 in LRH = 010(S3, S4, S5, S6, S7) for S0 in LRH = 100
II. Every state matches S0 and S7. But S0 and S7 match the best, so (S0, S7)×(many times)III. (S1, S2, S3, S7) (S4, S5, S6, S7) etc.
From LogicAid:So D1 = HQ2 + RQ1Q2Q3' + HQ3 + LQ1'Q2'Q3 + HQ1' + RQ1'Q2'Q3' D2 = RH'Q1'Q2'Q3' + RH'Q1Q2 + LH'Q1'Q2'Q3'D3 = LH'Q1'Q2Q3' + LH'Q1'Q2'Q3 + RH'Q1Q2LC = Q1Q2'; LB = Q1Q2' + Q2'Q3 ; LA = Q1Q2' + Q2'Q3 + Q1'Q2Q3'RC = Q1Q2'Q3' + Q1'Q2Q3; RB = Q1Q2'Q3' + Q2Q3; RA = Q1Q3' + Q2Q3Other minimum solutions can be found for D2 and D3 with this assignment.
16.19 (c) State LRH = 000 001 010 011 100 101 110 111 LC LB LA RA RB RCS0 S0 S7 S4 S7 S1 S7 - - 0 0 0 0 0 0S1 S0 S7 S0 S7 S2 S7 - - 0 0 1 0 0 0S2 S0 S7 S0 S7 S3 S7 - - 0 1 1 0 0 0S3 S0 S7 S0 S7 S0 S7 - - 1 1 1 0 0 0S4 S0 S7 S5 S7 S0 S7 - - 0 0 0 1 0 0S5 S0 S7 S6 S7 S0 S7 - - 0 0 0 1 1 0S6 S0 S7 S0 S7 S0 S7 - - 0 0 0 1 1 1S7 S0 S0 S0 S0 S0 S0 - - 1 1 1 1 1 1
Q1Q2 Q3 0 1
00
01
11
10
S0
S2
S1
S6
S7
S3
S4
S5
134 135
16.21 (a) S21
S30 0,1
S00
S110
1
1
01
0
D Q1
D Q2
D Q3
PLA
Q1+
Q2+
Q3+
STREFFPLM
PRF
Clock
CK
CK
CK
D1 = ST' FF PS Q1' Q2' Q3 + ST' RE PL Q1' Q2' Q3 + ST' M Q1D2 = ST' FF Q1' Q2' Q3' + ST' RE Q1' Q2' Q3'
+ ST' RE' PL' Q2 Q3 + ST' FF' PL' Q2 Q3'D3 = ST' RE' FF Q1' Q2' Q3' + ST' RE' FF' Q3
+ ST' FF' PL Q2 Q3' + ST' RE' Q2 Q3 + ST' M' Q1 + ST' Q1 Q3 + ST' RE' PL Q1' Q2'
P = Q1'Q2'Q3; R = Q2Q3' + Q1Q3'; F = Q2Q3 + Q1Q3
16.20
IDLE0
PLAYP
FFWDF
SFWDF
SBACKR
REWR
RE' FF' PL'
ST ST
ST' M ST' M
ST' M' ST' M'
PL RE PL FF
ST' RE' FF'
PL PL
ST, FFST, RE
RE
FF
PL
ST, FF, RE
ST' FF' PL' ST' RE' PL'
Note: This state graph assumes that only one of the buttons ST, PL, RE, and FF can be pressed at any given time. The graph is incompletely specified and must be augmented before using LogicAid. For example, the arc from REW to PLAY should be labeled PL ST' FF'.
134 135
b
an+1
n+1Cell 1b
a1
1Cell nb
an
nCell 2b
a2
2 b
a3
3x0
x1 x2 xn
Z
16.21 (b)
16.21 (c)
16.21 (d)
xiai bi 0 1
00
01
11
10
0
0
1
1
1
0
1
0
ai+1 = (xi + ai ) (xi'+ bi')
xiai bi 0 1
00
01
11
10
0
1
0
0
1
1
1
1
bi+1 = (xi + bi ) (xi + ai')
00 1
0
1 0
1
1
an+1bn+1
Z = an+1
S0
0 10
1 S3
S2
S1
aibiState
Next Statexi = 0 xi = 1 Z
S0 S0 S1 0S1 S2 S3 1S2 S2 S1 1S3 S3 S3 0
aibi
ai+1bi+1xi = 0 xi = 1 Z
00 00 11 011 10 01 110 10 11 101 01 01 0
a0 = b0 = 0a1 = (x0 + 0) (x0' + 1) = x0 b1 = (x0 + 1) (x0 + 0) = x0
Unit 17 Problem Solutions
17.1 See FLD p. 664 for solution. 17.2 See FLD p. 665 for solution.
17.3 (a, b)
17.4
See FLD p. 665-666 for solutions.
17.5
Up/Down
CO
Q(7)Q(6)Q(5)Q(4)
D(7)D(6)D(5)D(4)
Q(3)Q(2)Q(1)Q(0)
D(3)D(2)D(1)D(0)
COENT
CLK
CLRnLOAD
ENPUP CLK
ENPUP
ENT
CLRnLOADCOCO1
Up/Down
See FLD p. 666-667 for solution. See FLD p. 667 for solution.
136 137
17.7 (a) See FLD p. 668 for solution.
CE
Q
Q(1)
CLK
D CE
Q
CLK
D
LdALdB
LdA LdBLdA'A(1) B(1) LdA LdBLdA'A(2) B(2)
Q(2)
See FLD p. 667-668 for solutions.17.6 (a, b)
X1
CLK
CLK
2 X 4ROM
4X2
Z1Z2
D Q
D QQ1Q2
Q1+
Q2+
17.7 (b)
CE
Q
Q(1)
CLK
D CE
Q
CLK
D
LdALdB
A(1) B(1)
LdA
Q(2)
1 0
A(2) B(2)
LdA1 0
17.8 See FLD p. 668 for solution.
136 137
8
8
Clk
Ld 8-bit Register
8D
Q
En
Qint
17.12 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity myreg is
port(en, ld, clk : in std_logic;d : in std_logic_vector(7 downto 0);q : out std_logic_vector(7 downto 0));
end myreg;architecture Behavioral of myreg issignal qint : std_logic_vector(7 downto 0):="00000000";
beginq <= qint when en ='1' else "ZZZZZZZZ";process(clk)
beginif clk' event and clk='1' then
if ld='1' then qint <= d; end if;end if;
end process;end Behavioral;
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity srff is
port (clk, s, r : in std_logic;q, qn : out std_logic);
end srff;architecture Behavioral of srff issignal qint : std_logic:='0';
beginq <= qint;qn <= not qint;process(clk)
beginif clk'event and clk='1' then
if (not s and r)='1' then qint <= '0';elsif (s and not r)='1' then qint<='1';elsif (s and r)='1' then qint<='X'; end if;
end if;end process;
end Behavioral;
17.9 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- D-G Latchentity dglatch is
port (d, g : in bit;q : out bit);
end dglatch;architecture Behavioral of dglatch is
beginprocess(g, d)
beginif g='1' then q <= d; end if;
end process;end Behavioral;-- D flip flop using D-G latcheslibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dff is
port (d, clk : in bit;q : out bit);
end dff;architecture Behavioral of dff iscomponent dglatch is
port (d, g: in bit;q : out bit);
end component;signal p, clkn : bit;
beginclkn <= not clk;dg1 : dglatch port map(d, clkn, p);dg2 : dglatch port map(p, clk, q);
end Behavioral;
17.10
A rising edge triggered D-CE flip flop with asynchronous clear and preset.
17.11
138 139
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity encoder is
port (y0, y1, y2, y3 : in bit;a, b, c : out bit);
end encoder;architecture Behavioral of encoder is
beginprocess(y0, y1, y2, y3)
beginif y3='1' then a <= '1'; b <= '1'; c <= '1';
-- y3 has highest priorityelsif y2='1' then a <= '1'; b <= '0'; c <= '1';elsif y1='1' then a <= '0'; b <= '1'; c <= '1';elsif y0='1' then a <= '0'; b <= '0'; c <= '1';else a <= '0'; b <= '0'; c <= '0'; end if;
end process; end Behavioral;
17.13library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity comparator is
port (a, b : in std_logic_vector(3 downto 0);agb, alb, aeb : out std_logic);
end comparator;architecture Behavioral of comparator is
beginprocess(a, b)
beginif a > b then agb <= '1'; alb <= '0'; aeb <= '0';elsif a < b then agb <= '0'; alb <= '1'; aeb <= '0';else agb <= '0'; alb <= '0'; aeb <= '1'; end if;
end process; end Behavioral;
17.14
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity super is
port (a: in std_logic_vector(2 downto 0);d : in std_logic_vector(5 downto 0);rsi, lsi, clk : in std_logic;q : out std_logic_vector(5 downto 0));
end super;architecture Behavioral of super issignal qint: std_logic_vector(5 downto 0);
beginq <= qint;process(clk)
beginif clk' event and clk='1' then
case a iswhen "111"=> qint <= d;when "110"=> qint <= qint-1;when "101"=> qint <= qint+1;when "100"=> qint <= "111111";when "011"=> qint <= "000000";when "010"=> qint <= rsi&qint(5 downto 1);when "001"=> qint <= qint(4 downto 0)&lsi;when others=> NULL;end case;
end if;end process;
end Behavioral;
17.15 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity bcd_seven is
port (bcd : in bit_vector(3 downto 0);seven : out bit_vector(7 downto 1));
end bcd_seven;architecture Behavioral of bcd_seven is
beginprocess(bcd)
begincase bcd iswhen "0000"=> seven <= "0111111";when "0001"=> seven <= "0000110";when "0010"=> seven <= "1011011";when "0011"=> seven <= "1001111";when "0100"=> seven <= "1100110";when "0101"=> seven <= "1101101";when "0110"=> seven <= "1111101";when "0111"=> seven <= "0000111";when "1000"=> seven <= "1111111";when "1001"=> seven <= "1101111";end case;
end process; end Behavioral;
17.16
138 139
--The state assignment is as follows (q0q1q2q3)---S0 - 1000; S1 - 0100; S2 - 0010; S3 - 0001--VHDL code using equations derived by inspection from state graphentity sm1 is
port (x, clk : in bit;z : out bit);
end sm1;architecture equations of sm1 issignal q0 : bit := '1';signal q1, q2, q3 : bit:='0';
beginprocess(clk)
beginif clk'event and clk='1' then
q0 <= (x and q0) or (not x and q1) or (not x and q3);q1 <= (not x and q0) or (x and q3);q2 <= (x and q2) or (x and q1);q3 <= not x and q2;end if;
end process;z <= (not x and q1) or (x and q3) or q2;
end equations;
17.18
StateNext State
X = 0 X = 1Output
X = 0 X = 1S0 S0 S1 10 00S1 S1 S2 01 01S2 S2 S3 01 01S3 S0 S0 00 10
17.19
StateNext State
X = 0 X = 1 OutputS0 S0 S1 1S1 S3 S2 0S2 S1 S0 0S3 S0 S1 0
17.20
S0 S1
S3 S2
XZ
X'0X
0
X'0
X0
XZX'
Z
X'Z
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity sm1 is
port (x, clk : in std_logic;z : out std_logic);
end sm1;architecture Behavioral of sm1 istype rom8_3 is array(0 to 7) of std_logic_vector(0 to 2);constant myrom: rom8_3 :=("001","100","111","000","000","010",
"110","101");signal index, romout: std_logic_vector(0 to 2);signal q, d: std_logic_vector(1 to 2):="00";
beginindex <= x&q;romout <= myrom(conv_integer(index));z <= romout(0);d <= romout(1 to 2);process(clk)
beginif clk' event and clk='1' then q <= d; end if;
end process;end Behavioral;
17.17
140
17.21State
Next StateX1X2 = 00 01 10 11 Z
S0 S0 S1 S2 S0 0S1 S0 S1 S2 S1 0S2 S0 S1 S2 S2 1
8
8
Clk
StoreMask Register
8
X
Z
M
Set
8
17.22 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mask_8 is
port (X : in std_logic_vector(7 downto 0);Store, Set, Clk : in std_logic;Z : out std_logic_vector(7 downto 0));
end mask_8;architecture Behavioral of mask_8 issignal M : std_logic_vector(7 downto 0);
beginprocess(Set, Clk)
beginif Set='1' then M <= "11111111";elsif Clk'event and Clk='1' then
if Store='1' then M<=X; end if;end if;
end process;Z <= M and X;
end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Seq_143 is
port (Clk, X : in std_logic;Z : out std_logic);
end Seq_143;architecture Moore of Seq_143 issignal State : integer := 0;signal NextState : integer range 0 to 3;
beginprocess(State, X)
begincase State iswhen 0 => Z <= '0';
if X = '0' then NextState <= 0;else NextState <= 1; end if;
when 1 => Z <= '0';if X = '0' then NextState <= 2;else NextState <= 1; end if;
when 2 => Z <= '0';if X = '0' then NextState <= 0;else NextState <= 3; end if;
when 3 => Z <= '1';if X = '0' then NextState <= 2;else NextState <= 1; end if;
end case;end process;process(Clk)
beginif Clk'event and Clk='1' thenState <= NextState; end if;
end process;end Moore;
17.23
141
Unit 18 Problem Solutions
18.3 See FLD p. 669 for circuit. Notice that the Q output of the flip-flop is bin , while the D input is bout .
18.4
18.9
S1S5
S0
St0
ShSh
Sh
St'0
StSh
St'0
S2S4
S3
Sh
See FLD p. 670. AND-ing with xi is like M/Ad if xi is 1. Shifting is like moving from AND gates involving x1 to those involving x2, or from x2 to x3.
18.5 See FLD p. 670. Compare to divider state graph of FLD Figure 18-11.
18.6 See FLD p. 670.
18.7 (a) Overflow occurs only on division by 0, so V = y0' y1' y2' y3' y4' = (y0 + y1 + y2 + y3 + y4)'
See FLD p. 671.18.7 (b) - (d)
18.8 See FLD p. 671.
The ONE ADDER is similar to a serial adder, except that there is only one input. This means that the carry will be added to X. Thus, if the carry flip-flop is initially set to 1, 1 will be added to the input. The signal I can be used to preset the carry flip-flop to 1.
Let S0 represent Carry = 0, and let S1 represent Carry = 1. The state graph is as follows:
S1S0X' Sh
Z
X'0
I X Sh0Sh'0
,XZ
, QX Sh 0 1
00
01
11
10
0
0
0
0
1
0
1
1
Q = Q (Sh' + X )+
Q'
QD
Clk
Sh'X
PreN
I
QXQ'X'
X or Q'Sh
Z
QX Sh 0 1
00
01
11
10
0
0
1
1
0
1
0
0
Z = (Q + X) (Q'+X') (X + Sh)Z = (Q + X) (Q'+X') (Q'+ Sh)
142 143
18.10 (a)
18.10 (b) 18.10 (c)
Present State
Next StateStM: 00 01 10 11
Ad Sh Load Done 00 01 10 11
S0 S0 S0 S1 S1 0000 0000 0010 0010S1 S3 S2 S3 S2 0100 1000 0100 1000S2 S3 S3 S3 S3 0100 0100 0100 0100S3 S5 S4 S5 S4 0100 1000 0100 1000S4 S5 S5 S5 S5 0100 0100 0100 0100S5 S7 S6 S7 S6 0100 1000 0100 1000S6 S7 S7 S7 S7 0100 0100 0100 0100S7 S0 S0 S0 S0 0001 0001 0001 0001
18.10 (d)
AB C 0 1
00
01
11
10
S0
S3
S7
S5
S1
S2
S6
S4
(Other assignments are possible.)
S1S9
S0
S2
S
S
St/Load
M/Ad
M'/Sh
- /Sh
M/Ad
M'/Sh
- /Done
- /Sh
St'/0
S5
S6
S
M/Ad
M'/Sh
- /Sh
7
4
3
3456 0127ACC
multiplier
product
4-BITADDER
multiplicand
CONTROL St
ShAd
Done
Load
M
ClkC4
1 0 1 10 0 0 0 0 1 0 1
0 1 0 1 1 1 0 1
0 0 0 1 0 1 1 11 0 1 1
0 0 1 1 0 1 1 1
0 0 1 0 1 1 1 0
0 1 1 0 1 1 1 1
add
shiftshiftadd
shift
I. (S0, S7) (S1, S2) (S3, S4) (S5, S6) II. (S0, S1) (S2, S3) (S4, S5) (S6, S7)III. (S1, S3, S5) (S2, S4, S6) etc.
142 143
For this assignment, from LogicAid:JA = StB'C' + MC; KA = M' + B + C; JB = A'C; KB = A'C'; JC = AB'; KC = A'B; Ad = MAB'C' + MA'C; Sh = M'A + M'C + AB + AC; Load = StA'B'C'; Done = A'BC'
18.10 (d) (contd)
ShLd
SI
Clk
0 1 0 1
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0D7 D6 D5 D4 D3 D2 D1 D0
M
multiplier
adder
3 3
LdLd5 3
55
4
multiplicand
34
44
0
0Sh
Ld Ad
A
K
JClk
B
K
JClk
C
K
JClk
St
M
AdShLdDone
OR gates, ANDgates, & invertersimplement theequations from18.10 (d)
18.11 (a)
4567 0128ACC
multiplier
product
5-BITADDER
multiplicand
CONTROL St
ShAd
Done
Load
M
ClkC5
3
144 145
St M A B C DA DB DC Ad Sh Ld Done 1 - 0 0 0 1 0 0 0 0 1 0 - 1 1 0 0 1 0 0 1 0 0 0 - 1 0 - 1 1 0 0 1 0 0 0 - - 0 - 1 0 1 0 0 0 0 0 - - 1 1 - 0 1 0 0 1 0 0 - - 1 0 - 0 0 1 0 0 0 0 - - - 0 1 0 0 1 0 0 0 0 - - 1 - 1 0 0 1 0 1 0 0 - 0 1 - - 0 0 0 0 1 0 0 - 0 - - 1 0 0 0 0 1 0 0 - - 0 1 0 0 0 0 0 0 0 1
ShLd
SI
Clk
0 1
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0D7 D6 D5 D4 D3 D2 D1 D0
M
multiplierFA 3 3
Ld3
multiplicand
3
0Sh
Ld Ad
Q8D8
0 1 0 10 1 0 1 0 10 1
FA FA FA FA000000
0
QD
Clk
QD
Clk
QD
Clk
StM
AdShLdDone
PLAClkA
B
C
Graph is same as 18.10, so from LogicAid, using the same state assignment:
DA = StA'B'C' + MAB'C' + MA'CDB = A'C + ABDC = AB' + B'C + AC
Ad, Sh, Ld, Done: See solution to 18.10 (d)
18.11 (d)
18.11 (c)
0 0 0 0 0 0 0 1 10 0 0 0 0 0 1 1 0
1 0 1 0 0
0 0 1 0 1 0 0 0 11 0 1 0 0
0 0 1 1 1 1 0 0 0
0 1 0 1 0 0 0 1 1
0 1 1 1 1 0 0 0 1
shiftadd
shiftadd
shift
18.11 (b) See solution to 18.10 (b).
144 145
18.12 (a)
S0
S1 S2M'K'
Sh
St'0
MAd
K'Sh
KSh Sh
St M'
AdSt M Sh
M'K
State Counter X St M K Ad ShS0 00 000000111 1 1 0 1 0S1 00 011001111 0 1 0 0 1S2 01 001100111 0 1 0 1 0S1 01 100101111 0 1 0 0 1S2 10 010010111 0 1 1 1 0S1 10 101011111 0 1 1 0 1S0 00 010101111 0 1 0 0 0
18.12 (b)
18.13 (a)
FullSubtracter
d7
x7
b7 FullSubtracter
d6
x6
b6 FullSubtracter
d5
x5
b5
y2 y1
= 0
0
b8
C
C
(alternate solution)
divisor
Control
Clk
ShLdx0x1x2x3x4x5x6x7
ShSuSubtracter-Comparator
Divisor0
C StV
18.13 (b)
18.13 (d)
1 10 1 0 1 0 0 1 1
1 0 1 0 0 1 1 0
0 1 0 0 0 1 1 11 0 0 0 1 1 1 0
0 0 1 0 1 1 1 1
1 1
1 1
shift C = 0
1 10 1 0 1 1 1 1 0
1 0 1 1 1 1 0 0
0 1 0 1 1 1 0 11 0 1 1 1 0 1 0
0 1 0 1 1 0 1 1
1 1
1 1
sub. C = 1shift C = 0
sub. C = 1shift C = 0
shift C = 0
sub. C = 1shift C = 0
C = 0sub. C = 1
remainder quotient
S2S6
S3S5
S0
StLd
C'0
CSu
St'0
S4
S1
CSu
CSu
CSu
C'Sh
C'Sh
C'Sh
C'Sh
C'ShC
V
CSu ,
18.13 (c)
146 147
18.14 (c)
F.A.
d7
x7
Comparator C F.A.
d6
x6 y4
F.A.
d5
x5 y3
F.A.
d4
x4 y2
F.A.
d3
x3 y1
1
1
Comparator C
alternate solution
18.14 (d) 18.15 (a)
18.15 (b) D0 = St'Q0 + KQ1 + KQ2; D1 = StQ0 + K'B'Q1 + K'BQ2; D2 = K'BQ1 + K'B'Q2; R = StQ0Sh = K'B'Q1 + K'BQ1 + K'BQ2 + K'B'Q2 = K'Q1 + K'Q2; X = KQ1 + K'BQ1 + K'BQ2 = KQ1 + BQ1 + K'BQ2
Counter
Controller
Clk
StClrKClk
ClkEr
SISh
So
S1 S2S0St'0
K'Sh
StClr
K'ShK'
Sh SI
KSh
K0
K'Sh SI
KEr
,,S'o So
SoSo S'o
S'o
18.16 (a)
18.16 (b)
Control
Clk
ShLdx1x2x3x4x5x6x7
ShSuSubtracter-Comparator C St
V
y1y2y3y40
S1S4
S2S3
S0
St0
St'0
StLd
St'0
CV
C'Sh
CSu
C'Sh
C'0CSu,
18.14 (a) 18.14 (b)
1 1 0 11 0 1 1 0 1 0
0 1 0 0 1 1 1
1 0 0 1 1 1 01 1 0 1
1 1 0 1
0 0 1 1 0 1 1
shift C = 0
sub. C = 1
shift C = 0
sub. C = 1
1 1 0 10 1 0 1 1 0 1
remainder quotient
S1 S2S0
St'0
K'B'ShSt
RK'B'
ShK'BX Sh
K'BX Sh
KX
K0
146 147
18.16 (c) D0 = St'Q0 + KQ1 + KQ2; D1 = K'X0'Q1 + StQ0; D2 = K'X0Q1 + K'Q2; Clr= StQ0Sh = K'X0'Q1 + KX0'Q1 + K'X0Q1 + K'Q2; Er= KX0Q1; SI = K'X0Q1 + K'X0'Q2
18.17 (a)
Counter
ControlSt
Clk
SISh
ClkClk
Clk
SISh
LogicNetwork
a
b
Shift Register A
Shift Register B
C
Sh
K0
SI
Clk
18.17 (b)
S0
S2 S1
St'0
St'0
St0 K
Sh
K'Sh
StSh
Present State
StK 00 01 11 10
Sh 00 01 11 10
S0 S0 S0 S1 S1 0 0 1 1S1 - - S2 S1 - - 1 1S2 S0 S0 S2 S2 0 0 0 0
18.17 (c) I. (S0, S2)×2 (S1, S2) (S0, S1) II. (S0, S2)×2 (S1, S2) (S0, S1)×2From Karnaugh maps:D0 = Q0
+ = StQ0 + KQ0'Q1D1 = Q1
+ = St; Sh = StQ0'Alternative: Q0
+ = StQ0 + StKQ1
St K Q0 Q1 D0 D1 Sh 1 - 1 - 1 0 0 - 1 0 1 1 0 0 1 - - - 0 1 0 1 - 0 - 0 0 1
18.17 (d) SI = C'ab + Cab' + Ca'b
S0
0 10
1 S1 S2
18.18 (a)
Counter
ControlSt
Clk
SISh
Clk
SISh
LogicNetwork
a
b
Shift Register A
Shift Register B
CSh
K0
SID
Clk
Clk
S1S0
S2
St'0
K'Sh D
St CSh D
KSh D
KSh
St C'Sh
K'Sh
18.18 (b) State MeaningS0 ResetS1 Find AND of A & BS2 Find XOR of A & B
148 149
St C K Q0 Q1 Q2 Q1+ Q2
+ Q3+ Sh D
0 - - 1 - - 1 0 0 0 0 - - 1 - 1 - 1 0 0 1 1 - - 1 - - 1 1 0 0 1 0 1 1 - 1 - - 0 1 0 1 1 - - 0 - 1 - 0 1 0 1 1 1 0 - 1 - - 0 0 1 1 0 - - 0 - - 1 0 0 1 1 0
18.19 (a)
Control
Sh
C2
St
XSI
Clk
C1
Sh
M
X0
18.19 (b)
S0
S1
S2
S3
St'0
StSh
-Sh-
Sh
-Sh
Note: M can be determined independently of the state of the system, so it is not included in the state graph.
18.19 (c) JA = B; KA = B; JB = St + A; KB = 1; Sh = St + A + B; M = C1'C2 + X0'C1C2
Counter
Controller
ClkSt
LdClk
Clk
ABSI
K
0
N3
S1 S2S0St'0
KLd
K'A
K'B
StLd
K0
18.20 (a)
18.20 (b)
StateStK
00 01 11 10ABLd
00 01 11 10S0 S0 S0 S1 S1 000 000 001 001S1 S1 S2 - - 010 001 - -S2 S2 S0 - - 100 000 - -
D1 = KQ2 + K'Q1; D2 = St + K'Q2; A = K'Q1;B = K'Q2; Ld = St + KQ2
18.20 (c)
Q0+ = St'Q0 + KQ1 + KQ2; Q1
+ = StCQ0 + K'Q1;Q2
+ = StC'Q0 + K'Q2;Sh = StCQ0 + StC'Q0 + K'Q1 + KQ1 + K'Q2 + KQ2D = StCQ0 + K'Q1 + KQ1
18.18 (c)
18.21
Control
Clk
St LdAdEnInLdAcDone
EnAdSt'0
St'0
StLdAc, EnIn
S0 S1 S2 S3
S6 S5 S4
0
EnIn, LdAd
EnIn, LdAd
EnAd, LdAc
Done, EnAd, LdAcStDone
Change C' to D' in 18.17 (d)SI = D'ab + Dab' + Da'b
18.18 (d)
148 149
J = ST; K = ZER1 ZER2; Done = ZER1 ZER2 Q; CLR = STQ'; LD2 = STQ'; LD1 = STQ' + ZER1 ZER2' Q; CT1 = ZER1' Q; CT2 = ZER1 ZER2' Q
18.22 (a) 18.22 (b)
S1S0St'0
ZER1 ZER2Done
StLD2 LD1 CLR
ZER1 ZER2'CT2 LD1
ZER1'CT1
(N1 + 1)N2 cycles 18.22 (c)
18.23 (a)
S1S0St'0
EZERODone
StCLR LOAD
IZERO' EZERO'DOWN
IZERO EZERO'UP LOAD
D = EZERO' Q + StQ'; Done = EZERO Q; CLR = StQ'; LOAD = StQ' + IZERO EZERO' Q DOWN = IZERO' EZERO' Q UP = IZERO EZERO' Q
18.23 (b)
The quotient counter reaches 1111, and UP = 1 again.
18.23 (d)
N1 + (N1/N2) cycles (round down) The quotient will count upward forever, and Done will never be 1.
18.23 (c) 18.23 (e)
18.24
Clk
Ld
8-bit subtracterControlCircuit
Clk
N
B
8-bit registerSu
8
8
8
8
Clk
Clr 4-bit counterInc 1
4"000"
odd integer
SuLdSt
When the done signal comes on, square root is in the 4-bit counter
St - start
Ld - load N into registerand clear counter
Su - load subtracter outputinto register
Inc - increment counter
B - borrow
S1S0St'0
StLd
BDone
B'Su Inc