elec 2200-002 digital logic circuits fall 2015 logic synthesis (chapters 2-5) vishwani d. agrawal...
DESCRIPTION
Synthesis Procedure Minimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit. Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms: Programmable logic array (PLA) Standard cell library Field programmable gate array (FPGA) Others... Fall 2015, Nov 6... ELEC Lecture 6 3TRANSCRIPT
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ELEC 2200-002Digital Logic Circuits
Fall 2015Logic Synthesis (Chapters 2-5)
Vishwani D. AgrawalJames J. Danaher Professor
Department of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawal
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Logic SynthesisDefinition: To design a logic circuit such that it meets the specifications and can be economically manufactured:
Performance – meets delay specification, or has minimum delay.Cost – uses minimum hardware, smallest chip area, smallest number of gates or transistors.Power – meets power specification, or consumes minimum power.Testablility – has no redundant (untestable) logic and is easily testable.
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Synthesis ProcedureMinimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit.Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms:
Programmable logic array (PLA)Standard cell libraryField programmable gate array (FPGA)Others . . .
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References on Synthesis
G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994.S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994.
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Programmable Logic Array (PLA)
A direct implementation of multi-output function as a two-level circuit in MOS technology.PLA styles:
NAND-NANDNOR-NOR
Textbook, Chapter 5.
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Example: Two-Output FunctionNeed four products: P1, P2, P3, P4
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F1 A
B
C
D
F2 A
B
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Two-Level AND-OR ImplementationAlso known as technology-independent circuit.
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A
B
C
D
F1
F2
P1
P2
P3
P4
INPUTS AND OR
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INPUTS NAND NAND
NAND-NAND Implementation
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A
B
C
D
F1
F2
1P
2P
4P
3P
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A NAND Gate in nMOS Technology
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VDD
X
Y
XY
GND
VDD
X
Y
XY
GND
VDD
X
Y
XY
GND
R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design,Boston: McGraw-Hill, 2008, Section 6.8.2.
Depletionload
Enhancementload
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NAND-NAND PLA
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A B C D F1 F2
1P
2P
4P
3P
VDD
VDD
VDD
VDD
VDD
VDD
GND
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NAND-NAND PLA SCHEMATIC
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A B C D F1 F2
1P
2P
4P
3P
INP
UTS
OU
TPU
TS
AND-plane OR-plane
Tran
sist
ors
atcr
oss-
poin
ts
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Standard-Cell DesignObtain two-level minimized form.Map the design onto predesigned building blocks called standard cells (technology mapping).Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology:
90 nanometer CMOS65 nanometer CMOS45 nanometer CMOS. . .
This is known as application-specific integrated circuit (ASIC).
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Technology MappingFind a common logic element, e.g., two-input NAND gate or inverter (one-input NAND).MSOP is converted into NAND-NAND circuit.Split larger input gates into two-input NAND gates and inverters.Cover the circuit with standard cells, also split into two-input NAND gates and inverters (graph-matching).
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A Typical Cell LibraryName Area units (cost) Inputs Output function, Z
Inverter 2 A
NAND2 3 A, B
NAND3 4 A, B, C
NAND4 5 A, B, C, D
AOI21 4 A, B, C
OAI21 4 A, B, C
AOI22 5 A, B, C, D
XOR 4 A, B
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AZ ABZ
ABCZ
ABCDZ CABZ
CDABZ BABAZ
S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill1994, Section 7.7, pp. 185-198.
CBAZ )(
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NAND3 Cell in TransistorsNAND3 Cell in Transistors
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A
B
C
Z
VDD
GND
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NAND3 Cell Graphs
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Directed AcyclicGraph (DAG)(tree)Root ≡ OutputOne-input node (NOT)Two-input node (NAND)
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NAND4 Cell
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AOI21 Cell
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OAI21 Cell
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AOI22 Cell in TransistorsAOI22 Cell in Transistors
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A
B
C
D
VDD
GND
Z
Observe that in a CMOS circuit, any vector of input variables connects the output Zeither to GND or to VDD, giving it a value 0 or 1, respectively. Examining the pull-downnetwork, we notice that the output is connected to GND if AB = 1 or CD =1. Thatgives the output function as, . The cell, therefore, is AOI22.CDABZ
Pull-up network
Pull-down network
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AOI22 Cell
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XOR Cell
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NAND Graphs for Library CellsName Area units (cost) Inputs NAND graph
Inverter 2 A
NAND2 3 A, B
NAND3 4 A, B, C
NAND4 5 A, B, C, D
AOI21 4 A, B, C
OAI21 4 A, B, C
AOI22 5 A, B, C, D
XOR 4 A, B
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Technology Mapping ProcedureObtain MSOP.Convert to two-level AND-OR circuit.Transform to two-level NAND-NAND circuit.Transform to two-input NAND and inverter tree network.Perform an optimal pattern matching to obtain a minimum cost tree covering.
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INPUTS NAND NAND
Previous Example: 2-Level NAND(Slide 8)
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A
B
C
D
F1
F2
1P
2P
4P
3P
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A Simple Technology Mapping
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B
C
F1
F2
2PD
A
Cost = 24
NAND2 (3)NAND2 (3)
NAND2 (3)
NAND3 (4) NAND3 (4)
(2)
(2)
NAND2 (3)
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Optimum Mapping: Convert NAND Circuit to Directed Acyclic Graph (DAG)
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A
B
C
D
F1
F2
2P
4P
3P
1P
Each node is aNAND gate.(NOT ≡ 1-input NAND)
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Split DAG into Trees (Forest)
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A
B
C
D
F1
F2
2P
D
CB
2P
2P
A
D Cost = 24
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Split Nodes With More Than Split Nodes With More Than Two BranchesTwo Branches
(Use NAND3, NAND4 Graphs)(Use NAND3, NAND4 Graphs)
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≡2P 2Por F2 or F2
≡NAND4
or
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Uniform Branching (1 or 2)
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A
B
C
D
F1
F2
2PC
B
D
D
2P
2P
ACost = 32
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Graph Matching
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A
B
C
D
F1
F2
2PC
B
D
D
2P
2P
A
NAND3 (4)
NAND3 (4)
OAI21 (4)
NAND2 (3)
NAND2 (3)
(2)
(2)
Cost = 22
Nodes insertedFor pattern matching
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Technology Mapping
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A
B
C
D
F1
F2
2PC
B
D
D
2P
2P
A
OAI21 (4)
NAND3 (4)
NAND3 (4)
NAND2 (3)
NAND2 (3)
(2)
(2)
Cost = 22
Inverters insertedFor pattern matching
(2)
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Mapped Circuit
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B
C
F1
F2
2PD
A
Cost = 22NAND2 (3)
NAND3 (4) NAND3 (4)
(2)
(2)
NAND2 (3)
AOI21 (4)
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Original Reference
K. Keutzer, “DAGON: Technology Binding and Local Optimization by DAG matching,” Proc. 24th Design Automation Conf., 1987, pp. 341-347.
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