Baloch 1 MAPLD 2005/1024-L
Design of a ‘Single Event Effect’ Mitigation Technique for
Reconfigurable Architectures
TH
E
UNI VERSI TY
OF
E D I N B U
RG
H
SAJID BALOCH
Prof. Dr. T. Arslan1,2 Dr.Adrian Stoica3Supervisory Team
Baloch 2 MAPLD 2005/1024-L
ACRONYMES
– SEU (Single Event Effect)– SET (Single Event Transient)– SEB (Single Event Burnout)– SEL (Single Event Latch-up)– Cfg (Configuration)– EDAC (Error Detection and Correction)– SoC (System on Chip)– FPGA (Field Programmable Gate Array)– DEU (Double Event Upset)– TEU (Triple Event Upset )– MEU (Multiple Event Upsets)
Baloch 3 MAPLD 2005/1024-L
RECONFIGURABLE ARCHITECTURES
ME
MO
RY
ME
MO
RY
ReconfigurableArray
IP
DSP
IP
Re-Configurable SoC Architecture
a) FPGAs
- SRAM
- Anti Fuse
- EPROM
b) Reconfigurable SoC
- General purpose
- Domain Specific
Baloch 4 MAPLD 2005/1024-L
RADIATION EFFECTS RE-CONFIGURABLE ARCHITECTURES
– PERMANANT FAULTS (due to SEL, SEB etc)
– TEMPORARY FAULTS (due to SEU etc)
Baloch 5 MAPLD 2005/1024-L
SEU MITIGATION TECHNIQUES
a) HARDWARE REDUNDANCY
- Dual Modular Redundancy (DMR)
- Triple Modular Redundancy (TMR)
- EDAC Codes
- Process Technology
b) TIME REDUNDANCY
c) COMBINATION (Hardware & Time)
Baloch 6 MAPLD 2005/1024-L
• TRANSIENT FAULTS (Data Memory etc)
• PERMANANT FAULTS (Cfg. Memory)
Radiation Hardening SEU EFFECTS
Baloch 7 MAPLD 2005/1024-L
SEU EFECTS Synchronous Circuits
D-F
lip F
lop
D-F
lip F
lop
CombinationalLogic Circuits
Data_in Data_out
Clock
Baloch 8 MAPLD 2005/1024-L
SEU EFECTS Configuration Memory
M
M
D-F
lip F
lop
M
M M M MLUT
SEU (BITFLIP)
Baloch 9 MAPLD 2005/1024-L
CLUSTER
CLUSTER
CLUSTER
CLUSTER
CLUSTER
CLUSTER
SEU EFECTS ROUTING OF A SIGNAL
Baloch 10 MAPLD 2005/1024-L
Proposed SEU/SET MitigationTechnique
based on:• Temporal Data Sampling• Weighted Voting
Salient Features of The Proposed Technique:Auto Correction Mechanism for• 100% SEU Recovery• 100% Double Fault Recovery• Voter Faults Recovery
Baloch 11 MAPLD 2005/1024-L
Temporal Sampling
Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Data
CLk-A
CLk-B
CLk-C
L1 L2
L6L5
L4L3
1
3
5 6
4
2
Primary Section
Secondary Section
Baloch 12 MAPLD 2005/1024-L
TEMPORAL SAMPLING Clock Scheme
• 3 derivates of Main Clock
• Each Clock is Phase shifted
• 25% duty Cycle
CLk-A
CLk-B
CLk-C
CLOCK
Computation Cycle
2 Clock Cycles
Baloch 13 MAPLD 2005/1024-L
Minimized TermX4.X3.X0 + X5.X3.X0 + X5.X4.X0 + X4.X3.X1 + X5.X3.X1 + X5.X4.X1 + X4.X3.X2 + X5.X3.X2 + X5.X4.X2 + X5.X4.X3 +
X3.X2.X1.X0 + X4.X2.X1.X0 + X5.X2.X1.X0
Weighted Voter Circuit
Baloch 14 MAPLD 2005/1024-L
SEU in Secondary Section
Node BeforeSEU
AfterSEU
Voting Weights‘1’ ‘0’
Total Votes ‘1’ ‘0’
1 1 1 2 -
8 1
3 1 1 2 -
5 1 1 2 -
2 1 0 - 1
4 1 1 1 -
6 1 1 1 -
Case Example
Baloch 15 MAPLD 2005/1024-L
Multiple Bit Upset
Node BeforeSEU
AfterSEU
Voting Weights‘1’ ‘0’
Total Votes ‘1’ ‘0’
1 1 1 2 -
5 4
3 1 0 - 2
5 1 0 - 2
2 1 0 1 -
4 1 1 1 -
6 1 1 1 -
Case Example
Baloch 16 MAPLD 2005/1024-L
Hardware Implementation of Proposed Scheme with
Auto-Correction Mechanism
Baloch 17 MAPLD 2005/1024-L
Single Event Transition FaultData / Clock
Baloch 18 MAPLD 2005/1024-L
SEU/SET Simulator•SEU’s can be injected at instance•SEU of any duration can be injected•Multiple upsets can be injected
Baloch 19 MAPLD 2005/1024-L
Performance AnalysisFault Coverage
Mitigation Scheme %age Fault Tolerance
SET SEU DEU TEU
Proposed Scheme 100% 100% 100% 50%
F. Lima etal Scheme 63% 100% - -
D. Mavis etal Scheme 100% 100% 32% 18%
Baloch 20 MAPLD 2005/1024-L
Performance AnalysisArea Overhead
0
50
100
150
200
250
300
350
400
450
Proposed Technique Mavis etal Technique
Are
a (
u s
qu
are
mete
r)
Results are based on:
0.13µm CMOS technology
