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CHAPTER 8: Counter & Register
8.0 – Introduction to counter8.1 – Asynchronous counter8.2 – Synchronous counter8.3 – Up & Down Synchronous counter
8.4 – Integrated circuit register8.5 – Serial-In/Serial-Out8.6 – Serial-In/Parallel-Out8.7 – Parallel-In/Serial-Out8.8 – Parallel-In/Parallel-Out8.9 – Ring counter
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8.0 Introduction to Counters8.0 Introduction to Counters• Counting is a fundamental function of digital circuits• Counters are devices which have a CLOCK input and produce n outputs.• Counters consists of flip-flop connected together in specific ways such that on
each clock edge the output change. • n flip-flops are required for an n-bit output counter. • Normally, the effect of this change is to generate an output that is in some way
related to the previous output numerically (Pattern). • For example, every time a clock edge is detected the output could increase by 1. • Therefore, for n=3 (3 flip-flop); can write a table that illustrates this.
After the 8th clock edge, the counter start again 0.
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• have same control input for each flip flop which is the clock
• have less propagation delay
• depends on previous output• have propagation delay
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• The flip-flops can be connected in one or two ways, to produce either asynchronous counters or synchronous counters:
- Asynchronous counters (Ripple counter)All the inputs are the same (tied HIGH) and the output of each flip-flop is connected to the CLKof the next flip-flop.
- Synchronous countersAll the CLKs of each flip-flop are connected to a common CLOCK, and the inputs are a combinations of the previous outputs.
• The least-significant bit (LSB) is shown on the left and the most-significant bit (MSB) is shown on the right.
COUNTERSCOUNTERS
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JK Flip flop as basic function for counters:•A JK flip flop toggles when both inputs are 1. In this case it effectively counts every second clock pulse:
Sometimes called a “scale of 2 counter”
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J
K
clock
Q
~Q
clock
Q
You can also say it counts from 0 to 1 and back again.
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clock
Q1 Q21
clock
Q1
Q2
Outputs Q1 and Q2
cycle.
Complete the timing diagram for Q2
8.1 ASYNCHRONOUS COUNTER OPERATION8.1 ASYNCHRONOUS COUNTER OPERATION2-Bit Asynchronous Binary Counter: Connect two such flip flops together:
• The clock (CLK) is applied to the clock input of only the first flip-flop FF0, which always the LSB.
• The two flip-flops are never simultaneously triggered, so the counter operation is asynchronous.
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Propagation DelayAsynchronous counters are commonly referred to as ripple counters for the following reason. – The effect of the input clock pulse is first “felt” by FF0. – This effect cannot get to FF1 immediately because of the propagation
delay through FF0. – Then, there is the propagation delay through FF1 before FF2 can be
triggered. – Thus, the effect of an input clock pulse ‘ripples’ through the counter, taking
some time, due to propagation delays, to reach the last flip-flop.
ASYNCHRONOUS COUNTER OPERATIONASYNCHRONOUS COUNTER OPERATION
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A 3-Bit Asynchronous Binary Counter
-A 3-bit asynchronous binary counter is shown in figure beside.
-It has eight sates, due to its three flip-flops. 2n
J
K
Q
Q
J
K
Q
Q
J
K
Q
Q
1
1
1
1
1
1
clk
Qa Qb Qc
– These propagation delays cause a number of sequence changes when going from one number to the next, which can be undesirable in a lot of situations.
– The counter can get the wrong value at a particular instant in time
– Operating speed is therefore limited.
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A 4-Bit Asynchronous Binary Counters
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• Also known as truncated asynchronous counters.• Modulus of a counter is the number of unique states that the counter will
sequence through. • The key to implement truncated asynchronous counters is to detect the first
undesired state then RESET the flip-flops to zero that are not already zero.
ASYNCHRONOUS DECADE COUNTERASYNCHRONOUS DECADE COUNTER
Example:An asynchronous counter is required that counts from 0 to 9 before staring again at 0 again.
SolutionStep 1We must determine how many flip-flops are required to implement a counter that counts to 9. 4 bits are required and hence 4 flip-flops will be used to implement the counter.
Step 2We must detect when state 10 is output by the counter, i.e, when Q3Q2Q1Q0 = 1010. When we detect this state, we need to output a zero to those flip-flops not already zero. In order to output a zero, we can used a NAND gate circuit.
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Step 3We must decide on which flip-flops need to be RESET. When state 10 is detected Q0 and Q2 are already zero, therefore they do not need to be RESET. However Q1 and Q3 are both 1 so they must be RESET to 0. Hence the output of the detection circuit must be connected to their CLR inputs.The circuit required therefore is :
Hence our circuit for detecting the presence of a 10 can be simplified to:
This is possible because states 11, 12, 13, 14 and 15 cannot occur as the counter is RESET when 10 is detected. However the previous circuit is perfectly acceptable.
Replace T with J-K. T FF equal to JK FF with both inputs are connected together
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With respect to counter operation, synchronous means that all the flip-flops in the counter are clocked at the same time by a common clock pulse.
A 2-Bit Synchronous Binary Counter
8.2 SYNCHRONOUS COUNTER OPERATION8.2 SYNCHRONOUS COUNTER OPERATION
Operation used: will be either 00-NC, or 11-Tgl
J
K
Q
Q
1
1
J
K
Q
Q
clk
Qa Qb
C0
1
Qa 0
1
0
1
00 01 10 11 00 01
Qb
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A 3-Bit Synchronous Binary Counter
SYNCHRONOUS COUNTER OPERATIONSYNCHRONOUS COUNTER OPERATION
J
K
Q
Q
1
1
J
K
Q
Q
clk
Qa Qb
J
K
Q
Q
Qc
Qc should not toggle until both Qa and Qbare 1
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A 4-Bit Synchronous Binary Counter The particular counter is implemented with negative-triggered flip-flops.
SYNCHRONOUS COUNTER OPERATIONSYNCHRONOUS COUNTER OPERATION
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Example: Design a 3 bit Gray code with sequence below by using
JK Flip Flop
?? So how??...in other words…it should be a design process to implement counters with all sort of sequences…
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A summary of steps used in the design of this counter follows. In general, these steps can be applied to any sequential circuit.
1. Specify the counter sequence and draw the a state diagram.
2. Derive a next-state table from the state diagram.
3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop.
4. Transfer the J and K states from the transition table to Karnaugh maps. There is a K map for each input of each flip-flop.
5. Group the K map cells to generate and derive the logic expression for each flip-flop input.
6. Implement the expressions with combinational logic, and combine with the flip-flops to create the counter.
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Step 1: State Diagram
Example: Design a 3 bit Gray code by using JK Flip Flop
Step 2: Next State Table
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Step 3: Flip flop Transition Table
Step 4: Karnaugh Maps
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Step 5: Logic Expressions for Flip Flop Inputs
012
012
021
021
1212120
1212120
QQK
QQJ
QQKQQJ
QQQQQQK
QQQQQQJ
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Step 6: Implementation
Example: Design a counter for the sequence of: 000, 010, 011, 101, 110 using J-K FF
Step 1: Derive the State Transition Diagram
Step 2: Next State Table
000
010
011
101
110
PresentState
NextState
C B A0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
C+ B+ A+0 1 0X X X0 1 11 0 1X X X1 1 00 0 0 X X X
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PresentState
NextState Remapped Next State
Q Q+0 00 11 01 1
J K0 X1 XX 1X 0
PresentState
NextState Remapped Next State
C B A0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
C+ B+ A+0 1 0X X X0 1 11 0 1X X X1 1 00 0 0X X X
JC KC0 XX X0 X1 XX XX 0X 1X X
JB KB1 XX XX 0X 1X X1 XX 1X X
JA KA0 XX X1 XX 0X XX 10 XX X
Step 3: State Transition Table
JC = A
KC = A
JB = 1
KB = A + C
JA = B C
KA = C
JC
JA
JB
KC
KA
KB
0 0 X XX 1 X X
X X 1 XX X X 0
1 X X XX X X 1
X 0 1 XX 1 X X
0 1 0 XX X X X
X X X XX 0 X 1
A A
AA
A ACB CB
CBCB
CBCB
Step 4: Karnaugh Maps Step 5: Logic Expressions for Flip Flop Inputs
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CLK CLK CLK J
K
Q
Q
A
\ A
C
\ C KB
J
K
Q
Q
B
\ B
+
J
K
Q
Q
JA
C
A
\ A
B \ C
Count
A C KB JA
Step 6: Implementation
JC = A
KC = A
JB = 1
KB = A + C
JA = B C
KA = C
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8.3 UP/DOWN Synchronous Counters8.3 UP/DOWN Synchronous Counters Capable of progressing in either direction through a certain sequence. Sometimes called a bidirectional counter, can have any specified sequence of
states. Can be reversed at any point in their sequence. For instance, the 3-bit counter can be made to go through the following sequence:
0, 1, 2, 3, 4, 5, 6, 7, 0……
An up/down counter also can be in following sequence:
3, 2, 6, 4, 7, 3,……
To implement up/down counter, the previous process design can be use but with additional control input to control the sequence whether it is in up manner(control input should be in high state=1) or down manner(control input should be in low state=0).
UP
DOWN
UP
DOWN
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8.4 Integrated Circuit Registers
• Shift Registers, for data storage and data movement• Concept of storing a 1 or 0 in a D Flip Flop is shown
Types of Registers
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8.5 Serial In/Serial Out Registers
An 8 bit Shift Register
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8.6 Serial In/Parallel Out Registers
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The 74HC164 8-bit serial in/parallel out shift register.
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8.7 Parallel In/Serial Out Register
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The 74HC165 8-bit parallel load shift register.
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8.8 A parallel in/parallel out register
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8.9 Ring Counters
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Clock Pulse
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
0 1 0 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0
2 0 0 1 0 0 0 0 0 0 0
3 0 0 0 1 0 0 0 0 0 0
4 0 0 0 0 1 0 0 0 0 0
5 0 0 0 0 0 1 0 0 0 0
6 0 0 0 0 0 0 1 0 0 0
7 0 0 0 0 0 0 0 1 0 0
8 0 0 0 0 0 0 0 0 1 0
9 0 0 0 0 0 0 0 0 0 1