12mecv15 [compatibility mode]

SoC Development Containing Teststructures for SiVal of Memories/IO’s/Efuse/Std Cells

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008.

14/03/2014

Presented by:Gaurav Lalani12MECV15M.Tech-VLSIIntern at : FSL

Guided By:Mr. Parvez Zaman

Internal Guide:Dr. N.P.Gajjar

for SiVal of Memories/IO’s/Efuse/Std Cells

Topics CoveredTopics Covered

►ASIC Design Flow

►RTL Synthesis Flow

►Synthesis Environment

►Synthesis Flow in RC compiler

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008.

►Multi-Corner Synthesis

►Work Done till Date

►Future Work

An ASIC/VLSI Design FlowAn ASIC/VLSI Design Flow


An RTL Synthesis FlowAn RTL Synthesis Flow


What is Synthesis ?What is Synthesis ?

►Translation from higher abstraction level to lower abstraction level

►It is the process of converting RTL to gate level netlist

►3 types of synthesis:

� Behavior Synthesis


� Behavior Synthesis � RTL Synthesis � Physical Synthesis

Does RTL Synthesis Really Matter?Does RTL Synthesis Really Matter?

Bad synthesis results can have far

What if I have Bad Netlist ?

Poorly structured pathsHigher cell area

Unroutable

Congestion

Too slow

Crosstalk

More Iterations

Too big

Back-end Issues


Bad synthesis results can have far reaching consequences.

Larger Die

High Power Consumption

Increased Engineering Costs

Slower Speed

Project Issues

Late To Market

High Part Costs

High Development

Costs

Market Issues

►Inputs

• RTL: Verilog, VHDL, directives, pragmas.

• Constraints: .sdc or .g• Library: .lib • Physical: LEF, DEF, Captable

Logic Synthesis EnvironmentLogic Synthesis Environment

Encounter RTL

Compiler

RTL Code

Captable LEF

.LIB Constraints


►Outputs

• Optimized netlist• Constraints : .sdc or .g• First Encounter® input files

PhysicalDesign

Optimized netlist

Constraints

RTL Lib

Read RTL

Elaborate &Uniquify

Scan Stitching

Incremental Optimization

Synthesis Flow in RC Compiler


Timing & Design Constraints

Synthesize to Generic Logic

Map to Technology Library

Netlist Constraints

ElaborationElaboration

►During Elaboration RC compiler performs following tasks:

1) Builds data structure2) Infers registers in the design 3) Performs high level HDL optimizations4) Checks Semantics


UniquificationUniquification

Top Module For FA

HAInstantiation

1

HAInstantiation

2


Module Definition

For HA

Module Definition

For HA

Design ConstraintsDesign Constraints

►Clock signal specification� period� duty cycle� transition time� Skew

► Delay specifications


� Maximum� Minimum

►Timing exception� false path� multicycle path

Boundary Optimization & Constant PropagationBoundary Optimization & Constant Propagation

� Constants can modify structure inside an hierarchy and change net connections across hierarchical boundaries.

• Rewiring of equivalent signals across hierarchy� If two outputs of a module are identical, RC may disconnect one of them and

use the other output to drive the fanout logic for both.• Optimize away unloaded flops and associated logic


� Optimization of flop-driven hierarchical boundaries• Flops with constants in the ‘D’ lines are equivalent to constants depending on reset

method.

clk FF

D Q

rst

1’b0

Optimization

1’b0

Equivalent assign statement in

verilog

Equivalent assign statement in

verilog

Hierarchy boundaryHierarchy boundary

unusedunused1’b0

Also driven awayAlso driven away


Multi Corner SynthesisMulti Corner Synthesis

REQUIREMENT : -

► For C65 and below technologies, due to temperature inversion ,delay of a cell is maximum at wcscold corner, whereas transitions are better at low temperature. CPF with multiple library domain can be used in such scenarios.


Multi Corner Synthesis ….Multi Corner Synthesis ….

Encounter RTL

Compiler

RTL Code

Captable LEF

.LIB Constraints


PhysicalDesign

Optimized netlist

Constraints

Interacting signals in Multi Power Domain DesignInteracting signals in Multi Power Domain Design

Power Domain 1 (1.2V)

Power Domain 2(1.0V)

Memory

Isolation

Normal V

Lev

el S

hift

er


1.2VDomain

Power Domain 3 (1.8V) switchable

MemoryLow Vt

(High Speed)Normal Vt High Vt

(low leakage, lower Speed) Isolation

Isolation

Isolation

QOR METRICSQOR METRICS

►AREA

►TIMING

►POWER


►POWER

►YIELD

Physical Physical synthesis : For better Timing convergence synthesis : For better Timing convergence

►Floorplan Def is read in to RC.

►RC does actual placement by invoking Encounter

►Rs & Cs are extracted on basis of actual placement data from a placed def. Annotate RC

Chip Place Prototype

Post optimization netlist


def.

►These values are annotated to timing data.

►Shows better correlation for the final placement results in synthesis stage.

Incremental Optimization Based on RC

Annotate RC

LMTV ARCHITECTURELMTV ARCHITECTURE

CoreControl

RegistersFreq_ Counters Bus MUXs

Padring

Address

SystemControl

Chip ID ROInputData

OutputData

EFuseArray


MFTRMemory

FunctionalTestand

RepairBlock

STD and I/O Cells

Core

Address

Pwr/Gnd

Memory Control MTMMemoryTiming

MeasurementBlock

Ref.: FSL Internal Doc

Work Done till DateWork Done till Date

►Presently working on Synthesis of LMTV SoC

►Understood the basic concepts of Static Timing Analysis

►Blocks Synthesized:� All_Cell� Ring Oscillator


� Ring Oscillator� Memory Test and Repair (MTR)� Frequency Counter� Padring� Efuse, SRAM, ROM, 2PRF, 1PRF

Future WorkFuture Work

►Execute Synthesis on LMTV SoC with relevant optimizations.

►Performing Verification of PROMO test-chip.


THANK YOU


12mecv15 [compatibility mode]

Documents

freescale logo

service names

respective owners

bad synthesis results

behavior synthesis tmfreescale

bad netlist

rc compilertmfreescale

lib physical