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Digital Chip Testing with Agilent 93000 SOC Series ( )
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}Test Development Flow
1.
IC 2 test plan
design a DUT board pin configuration level setup timing setup vector
setup testflow setup testing the device result analysis
IC test plan
functional scan pattern power dissipation
design a DUT board DUT board
IC testhead pogo pin IC CIC
8 IC package (DIP48 PLCC68 PLCC84 CQFP100 CQFP128
CQFP144 CQFP160 CQFP208) DUT board
pin configuration IC signal pin
signal pin test channel device power
supply IC
level setup power supply voltage current limit
drive voltage (VIL VIH) compare voltage
threshold (VOL VOH) timing setup
system cycle (period time) vector
setup waveform
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vector
testflow setup
testing the device
IC IC response
response (PASS)
(FAIL) result analysis timing
diagram error map shmoo plot
IC
1. CIC DUT Board
CIC 8 IC digital channel 320
DUT board testhead 3
DIP48 CQFP128 CQFP144 package DUT board PLCC68
PLCC84 CQFP160 DUT board CQFP100 CQFP208
DUT board DUT board (loadboard) package pin count
320 DUT board
IC power pin DUT board
IC power pin device power supply
DUT board
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Software Overview
1. Software Overview
SmarTest 5
pin configuration level setup timing setup vector setup testflow setup
testing the device result analysis SmarTest
IC
IC response SmarTest offline mode
online mode online mode offline mode
offline mode unix%>
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Pin Config
Levels
Timing
Vectors
Testfunction
ASCII Interface
ScanConverter
ASCII
data
STIL, WGL
SmarTest
Testflow
Test Plan&
Design a DUTLoadboard
TranslationDesign
Pass/Fail
Analysis
Pin Config
Levels
Timing
Vectors
Testfunction
ASCII Interface
ScanConverter
ASCII
data
STIL, WGL
SmarTest
Testflow
Pin Config
Levels
Timing
Vectors
Testfunction
ASCII Interface
ScanConverter
ASCII
data
STIL, WGL
SmarTest
Testflow
Test Plan&
Design a DUTLoadboard
TranslationDesign
Pass/Fail
Analysis
5 SmarTest Overview
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SmarTest main toolbar report
window operation control window 6 main toolbar
report window log
operation control window
report window log tester
state tester operation
SmarTest main toolbar File Quit
pin configuration level setup
main toolbar 7 8 tabs tabs buttons
main toolbar 4 buttons connect
disconnect break change device connect AC
relay disconnect AC relay break IC
change device IC IC
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6 SmarTest Start-up Screen
Change
Device
Break
Disconnect
Connect
Tabs
Buttons
7 SmarTest Main Toolbar
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2. Pin Configuration
pin configuration data manager setup page
Config Icon 10 File Load IC
template CIC DUT board package
pin test channel CIC
template
test
channel
main toolbar pin configuration button
data manager Config Icon pin configuration
11 pin configuration MONITOR Mode
EDITOR Mode EDITOR Mode
Mode editor EDITOR Mode EDITOR Mode
pin name
( 16 ) type
IC type i IC response type o bi-directional
I/O type io pin number pin VDD
VSS pin Edit delete
line... delete
device power supply
DUT board pin
configuration test channel Download
data manager Config Icon
data manager Save ( 12
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10 Defining the Pins
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pin configuration
(levels timing vector)
pin configuration
Select groups... Pin Group Definition ( 13)
new atomar definition Digital Pin Group Definition (
14)
copy
Config
11 Pin Configuration
12 Pin Configuration
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save Pin Group Definition
group
Pin Group Definition done data
manager Config Icon
data manager Save
3. Defining the Levels
Level Setup drive voltage (VIL VIH) 15
compare voltage threshold (VOL VOH) 16 power
13 Pin Group Definition Window
14 Digital Pin Group Definition Window
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supply voltage current limit power setup time
power 17 data manager
setup page Level Icon 18 Level Icon
data manager Level Icon Level Setup
19 Level equation editor
Level equation set level equation set SPECS
EQUATIONS DPSPINS
LEVELSET VIH VIL VOH VOL
SPECS Level Spec Tool
20 level equation set 19
COREPW IOPW core power io pad power
EQUATIONS VIH VIL VOH VOL
LEVELSET 1 all_ins pin group clk pin vil vih
VIL VIH ( pin configuration
level setup ) io_pins
pin group vil vih vol voh all_outs pin group
voh voh
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Power Supply Voltage
vout
Setup
Time
Internal
settling timet_ms
Connect Current Limit
ilimit
Disconnect Stage:
offcurr =min, act
17 DPS Voltage and Current Limit
18 Level Setup Window
LEVEL EQN SET n
LEVEL EQN SET 2
Level Equation Editor
LEVEL EQN SET 1
SPECS
EQUATIONS
DPSPINS
LEVELSET 1
LEVELSET k
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Level Spec Tool
SPECS
= 4.5 V
= 0. 5V
SPECS
= 4.8 V
= 0. 2V
LEVEL SPEC SET 1
LEVEL SPEC SET 2
19 Level Setup Architecture
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20 Level Equation Editor
Level Equation Editor Level Setup Select Edit
Equations vi CIC nEdit
21 nEdit keyword nEdit
Shell LEVEL Download Equations download data manager
Level Icon data
manager Save
EQNSET 1 "levels equation set"
SPECS
COREPW [V]
IOPW [V]
EQUATIONS
VIL = 0
VIH = IOPW
VOL = 0.2*IOPW
VOH = 0.8*IOPW
DPSPINS corevdd
vout = COREPW
ilimit = 1000
t_ms = 4
offcurr = act
DPSPINS iovdd
vout = IOPW
ilimit = 1000
t_ms = 4
offcurr = act
LEVELSET 1 "no termination"
PINS all_ins clk
vil=VIL
vih=VIH
PINS io_pins
vil= VIL
vih= VIH
vol= VOL
voh= VOH
PINS all_outs
vol=VOL
voh=VOH
20 Level Equation Set Example
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level equation set SPECS
Spec Tool Spec Tool Level
Setup Select Edit Specifications 22
level equation set create Create level spec set
23 Create level spec set Set number
Description create Spec Tool
( 24) Spec Tool SPECS
Actual File Download
download data manager Level Icon
data manager Save
SPECS core
*21 Level Equation Editor
*22 Select Level Equation Set
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power io pad power Spec Tool
1.8 V 3.3 V vil=0 V vih=3.3 V vol=0.66 V voh=2.64 V
CIC
CIC eNews timing vector
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924 Spec Tool
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RPO.C.3
RPO.C.6
NW.S.1
NWR.E.1
NWR.C.3
OD.C.1
OD.C.2_OD.C.3
OD.C.5
RPO.S.1
RPO.C.3
RPO.C.6
ESD.GUIDE.4
ESD.5E
ESD.5F
ESD.5G
I/O PAD ERROR STC18io_33T
ESD.5E
PO.W.1.MM
TSMC I/O PAD ERROR
CTM.R.2CTM density is not enough
for capacitor
M6T.E.2Min extension of M6T region beyond VIA5 at the end of M6T is 0.45um
for mimcap5
M6T.C.1
M6T.E.3
INDDMY Meyal 6 567 50um
for inductor
M6T. I .1No Via and metal layers inside INDDMY region
for 3D-inductor
M1.A.1Minimum area of M1 region < 0.202um*um8
for resistor
PO.R.1P-cell(moscap_g3, moscap_g6)9:8
for varactor
mos.01.LAT.3(;SNominal Vt MOS
for mos
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2.
MEMS Interferometer Measurement System
Hierarchical vs. Flat
Hierarchical AM.W.1.M5
9 19 CIC MEMS Interferometer Measurement SystemMEMS Interferometer Measurement System
1. White light Interferometer(Optical profiler)2. MEMS Motion Analyzer
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Hierarchical CIC FlatFlat
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