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Slides adapted from:
N. Weste, D. Harris, CMOS VLSI Design, © Addison-Wesley, 3/e, 2004
The CMOS Inverter
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Outline
Robustness of CMOS Inverter – The Static Behavior Switching threshold Noise Margins
Performance of CMOS Inverter – Dynamic Behavior Propagation delay
Power Dissipation Static dissipation Dynamic dissipation
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Q&A
1. If the width of a transistor increases, the current will increase decrease not change
2. If the length of a transistor increases, the current willincrease decrease not change
3. If the supply voltage of a chip increases, the maximum transistor current willincrease decrease not change
4. If the width of a transistor increases, its gate capacitance willincrease decrease not change
5. If the length of a transistor decreases, its gate capacitance willincrease decrease not change
6. If the supply voltage of a chip increases, the gate capacitance of each transistor willincrease decrease not change
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Q&A
1. If the width of a transistor increases, the current will increase decrease not change
2. If the length of a transistor increases, the current willincrease decrease not change
3. If the supply voltage of a chip increases, the maximum transistor current willincrease decrease not change
4. If the width of a transistor increases, its gate capacitance willincrease decrease not change
5. If the length of a transistor increases, its gate capacitance willincrease decrease not change
6. If the supply voltage of a chip increases, the gate capacitance of each transistor willincrease decrease not change
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CMOS Inverter Static Behavior: DC Analysis
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CMOS Inverter: DC Analysis
DC Response: Vout vs. Vin for a gate Inverter
When Vin = 0 Vout = VDD
When Vin = VDD Vout = 0 In between, Vout depends on transistor current By KCL, must settle such that Idsn = |Idsp| We can solve equations Graphical solution gives very good insight
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Transistors operation regions
Current depends on transistor’s operation region For what Vin and Vout are nMOS and pMOS in
Cutoff ? Linear ? Saturation ?
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nMOS and pMOS operation
Idsn
IdspVout
VDD
Vin
Idsn
IdspVout
VDD
Vin
Vgsn = Vin
Vdsn = Vout
Vgsp = Vin - VDD
Vdsp = Vout - VDD
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Graphical derivation of the inverter DC response: I-V Characteristics
Make pMOS wider than nMOS such that n = p
For simplicity let’s assume Vtn=Vtp
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Graphical derivation of the inverter DC response: current vs. Vout, Vin
Load Line Analysis: For a given Vin:
Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal
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Graphical derivation of the inverter DC response: Load Line Analysis
Vin0
Vin0
Idsn, |Idsp|
VoutVDD
Vin = 0
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Graphical derivation of the inverter DC response: Load Line Analysis
Vin1
Vin1Idsn, |Idsp|
VoutVDD
Vin = 0.2 VDD
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Graphical derivation of the inverter DC response: Load Line Analysis
Vin2
Vin2
Idsn, |Idsp|
VoutVDD
Vin = 0.4 VDD
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Graphical derivation of the inverter DC response: Load Line Analysis
Vin3
Vin3
Idsn, |Idsp|
VoutVDD
Vin = 0.6 VDD
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Graphical derivation of the inverter DC response: Load Line Analysis
Vin4
Vin4
Idsn, |Idsp|
VoutVDD
Vin = 0.8 VDD
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Graphical derivation of the inverter DC response: Load Line Analysis
Vin5Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
Vin = VDD
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DC Transfer Curve
Transcribe points onto Vin vs. Vout plot
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DC transfer curve: operating regions
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Beta Ratio If p / n 1, switching point will move from VDD/2 Called skewed gate
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Noise Margins How much noise can a gate input see before it does not
recognize the input ?
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Noise Margins To maximize noise margins, select logic levels at unity gain
point of DC transfer characteristic
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DC parameters Input switching threshold: VTH
Minimum high output voltage: VOH
Maximum low output voltage: VOL
Minimum HIGH input voltage: VIH
Maximum LOW input voltage: VIL
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CMOS Inverter Dynamic Behavior: AC Analysis
DC analysis tells Vout if Vin is constant AC analysis tells Vout(t) if Vin(t) changes
Requires solving differential equations Input is usually considered to be a step or ramp from 0 to VDD or vice versa
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CMOS Inverter Dynamic Behavior: AC Analysis
The switching characteristic (Vout(t) given Vin(t)) of a logic gate tells the speed at which the gate can operate
The switching speed of a logic gate can be measured in terms of the time required to charge and discharge a capacitive load
Critical paths Timing Analyzers automatically finds the slowest paths in a logic
design Critical paths can be affected at various levels:
Architecture/ Microarchitecture Level Logic Level Circuit Level Layout level
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Inverter Step Response
Find step response of inverter driving load cap
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
0
2
2
0
2)
)
( ( )
( DD DD t
DD
out
outout out D t
n
t
ds
D
I V
t t
V V V V
V V V VV
t
V t V t
Vout(t)
Vin(t)
t0t
Vin(t) Vout(t)Cload
Idsn(t)
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Delay Parameters
tr: rise time
From output crossing 0.2 VDD to 0.8 VDD
tf: fall time
From output crossing 0.8 VDD to 0.2 VDD
tpdr: rising propagation delay
From input crossing VDD/2 to rising output crossing VDD/2 tpdf: falling propagation delay
From input crossing VDD/2 to falling output crossing VDD/2 tpd: average propagation delay
tpd = (tpdr + tpdf)/2
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Delay Parameters cont.
tr, tf
Tells how steep can be the waveform that the logic gate is able to provide at its output
tpdr, tpdf
Input-to-output delay of the logic gate (time needed for the output to respond to a change in the input)
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Factors affecting delay
CLOAD (= Cintrinsic + Cextrinsic) intrinsic capacitance
(parasitic capacitance of the driving logic gate) extrinsic capacitance
(interconnect capacitance + capacitance of the stage driven)
Slope of the input waveform As the voltage on the gate terminal of a transistor change so
does its capacitance
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Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically
Uses more accurate I-V models too! But simulations take time to write It is important to develop back of the envelope techniques to rapidly
estimate delay, understand its origin, and figure out how it can be reduced
(V)
0.0
0.5
1.0
1.5
2.0
t(s)0.0 200p 400p 600p 800p 1n
tpdf = 66ps tpdr = 83psVin Vout
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Delay Estimation
We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask “What if ?”
The step response usually looks like a 1st order RC response with a decaying exponential.
Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that tpd = RC
Characterize transistors by finding their effective R Depends on average current as gate switches
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RC Delay Models Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width Resistance inversely proportional to width
kg
s
d
g
s
d
kCkC
kCR/k
kg
s
d
g
s
d
kC
kC
kC
2R/k
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Power Dissipation
Static CMOS gates are very power-efficient because they dissipate nearly zero power while idle
Instantaneous power:
Energy consumed:
Average power:
DDDD V(t)iP
T
0
DDDD dtViE
T
0
DDDDavg dtViT
1P
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Power Dissipation
Power dissipation in CMOS circuits comes from two components:
Static Dissipation Subtreshold conduction Tunneling current Leakage through reverse biased diodes
Dynamic Dissipation Charging and discharging (switching) of the load capacitance “Short-Circuit” current while both pMOS and nMOS networks
are partially ON
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Static Dissipation
OFF transistors still conduct a small amount of current : Sub threshold current Current through reverse biased diodes gate tunneling current
In 130 nm processes and beyond leakage is becoming a major design issue and vendors now provide leakage data (often in the form of nA/m of gate length)
leakageDDstatic IVP
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Dynamic Dissipation
T
0
DD
T
0
DDDDDDscswdynamic (t)dti
T
VdtV(t)i
T
1PPP
clock2DDsw fVCP
Assuming a logic gate goes through one complete charge/discharge cycle every clock cycle:
clock2DDsw fVCαP
Because most gates do not switch every clock cycle, we introduce a corrective activity factor :
A clock has =1 because it rises and fall every cycle, but most data have a maximum activity factor =0.5 because they transition only once every cycle
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Dynamic Dissipation
Because, input rise/fall time is greater than zero, both nMOS and pMOS will be ON for a short period of time (while the input is between Vtn and VDD-|Vtp|)
This results in a “short-circuit” current pulse from VDD to GND
Typically this increases power dissipation by about 10%
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Low Power Design
Power Dissipation is a major problem !!!
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Dynamic Power Reduction
Decrease activity factor Selective clock gating Drawback: if the system transitions rapidly from an idle
mode to a fully active mode a large di/dt spike will occur
Decrease switching capacitance Small transistors Careful floor planning to reduce interconnect
Decrease power supply Adjust voltage depending on the operating mode
Decrease operating frequency
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Static Power Reduction
Subthreshold current can be reduced by increasing Vt
Selective application of multiple threshold(low-Vt transistors on critical paths, high Vt transistors on other paths)
Control Vt through the body voltage
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Turn off the power supply entirely. MTCMOS circuits use low Vt transistors for computation and high Vt transistor as a switch to disconnect the power supply during idle mode
The leakage through two series OFF transistor is much lower (10-20x) than that of a single transistor (stack effect)
Static Power Reduction cont.