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Douglas WongToshiba America Electronic Components
Flash Forward @ CES 2011Flash Forward: Flash Memory Storage Solutions
Jan. 7th 2011, CES Las Vegas
AgendaAgenda
• A Short History on Flash Memory• A Short History on Flash Memory• What is NAND Flash Memory?• The Need for Speed• The Need for Speed
Flash Forward @ CES 2011
’84 ’85 ’86 ’87 -------’91 ’92 ’93 --- 2000s
J i t V t
Flash Memory Timeline
SANDISK-type(SanDisk)
NANDNAND--typetypeNAND-type
Joint Venture Development
(Toshiba, (Toshiba, Samsung)Samsung)
AND-typeX
FileFile--StorageStorage
yp(Toshiba)
ACEE-type(TI)
AND-type
FLASH FLASH MEMORYMEMORY
T hib
NORNOR--typetype((Intel,AMDIntel,AMD))
AND type(Hitachi)
NOR-type(Excel / I l)
yp(Hitachi)Toshiba
(( ,, ))
SST-type(SST)
XSST-type
(SST, Sanyo)
CodeCode--StorageStorage
(Intel)
Split-gate-type(SEEQ)
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DiNOR-type(Mitsubishi)
DiNOR-type(Mitsubishi)
Flash Memory Primer
• All Flash requires Erase before Programming– Erase
– Program
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NORNORAGAG--ANDANDBit line(metal)
Contact
NROMNROMNANDNAND
Word line(poly)
Source line(Diff. Layer)
Unit Cell
Cell Circuit Unit Cell
Word line(poly)
Unit Cell
Word line(poly)
Unit Cell
Word line(poly)
2F2F
Bit / Source line(Diff. Layer)
Source line(Diff. Layer)
3F
Source line(Diff. Layer)
2F5F
2FLayout
Cross-section
2F2F
2F3F
2F2F
Cell Size 6F2 10F24F24F2
High productivityHigh productivitySimple structureSimple structure
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High productivity High productivity High reliabilityHigh reliabilityMinimum cell sizeMinimum cell size
Scalability Scalability advantageadvantage
LOCOS LOCOS 0.7~0.4um0.7~0.4um New New Structures Structures 90nm90nm~~
32M32M
16M16M SASA--STI STI 0.25um0.25um~~0.13um0.13um17 Years of NAND Flash Memory Progress
11
256M256M
Floating GateFloating Gate
LOCOSLOCOSTunnel OxideTunnel Oxide
Control GateWSiWSiONOONO
Floating Gate
Control Gate
Tunnel Oxide
32M32M64M64M Control Gate ONO
Floating Gate
Tunnel Oxide STI
WSi
0.10.1
( um
2 )
256M256M
512M512M
1G1G1G1GMLCMLC
LOCOSLOCOSTunnel OxideTunnel Oxide
Floating GateControl GateFloating GateControl Gate
STI
Cel
l Siz
e(
2G2G4G4G
8G8G
1G1G
4G4G
2G2GLOCOS
STIFloating Gate
Control Gate
0.010.01
Multi Level Cell Multi Level Cell
8G8G16G16G8G8G
16G16G32G32G
STI
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0.0010.001
Fine LithographyFine Lithography 250250nmnm 160160nmnm 130130nmnm 9090nmnm 7070nmnm 5555nmnm 443nm3nm
NAND Flash Memory• NAND Flash was intended for file storage applications• NAND Flash is page-based for Read & Program operations
– The internal data registerholds one page of date
– A “page” is the unit of transferbetween the data registerand the memory arrayand the memory array.All program and read operationstransfer a page of data betweenthe data register and a page in
Flash Forward @ CES 2011
the data register and a page inthe memory array.
Growing Need for Higher NAND I/F Speed• Performance demand with the growth of storage interface• Performance demand with the growth of storage interface• With continuing innovations in the NAND architecture and enhanced
I/O speed, increased performance can be achieved.
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Read & Program Performance increased by long page size since tR and tPROGdoes not depend on page size Faster I/O needed to fill/empty page buffer
Advantages of Larger Page Size
Page size: 2kBPage Buffer
does not depend on page size. Faster I/O needed to fill/empty page buffer.
Serial Data in Serial Data out tR: Random Access Time
NAND PagetR:
tPROG:
tR:
tPROG:
tRC/tWC:
Random Access Time
Program Time
Read Cycle/Write Cycle Time
Page size: 8kBPage BufferSerial Data in Serial Data out
Cycle Time
Page Buffer
NAND Page
tPROG:
tR:
Serial Data in Serial Data out
Flash Forward @ CES 2011 9
NAND Flash Page Read OperationNAND Flash Page Read Operation
CE
ALE
CLE
WE
Register Data-Out
Page Address
tR
RE
I/O1~8
R/B Wait(tR)
D2111D000h 30h
Column Page Addr
Command Command
Column Addr.
Page Addr.
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300
Calculated Legacy NAND Page Read Time*
250
150
200
tR
100
tRC*Page Size
0
50
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2 kB 4 kB 8 kB
*SLC NAND, legacy NAND interface. Time represents calculated theoretical read time based on typical specifications for legacy NAND and Toggle Mode cycle times. Actual read time may vary depending on host performance and other factors.
Calculated DDR (Toggle) NAND I/F Page Read Time*300
250
150
200
tR
100
tRC*Page Size
0
50
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*SLC NAND, 133 MT/s, toggle mode NAND interface. Time represents calculated theoretical read time based on typical specifications for legacy NAND and Toggle Mode cycle times. Actual read time may vary depending on host performance and other factors.
2 kB 4 kB 8 kB
NAND Interface Evolution• As performance requirements increase, the legacy NAND interface(SDR–p q , g y (
single data rate) becomes bottleneck, esp. for read performance.• JEDEC NAND Flash I/F specification is scheduled to be ratified in early 2011
Legacy SDR( 50 Mbps)
Toggle-mode DDR Synchronous DDR(~50 Mbps)
WE#RE#DQQS
CKW/R#
DQQS
PinoutWE#
RE#DQ
DQS DQSQ
DQS
CKW/R#
WE#
DQSWrites
WE#
Reads RE#DQSDout
DQS
CK
Dout
W/R#
DinDin
RE#
D t
Din
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Dout DoutDout
Supported interface is identified by Read ID
High-Speed NAND Flash Interface
• New features to enable up to 400 Mbps– Complementary DQS and RE signals– Complementary DQS and RE signals– Vref (SSTL)– On Die Termination
l d– DQS latency adjustment
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Note: Features are under discussion and subject to change without notice.
High-Speed NAND Flash Interface
Legacy SDR
DDR(Toggle/Sync)
High-SpeedDDR
Type Description
15 16 20
CE#CLEALERE#
WE#
Toggle DDRNAND
CE#CLEALERE#WE#
ToggleDDR 400NAND
ALE ALE ALE I Address Latch Enable
CLE CLE CLE I Command Latch Enable
/CE /CE /CE I Chip Enable
/RE /RE or W/R# /RE I Read Enable or W/R# WP#
R/B#DQS
DQ[0:7]
WP#R/B#DQSDQ[0:7]
DQS#REVrefVpp
/WE /WE or CK /WE I Write Enable or CK
/WP /WP /WP I Write Protect
R/B R/B R/B O Ready/Busy
DQ DQ DQ I/O Data Input/OutputDQ DQ DQ I/O Data Input/Output
DQS DQS I/O Data Strobe
/DQS I/O Data Strobe Complement
RE I Read Enable Complement
Vpp I E ternal High Voltage
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Vpp I External High Voltage
Vref I Voltage Reference
Backward Compatibility• High-Speed NAND Flash supports backward compatibility
• New signals and functions are user-selective
Backward Compatibility
• Set feature command is used for changing interface
• ONFi-JEDEC Joint Task Group collaborating to provide a single, industry p g p g ystandard, high-speed NAND interface with backward compatibility.
• For an early and close look at the spec or contributions to the standard, please join JEDEC.
Flash Forward @ CES 2011