double nested miller

8/8/2019 Double Nested Miller

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758 IEEE JOURNAL OF SOLID -STATE CIRCU ITS , VOL. 2 8 . NO . 7 . JULY 19 93

A CMOS Low-Distortion Fully Differential PowerAmplifier with Double Nested Miller Compensation

Sergio Pernici, Member, IEEE, Gerrnano Nicollini, and Rinaldo Castello, Senior Member, IEEE

AbstractA four-stage fully differential power amplifier usinga double nested Miller compensated structure is presented. Themultiple-loop configuration used results in a lower harmonicdistortion, at least in the audio band, compared to conventionalthree-stage amplifiers with nested Miller compensation. Designcriteria and conditions for good stability of amplifiers using amultiple- (greater than two) loop topology are presented. Theamplifier operates with a single power supply which has aminimum value of 3 V. With a 5-V supply, power dissipationis 10 mW and THD is -S3 dB for a 6-VP P differential outputsignal at 10 kHz and a load of 50 Q. With 8-0 load and for a10-kHz, 4-VPP output signal, THD is -68 dB. The chip area is0.625 mm in a 1.5-~m single-poly, double-metal, n-well CMOStechnology

I. INTRODUCTION

I N recent years many new very complex systems have beenintegrated into silicon chips. This has become possibleespecially through the use of new digital circuits with acontinually increasing flexibility and precision. In this processmany analog circuits have been substituted with digital ones.Although this tendency will continue, some analog blocks,especially those interfacing with the external world, cannot bereplaced. One example is given by the power amplifiers oroutput buffers. Furthermore, as the precision and accuracy ofDSP-based systems increase, the level of performance requiredfrom the analog interface circuits also increases.In ISDN voice terminal equipment and digital telephone

sets, for instance, there is the necessity to drive loads of50100 0 and more than 100 nF for acoustic transducers, usingCMOS technologies and a 5-V power supply [1]. Similar needsare present in battery-operated systems such as portable hi-fisystems and cellular and cordless phones, where sometimespower supply can be as low as 3 V. In all these cases generalrequirements are low distortion together with small die sizeand low quiescent current. However, it is difficult to satisfyall these requirements, especially regarding distortion, usingprevious design methodologies, In fact, for a buffer amplifierdr iving h eavy loads , th ere is a trade-off between lin ea r ity onth e on e h and and power con sumpt ion and s ilicon a rea on th eoth er . For in s tan ce, to im prove open loop lin ea r ity wh ile givingou tpu t cu rren ts of u p to hu n dreds of m illiamperes , very la rgewidths (up to 10000 #m) are used for the output devicesManuscript received November 30, 1992; rewsed Febrnary 22, 1993.S. Pemici and G. Nicol lini are with ST SGS-Thomson Microelectronics,

20041 Agrate Bnanza, Italy ,R. Castello is wi th the Department of Electrical Engineering, Universdy of

Pavia, 27100 Pawa, Italy.IEEE Log Number 9208895.

#cl

VIN+ 0 OUTRP1 C4

Fig. 1. Multiple-loop feedback topology.

resulting in large silicon area. Conversely, to improve closedloop linearity, a large unity-gain bandwidth and consequentlya large power dissipation are required.Most recently reported buffer amplifiers [2][7] use a three-

stage nested Miller compensated topology to get better lin-earity for a given power consumption andlor silicon area ascompared with a simple two-stage Miller structure [8]. Thispaper goes a step further, presenting a differential poweramplifier with four stages of gain (including the class ABoutput stage) with a double nested Miller compensation. Thishas resulted in a better linearity with lower power dissipationand smaller area even compared with a nested Miller topology.In Section II of this paper, the multiple-loop compensationtechnique is presented and analyzed. Special attention is givento the key problem of stability. This is a particularly criticalaspect of the design when using four or more stages and thussome basic principles for good stability are provided. Thereasons why distortion is improved, at least in the audio band,are explained in Section III.In Section IV the new amplifier topology is described, while

experimental results are reported in Section V.

II. STABILITY IN MULTIPLE-LOOP AMPLIFIERSThe block diagram of a multiple nested Miller compensated

amplifier is shown in Fig. 1. The case of a single-endedstructure with four stages of gain is represented. The firststage is a differential input stage, the second and third onesare intermediate noninverting gain stages, and the last one isthe inverting output stage delivering the power to the loadrepresented by resistor R4 and capacitor G4. If a differentialstructure were used it would not be mandatory to use nonin-verting intermediate gain stages, but in this case a crossing ofthe intermediate compensation capacitors would be necessaryto obtain a stable structure.

001 89200/93$03.00 @ 1993 IEEE


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PERNICI cf al .: CMOS LOW-DISTORTION FULLY DIFFERENTIAL POWER AMPLIFIER 759

Voltage A,,.gain(m) m128

100-

80-

61-Openloopgainwith

40- c om p en sa t io n c a pa c it o rs

\ \f4mIlg. 2. Bode plot of an amplifier with double nested Miller compensation.

A Bode plot for the amplifier is presented in Fig. 2. Thepoles of the open-loop frequency response without compensa-tion capacitors are at frequencies

fi= 127rRPiCPi i=l,3f,= 12TR4C4 (1)

where RPi and CPi are the parasitic output resistances andcapacitances, respectively, of the ith stage, while R4 and C4represent the external loads.Consider now the movement of the poles when the com-

pensation loops are closed. The insertion of the compensationcapacitors Gi produces a pole-split ting effect similar to thatoccurring in a simple Miller compensated structure where thepole ~lm associated with the output of the first stage is movedto low frequency while the output pole is moved to highfrequency [8]. In this case flm is pushed to very low frequencywhile all the other poles, included the one at the output, arepushed to high frequency. The position of the dominant polefl~ is given by the following expression:

flnr = 1 (2)21rGm2 RPZ G7n3RP3 G7n4R4RPI CIwhich shows that j lm is moved down in frequency by a factorequal to the product of the gains of all the following stages.In order to obtain a good phase margin, this pole must be at avery low frequency while the nondominant poles f Zm .-. fN~must be at frequencies higher than the unity-gain frequency~T of the amplifier:

firrr > fT > fl?n, i=2, N (3)The exact position of the nondominant poles can be quitecomplex to calculate. In fact, if no special precaution istaken, these poles tend to interact with each other givingrise to complex pairs. This produces bumps in the frequencyresponse, which is an indication of a critical design from thepoint of view of stability. A stable and robust design and asimple expression for the nondominant poles can, however, be

VoltageGain(dB) h%oublem n n Nested100 Millerrz,w f360 a

~ Freq. (Hz) f4A \Fig. 3. Loop gains for a nested Miller and a double nested Miller compen-sated amplifier with compensation loops open.

obtained if the following rules are implemented:

(4)

GmN >> Gmi, i=l, N1. (5)where Gmi is the transconductance of the ith stage. Whenthe above rules are satisfied, the approximate position of thenondominant poles is given by the following expression:

(6)

while the unity-gain frequency of the amplifier is given by

(7)

The first stability condition (equation (4)) requires eachnondominant pole to be positioned at a frequency which isat least twice as high as that of the previous one. When thiscondition is satisfied, all the poles are sufficiently separatedso as not to interact with each other, i.e. they are on thereal axes according to (6). In this case each one of themcan be associated with the output of each amplifying stagewhen computing the amplifier open-loop transfer function.The output of the first stage is associated with the dominantpole and the outputs of the following n 1 stages with thenondominant ones.Equation (5) is always satisfied in the case of power

operational amplifiers since the transconductance of the laststage must be very high, compared to that of the precedingstages, in order to drive heavy loads.On the contrary, condition (4) is a pretty stringent one

and tends to limit considerably the overall bandwidth of theamplifier as the number of stages is increased. Nonetheless, alower distortion can be still obtained as explained hereafter.It would be possible to overcome the bandwidth reduction

effect using the technique called multipath nested Millercompensation, which was recently presented for a three-stage amplifier [9]. In this amplifier an independent path wasintroduced to bypass the intermediate stage at high frequencies,forcing the amplifier to behave as a two-stage amplifier.


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760 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 7, JULY 1993

M21A!!ll-

M21B

7A w~ AM1OA Vin+

oUT+ :a J WF MlCIA CIB11 II

MS M611 C2AA

C2B IIC3A - VB2 jr M14B C3 B -1

M20A J ~:B, c J

v v v v? :T: ? v .1:M3 M12B &+ M20BM15A M4MllA M1lB M15B

mchm

OUT-

1 IFig. 4 . Overall ampl ifier schemat ic.

From (3)(7) it follows that the amplifier has a very gooddegree of stability even in the unity-gain closed-loop config-uration.

111. DISTORTION IN MULTIPLE-LOOP AMPLIFIERSIn power amplifiers driving heavy loads and without prob-

lems of current driving (such as slew rate or output voltageclipping due to limited output current capability), distortion ismainly due to the output transistors. In fact, to get the requiredcurrent driving capability without excessively large devices,the gates of the output transistors must be driven with a rail-to-rail voltage swing. As a consequence, these devices movefrom saturation to deep linear operation during each cycle ofthe output signal (a sinusoidal driving is assumed). The mostcritical situation for a given value of the impedance load iswhen the load is purely resistive. ln fact, in this case thereis a 180 phase shift between gate and drain voltages of theoutput devices so that the maximum peak of current in theload is required when the output voltage is at its maximumvalue and the gate voltage is at its minimum value. In thiscondition the output transistor may leave the saturation regionduring part of the output swing and, as a consequence, thegain of the amplifier is strongly reduced. This condition canbe modeled with a large distortion source located in parallelwith the output transistors.When feedback loops are closed, distortion is reduced by

a factor equal to the products of the gains of all the loopssurrounding the distortion source (both external feedback andinternal compensation loops). In a multiple-loop feedbackconfiguration like that of Fig. 1, it can be shown that thelinearization factor for the distortion coming from the outputtransistor can be computed by opening all the compensationloops and computing the gain of the structure obtained in thisway, This can be accomplished by cutting all the connectionsbetween the compensation capacitors and the op-amp output(that is, cutting at point A in Fig. 1). To preserve the loadson all internal nodes after the loops have been opened, thecompensation capacitors must be connected to ground.Fig. 3 shows the loop gain for a nested Miller and a double

nested Miller compensated amplifier with compensation loopsopen. The figure assumes that the two amplifiers are designed

to give the same dc gain. To achieve this, a lower gain is usedin ~he input stage of the double nested amplifier compared withthe nested one. Thus the pole of the input stage in the doublenested case is pushed to a higher frequency (~j ) thanks toa lower output resistance. The pole associated with the extragain stage is located in the proximity of that associated withthe second stage of the nested Miller circuit (~~ w fz). FromFig. 3 it can be seen that the double nested configuration has alarger loop gain (i.e., l inearization factor) up to several hundredkilohertz (frequency jZ in the figure), even though the nestedMiller configuration has a larger bandwidth. For the exampleof Fig. 3, the improvement between 1 and 20 kHz is about20 dB. If the signal band is within this range, a 20-dB betterclosed-loop linearity can be expected for the double nestedamplifier assuming the same open-loop nonlinearity. Note thatat 100 kHz there is still an improvement when using a doublenested configuration.

IV. NEW AMPLIFJER TOPOLOGYThe circuit schematic of the new four-stage amplifier is

shown in Fig. 4. Because of the symmetry of the circuit onlythe left half section is analyzed. The input stage (iW1-A49) is afolded gain stage. Input devices are p-channel to lower flickernoise. Their gm is not very high so that the compensationcapacitors resulting from (7) have a reasonable value for thegiven bandwidth. This also produces a good slew rate behavioreven if the bias current of the input transistors is quite small(12.5,uA).The second stage is a noninverdng gain stage composedof a common-source p-channel input (M1OA), a current

mirror (All 1A, Lf12A), and a fixed current source (&f13A)of 25 ,uA. The third stage (M14AI1419A) is similar to theprevious one but of the complementary type. M15A is a fixedcurrent source of 50 MA. The output stage (iW20A, M2~A)uses a class AB topology with the p-channel transistor drivenby the output of the third stage and the n-channel by the outputof the second one. Note that the amplifier has a four-stagetopology only from the input to the p-channel output transistor,while from the input to the output n-channel it has a three-stage topology. The gain difference from the input to the gate


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PERNICI et al,: CMOS LOW-DISTORTION FULLY DIFFERENTIAL POWER AMPLIFIER 761

vhlt rNPLrTL

vin-STAGE

Vcc1CM1....% OUT+ OUT-VCMd h-cl CzCS TT T T c : m7+7 ?-k

Fig. 5. Common-mode feedback circuit.

of these two output transistors is partially compensated by thelarger gm of the n-channel output device.This configuration gives a tight control on the value of

the quiescent current in the output transistors whose nominalvalue is 750 pA. The standard deviation of this current overall possible process variations was measured to be only 8%. Infact, the main source of fluctuations of the quiescent current isthe mismatch in the current ratio between ivl14A and iW20Athat is quite small.There are two compensating capacitors (CIA and C72A)

from the amplifier output to the outputs of the first and secondstage. A third compensation capacitor (C3A) is inserted fromthe amplifier output to the source of the common-gate n-channel device (Ivf17A) placed at the output of the thirdstage. Therefore, the two more external nested compensationloops are of the Miller type, while the internal one realizesa cascode-type compensation [10]. The output pole of theamplifier resulting from the insertion of the compensationcapacitor C3A is at a higher frequency than that which wouldresult from a normal Miller loop. In fact, the frequency of thispole is approximately

C3Af,m . 4 _2Tr(CL + C3A) C~3 (8)where Gm4 is the transconductance of the p-channel outputtransistor and CP3 is the parasitic capacitance at its gate. Thus,fb~ is increased by a factor equal to C3A/CP3 with respectto a normal Miller loop. This helps to increase overall stabilityin the presence of a capacitive load. Using this approach theoutput pole is moved to a higher frequency leaving morespace between itself and the unity-gain frequency to place theother two high-frequency poles resulting from the insertion ofCIA and C2A. Also the amplifiers power supply rejectionis improved in this way [10]. The maximum increase in thefrequency of this output pole is limited by the parasitic poleat the source of iM17A which is located at the frequencyGrn &f17A/ zfl(C3A + C@ A.!f17A). Trying tO fu rth er in crea se th efrequ en cy of th e ou tpu t pole r es u lt s in com p lex poles givin ga peak in g in th e frequ en cy respon s e.A dynamic common-mode feedback has been used as shown

in Fig. 5 [11]. A voltage related to the average value ofthe outputs is taken through a switched-capacitor networkand is applied to an inverting stage in order to have theright polarity for the common-mode correction signal at nodeliVCLfl? In this way the common-mode feedback loophas the same poles as the differential loop plus the pole

Fig. 6. Chip microphotograph,.9 0 I 1 1.. !.[.! .!!.. !lI 1 1 1,-88 f=ltd l --- . . . ..=-86-84-82T.H.D [dB].80

-78-76.74-72 11111111111111 ,1111,111111111,1 ,-

3.5 4.0 4.5 5.0 5,5 6.0 6,5 7.0 7.5Vout [volt]

Fig. 7. Measured THD versus output swing with500 () and 100Q ( )load at various frequencies.

associated with the node IiVCMF. This extra pole, however,is at a much higher frequency than the unity-gain frequency.Thus, a similar bandwidth for both the main amplifier andthe common-mode amplifier can be obtained. This type ofcommon-mode feedback is highly linear so that there is nodistortion degradation due to its presence. Moreover, it doesnot increase power dissipation.The device sizes for the amplifier are reported in Table I.

V. EXPERIMENTAL RESULTSA microphotograph of the differential amplifier is shown

in Fig. 6. The amplifier is implemented in a 1.5-~m CMOSn-well double-metal, single-poly technology with implantedcapacitors (poly/n+). The overall active area is 0.625 mm2.Fig. 7 shows the measured total harmonic distortion versus

OUtDUt swing with loads of 50 and 1000 and a power supply. . .


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762 IEEE JOURNAL OF SOLID -STATE CIRCUITS, VOL. 28, NO . 7, JULY 1993

Fig. 8. Amplifier step response.

TABLE ICOMPONENTIZESMl= M2M3 = M4M5 = M6Ml= M9M8M1OA = M1OBM1 lA = M1 lBM1 2A = M1 2BM1 3A = M1 3BM1 4A = M1 4BM1 5A = M1 5BM1 6A = M1 6B

.500/ 51 0 0/ 81 5 0/ 21 0 0/ 62 0 0/ 61 0 0/ 450 /2 .550 /2 .52 0 0/ 6200 /1 .52 0 0/ 83 0 0/ 2

M1 7A = M1 7BM1 8A . M1 8BM1 9A = M1 9BM2 0A . M2 0BM2 1A = M2 1BCIA = CIBC2 A = C2 BC3 A = C 3BMCM1MCM2 = MCM3cl= C2Cs l = CS2

3 0 0/ 250 /2 .550 /2 .53000 /1 .53500 /1 .517 .5pF5 PF12 pF2 0 0/ 65 0/ 83 .6 r IF1 .2 P F

of 5 V at three different frequencies (1, 10, and 20 kHz). In theaudio band, distortion at 6 VP_P is always lower than 77 dBfor 500 and -80 dB for 100 Q. There is no significant linearitydegradation up to a voltage swing of 7 VP-P. This limit couldbe increased even more enlarging the output transistors. Nodegradation in linearity for small input levels due to crossoverdistortion has been detected.In the previous measurements and in all the following onesan inverting configuration with unity gain is assumed andthe capacitive load is intended to be 250 pF. However, thebehavior of the circuit remains unchanged for capacitive loadsfrom O to 1 nF.Fig. 8 shows the step responses of the amplifier in unity-gain

configuration in case of a large step of 7 VPP and a small oneof 100 mVP-P with a load of 50 ~ and 200 pF. The responseis quite clean demonstrating that a good stability is achieved.PSR is always better than 72 dB up to 90 kHz.There is no significant variation in the obtained results if

a 3-V power supply is used and a reduced output swing of2 VP-P is considered. This swing could be increased simplyenlarging the output transistors.The main amplifier performances are summarized in Ta-

ble II.

VI. CONCLUSIONSA fully differential power amplifier with four stages of

gain was presented. The double nested Miller compensationapproach used leads to very low distortion. The reported circuitoperates from a single power supply with a minimum value

TABLE IIAMPLFtER PERFORMANCESUMMARY

VDD = 5V @ T=25C @ Vou t / Vin = 11.5- Mm CMOS doub l e me ta l, s in g ie po ly si li co n

Quiescen t Power Dis sipa tion 10 mWUnity Gain Bandwidth 2 MHzSlew Rate 1.5V / psecOutput Noise (AudioBand-Pass ) 1 0 p vArea 0.625 mmzTotal Harmonic Distortion

Vout=7Vpr), f=1KHz, ~=50Q -86 dBPower Supply Rejection

f= 1KHz >90 dBf= 100KHz 71 dB

of 3 V (in this case the input and output voltages must beproperly scaled).The amplifier is stable for a wide range of loads, both ca-

pacitive and/or resistive. This design demonstrates that robustamplifiers can be designed with a number of stages in excess ofthree. Stable operation can be achieved with a small reductionin bandwidth, which nevefiheless produces a large linearityimprovement in the audio band and beyond.In the audio band measured distortion is about 20 dB smaller

than that of a similar amplifier with one less gain stage and us-ing a simple nested Miller compensation (obtained suppressingthe first intermediate gain stage). This confirms experimentallyhow, starting from the same sources of distortion, the amplifiertopology can drastically change the closed-loop linearity.Furthermore, simulations show that in some cases (e.g.,

if only the telephone band is important) going to an evenhigher number of stages (e.g., 5) can further improve linearity.Alternatively, the same distortion can be achieved with smallerpower consumption. This opens new possible solutions forpower amplifier design.

ACKNOWLEDGMENTThe authors would like to thank S. Mariani for the careful

layout.REFERENCES

[1J G. Nicolliniet al., A 5V CMOS programmable acoust ic f ront-end forISDN terminals and digi tal t elephone sets, in Proc. ESSCIRC, 1992,pp. 229232.


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[2]

[3][4][5]

[6]

[7]

[8][9]

[10]

[11]

J. H. Hui jsing and D. Linebarger, Low-voltage operational ampli fierwith rai l- to-rai l input and output ranges, IEEE J. Solid-State Circuits,vol. SC-20, pp. 11441150, Dec. 1985.M. Pardoen and M. Degrauwe, A rai l- to-rai l input/output CMOS poweramplifier, I EE EJ , S ol id -S ta te C irc ui ts , v ol . 2 5, pp. 501504, Apr. 1990.L. Tomasini, A. Gola, and R. Castello, A fully differential driver forISDN~ IEEE J. Solid-State Circuits, vol. 25, pp. 546-554, !,pr. 1990.F. Opt Eynde, P. Ampe, L. Verdeyen, and W. Sansen, A CMOS large-swing low-dis tort ion three-stage class AB power amplif ie r, IEEE J,Solid-State Circuits, vol. 25, pp. 265273, Feb. 1990.R. Castello, G. Nicollini, and P. Monguzzi, A high-linearity 50- QCMOS differentia l driver for ISDN applicat ions , IEEE J. Solid-StateCircuits, vol. 26, pp. 18091816, Dec. 1991.H. Khorramabadi, J. Anidjar, and T. R. Peterson, A highly efficientCMOS line driver with 80-dB linearity for ISDN U-interface appli-cations, I EE E J . S ol id -S ta te C irc ui ts , vol. 27, pp. 17231729, Dec.1992.P. R. Gray and R. G. Meyer, A na ly si s a nd D esi gn o f A na lo g I nt eg ra te dCircuits, 2nd ed. New York: Wiley, 1984.R. G. H. Heschauzier, L. P. T. Kerklaan, and J. H. Huijsing, A1OO-MHZ 100-dB operational amplifi er wi th mul tipath nested Millercompensation structure, IEEE J. Solid-State Circuits, vol. 27, pp.17091722, Dec. 1992.B. K. Ahuja, An improved frequency compensation technique forCMOS operational amplifiers, IEEE J. Solid-State Circuits, vol. SC-18,pp. 629-633, Dec. 1990.D. Senderowicz, S. F. Dreyer, J. H. Huggins, C. F. Rahim, and C. A.Laber, A fami ly of dif feren tial NMOS analog circu its for a PCM codecfilter chip, lHZE J. Solid-State Circuits, vol. SC-17, pp. 10141023,Dec. 1982.

Sergio Pernici (S80-M85) was born in Bergamo,Italy, in 1958. He received the degree in electronicengineer ing from the Politecnico dl Milamo, Milan,Italy, in 1984.S ince 1985 he has been with ST SGS-Thompson

Microelect ronics, Agrate, Mikmo, Italy, where heis involved in the design of analog and mixedanalog/digital integrated circuits for telecommuni-cations. He has contr ibuted to the designl of severalcommercial CMOS integra ted circui ts inc ludlng STM5913/14/16/17, ST 5080, ST 5088. He holds three

patents granted in the U.S. and Europe.

Germano Nicollini was born in Placenza, Italy in1956. He received the degree in elec tronic engineer-ing from the University of Pavia in 1981.Since 1982 he has been with ST SGS-Thomson

Microelectronics, Milano, Italy, where he is in-volved in the design of analog and mixed in tegratedcircuits for telecommunications. He was ProjectLeader of the M5913/14/16/17 ST COMBOS andthen he became responsib le for the design of acous-tic front-ends for ISDN terminals and digital tele-rIhone sets. At the mesent time. he is in chame of

a group for the developm&t of acoustic f ro~t -ends for cordless and cefirr lartelephones. During part of the academic years 19901991 and 19911992he was a Vkiting Professor at the University of Geneva. He holds severalpending patent s and 14 paten ts gran ted abroad .

Rhaldo Castello (S78M84SM92) was bornin Geneva, Italy, 1953. He received the degree ofIngegnere (summa cum laude) from the Universityof Geneva, Italy, in 1977. In 1979 he began his grad-uate s tudy at the Univers ity of California, Berkeley,where he received the M.S .E.E. degree in 1981 andthe Ph.D. degree in 1984. While at Berkeley he wasa Teaching Assistant.Both in 1983 and 1984 he was a Visiting Pro-

fessor during part of the academic year at theUniversity of Geneva. From 1984 to 1986 he was

a Visi ting Assistant Professor at the Univers ity of California, Berkeley. Since1987 he has been an Associate Professor with the Department of ElectricalEngineer ing at the University of Pavia, Italy, and a consul tant with ST SGS-Thomson Microelectronics , Milan, I taly. Hk main interes t is in c ircuit des ign,par ticularly in the area of telecommunica tions and analog/digital interfaces .Dr. Castello has been a member of the program Committee of the European

Solid-S tate Circuits Conference (ESSCIRC) since 1987 and he was ProgramChairman of ESSCIRC 91 held in Milan. He was a Guest Editor for the July1992 , issue of the IEEE JOUXNALOF SOLID-STATECIRCUITS.Since 1992 he hasb een a m em ber of th e p rogram Com mittee of th e In tern ation al Solid -StateC ir cu i ts Con fer en ce (ISSCC).

double nested miller

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