Nested Miller Compensation Using Current Buffers for Multi-stage Amplifiers

Annajirao Garimella, M. Wasequr Rashid and Paul M. Furth Klipsch School of Electrical and Computer Engineering,

New Mexico State University, Las Cruces, NM 88003, USA

Email: garimella@ieee.org, mrashid7@gatech.edu, pfurth@nmsu.edu

Abstract-Firstly, a literature review of existing nested Miller compensation (NMC) schemes for low-voltage multi-stage am­plifiers is made. Secondly, a novel nested Miller compensation using two current buffers (NMCCB) in the feedback network is introduced. As opposed to previous NMC schemes, this scheme uses a non-inverting gain stage for the first stage and inverting gain stages for both the second and third stages. An inverting current buffer is utilized for the first time whereas previous NMC feedback networks utilized a positive current buffer. In conventional NMC, the major limitation is bandwidth since inner compensation capacitance loads the output node. In the proposed scheme, the two current buffers in the feedback network create two LHP zeros, canceUing one of the non-dominant poles and extending the bandwidth. Detailed small-signal modeling and analysis of the NMCCB compensation network is presented, demonstrating the effectiveness of this strategy.

I. INTRODUCTION

As supply voltages scale down with advanced process

nodes, low-voltage, high-gain amplifiers are realized by cas­

cading multiple gain stages. However, each gain stage in­

evitably introduces low-frequency poles which require ad­

ditional frequency compensation capacitors for stability. For

this purpose, compensation of multi-stage amplifiers using

nested Miller compensation (NMC) techniques have been

introduced [1]-[11]. Fig. 1 shows a generic three-stage amplifier using NMC

topology. The inherent limitation of this topology is limited

bandwidth, since inner loop compensation capacitance CC2 loads the output node. Hence reverse NMC (RNMC) is often

chosen as an alternative.

Now, the addition of a voltage follower or a current buffer

in the feedback network introduces an LHP zero and extends

the bandwidth. To this end, a novel NMC using two current

buffers (NMCCB) in the feedback network is introduced. As

opposed to previous conventional NMC schemes, this work

uses a non-inverting gain stage for the first stage and inverting

gain stages for both the second and third stages. Using an

inverting stage as the second gain stage reduces the quiescent

current, transistor count and silicon area.

This paper is organized as follows: A comprehensive survey

of existing NMC schemes and pole-zero analysis is made in

Section II. Section III discusses the choice of using a low­

quiescent current inverting stage as the second gain stage. The

proposed NMCCB is introduced and analyzed in Section IV, followed by conclusions in Section V.

Fig. l. Generic NMC topology.

II. NESTED MILLER COMPENSATION TOP OLOGIES

A. Generic NMC topology

Let the Om, output resistance and lumped parasitic capac­

itance of ith stage be represented by gmi) Ri and Ci respec­

tively. CL is the load capacitance. The two NMC capacitors

CCI and CC2 in Fig. 1 form feedforward paths at higher

frequencies, resulting in RHP zeros.

Assuming that the CiS « CCl) CC2) and CL, and the poles

are widely separated, small-signal analysis yields the transfer

function given by [4],

ANMc(s) �

where the dc voltage gain ADc is given by

ADc = gmlRlgm2R2gm3R3.

and the dominant pole is given by

1 Wp3dB =

(1)

(2)

(3)

The above transfer function indicates two RHP zeros and three

LHP poles, if gm3 > gm2.

B. NMC using Nulling Resistor

To eliminate the RHP zeros, NMC using nulling resistor

(NMCNR) was proposed in [4] and is shown in Fig. 2. The

resistor Rm added in series to the compensation capacitances

978-1-61284-857-0/11/$26.00 @)2011 IEEE

Rm

C3lCL

Fig. 2. NMC using nulling resistor (NMCNR) topology, adapted from (4).

Fig. 3. Multi-path NMC (MNMC) topology, adapted from [I), (2).

eliminates the non-dominant RHP zero and instead creates an

LHP zero.

The dominant LHP zero is given by

1 Wzl =

CClRm + CC2 (Rm - 1/gm3)' (4)

By equating Rm to 1/gm3, the dominant zero becomes

(5)

C. NMC with Feedforward Transconductance (Gm) Stages

In [1]-[3], [5], [6], [8], feedforward transconductance (Gm) stages are added to cancel the RHP zeros introduced by Miller

compensation capacitances and improve stability. However,

these feedforward Gm stages increase the circuit complexity,

power consumption and silicon area.

Fig. 3 shows the mUlti-path NMC (MNMC) topology [1],

[2], where a feedforward Gm stage gmfl added from the input

to intermediate node V2 of the amplifier, creates a dominant

LHP zero, given by

gmlgm2 Wzl = - .

CClgmfl (6)

This dominant LHP zero cancels the second non-dominant

pole, extending the bandwidth. However, this technique re­

quires additional circuitry and power consumption for the

feedforward Gm stage.

Fig. 4 shows NMC with feedforward Gm topology

(NMCF) [6], where a feedforward Gm stage gmf2 is added

from the intermediate node V2 to the output of the amplifier.

The essential difference between MNMC and NMCF is the

Cel .--------1

Fig. 4. NMC with Feedforward Gm (NMCF) topology adapted from (6).

Fig. 5. NMC with feedforward Gm stage and nulling resistor (NMCFNR) topology adapted from (5).

feedforward Gm stage gmfl is removed, and feedforward Gm stage gmf2 is introduced, where gmf2 2:: gm2 [6]. The equation

for the dominant zeros can be found in [6].

NMC with feedforward Gm stage and a nulling resistor

topology (NMCFNR) [5] is shown in Fig. 5, where a nulling

resistor Rm is used to eliminate the RHP zeros. When gmf2 > gm2 and Rm = 1/(gmf2 + gm3), the system will have only

one LHP zero, given by

__ [ CCI + CC2 +

CC2 (gmf2 - gm2) ] -1

Wzl -gmf2 + gm3 gm2gm3

(7)

Another topology, nested Gm capacitance compensation

(NGCC) [3], shown in Fig. 6, uses a total of n-1 nested

feedforward Gm stages for an n-stage amplifier. However, the

circuit complexity and power consumption is much more in

NGCC than in NMCF and MNMC.

Active feedforward frequency compensation (AFFC) was

introduced in [8], and is shown in Fig. 7. It has one feedfor­

ward path through gmf2 and one feedback path through gmCG and CCI. The inner loop uses compensation capacitor CC2 from the intermediate node V2 to the output of the amplifier.

This configuration introduces an LHP zero at

(8)

III. NON-INVERTING SECOND STAGE IN NMC

The three-stage amplifiers employing the above mentioned

NMC topologies required a second stage that is non-inverting.

The low-voltage non-inverting stage is often realized using a

gmf1

'----1+1-----------'

Fig. 6. Nested Gm Capacitance Compensation (NGCC) topology, adapted from [3].

9.cG

Fig. 7. Active feedforward frequency compensation (AFFC) topology, adapted from [8] .

common-source amplifier with an output mirror, as shown in

Fig. 8. In [7], a second differential amplifier forms the non­

inverting stage.

If the non-inverting second stage of Fig. 8 were replaced

with an inverting stage, a simpler common-source amplifier

could be used, thereby eliminating the quiescent current in

one branch, as well as the corresponding transistors. IV. PROPOSED NMCCB TOPOLOGY

The proposed NMC using Current Buffers (NMCCB) is

shown in Fig. 9. NMCCB uses a non-inverting gain stage for

the first stage and inverting gain stages for both the second

and third stages.

A. Feedback Network

NMCCB topology utilizes two current buffers in the feed­

back network: a positive current buffer 9mCG in the inner loop

and an inverting current buffer 9mBU in the outer loop. The

two current buffers obviate the feedforward path and introduce

two LHP zeros.

B. Small-signal Analysis

The small-signal analysis of Fig. 9 yields five poles and two

LHP zeros. Neglecting the two very high frequency poles, the

transfer function can be approximated as

v,

Fig. 8. Typical implementation of non-inverting second gain stage in a NMC topology, adapted from [6].

Vin

Fig. 9. Proposed Nested Miller compensation using Current Buffers (NM­CCB) topology.

(1 + _8 ) (1 + s..!k:L) (1 + s CT ) . Wp3dB g",CG g",BU R1g",2R2g",3

where ADc is the dc gain given by

ADC = 9m1Rl9m2R29m3R3,

and the dominant pole Wp3dB is given by

1 Wp3dB = --------­

Rl CCl9m2R29m3R3

The two LHP zeros are given by

9mCG wz,CG=- -

C C2 9mBU

Wz,BU=- -C C1

(9)

(10)

(11)

(12)

(13)

Note that the second pole is exactly canceled by the LHP zero

created by the inner loop. This results in a two-pole, one-zero

system as shown in Fig. 10. Placing the outer loop LHP zero

close to the dominant pole results in bandwidth extension. This

proposed scheme overcomes the limitation of bandwidth, often

posed by conventional NMC topologies.

The gain-bandwidth product is given by

A 9ml

WGBW � DCWp3dB = Cc

(14)

The phase margin of the amplifier can be calculated from

PM�90o+tan-l ( WGBW ) -tan-1 (WGBW ) (15) WZl,BU Wp3

Non-dominant poles

Uncompensated

ffiP3 ffiP2 C9>3dB

NMCCB

ffiZ,CG ffiZ,BU

ffiP3 ffiP2 ffi P3d

Im

Fig. 10. Diagram illustrating pole-zero locations (not to scale).

C. Transisor-Ievel Implementation of Current Buffers

A positive current buffer can often be implemented using

a simple common-gate transistor [11]-[14] or as a current

follower [15]. Fig. II(a) shows the generic implementation

of cascode compensation. This current buffer introduces an

LHP zero given by (12).

An inverting current buffer can be implemented using a

current mirror, as shown in Fig. II(b) [13], [16]-[19]. This

compensation network introduces an LHP zero, given by (13).

Further details on the implementation of frequency compen­

sation techniques using current buffers can be found in [20].

Typically a common-gate (cascode) transistor or a current

mirror is inherent to the differential amplifier of the first

stage and can be utilized as an inverting current buffer. Hence

the implementation of current buffers does not require addi­

tional circuitry, thereby introducing no additional static power

consumption or area overhead. Additionally, employing an

inverting stage as a second gain stage eliminates the quiescent

current in one branch, as well as the corresponding transistors.

�mBU X CC1 Y - t--o

1 9mBU

(a)

(b)

Fig. II. Block diagram and transistor implementation of compensation networks using current buffers: (a) Cascode compensation (b) Compensation using current mirror as inverting current buffer.

V. CONCLUSION

Existing NMC topologies are reviewed. Novel NMC us­

ing current buffers for three-stage amplifiers is introduced,

overcoming the existing inherent limitations. This scheme

employs an inverting stage as the second gain stage, reducing

quiescent current and allowing the use of an inverting current

buffer in the outer-loop. Simple design equations, accurately

predicting the pole-zero locations and phase margin are de­

veloped. Possible transistor-level implementation of current

buffers is elucidated. This scheme finds applications in multi­

stage amplifiers and low-dropout (LDO) voltage regulators.

ACKNOWLEDGMENTS

Sincere thanks to Punith R. Surkanti for typesetting the

paper.

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