discrete cad flow project - ieee web...

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, Ready Play, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc.

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc.

2 TM

Agenda • Motivation • Modeling challenge • Review of conventional approaches • Multiphysics modeling • Conclusions


3 TM

Introduction

• Freescale Semiconductor designs and manufactures high-power RF transistors for wireless infrastructure markets.

• Non-linear electro-thermal models of the transistors are available for download: http://www.freescale.com/rf/models


4 TM

Inside an RF Power Transistor

Transistors

Gate Lead

Drain Lead

MOS capacitors

Flange

Integratedcapacitor

Ceramicsubstrate

Array ofbonding-wires

500 mil

This packaged transistor operates at 2.1 GHz and is capable of producing 300 W (CW) output power


5 TM

Conventional Modeling Techniques


6 TM

The Modeling Challenge

• How do we enable a CAD-based design flow ?

MOScap EM Simulation Capability

Transistor Models

Package Simulation Capability

EM Bondwire Simulations & ADS BONDW model

6


7 TM

Modeling Approach • Separate the package and matching networks from the

transistor

Linear problem (electromagnetic)

Non-linear modeling (electrothermal)

P. H. Aaen, J. Wood, and J. A. Pla, Modeling and Characterization of RF and Microwave Power FETs, Cambridge University Press, 2008


8 TM

The Power Transistor

A power transistor is a large device! • It may be a significant fraction of a wavelength wide

⇒ distributed effects • It generates a lot of heat ⇒ good thermal model • It presents a very small impedance which is difficult to

measure − Wg ~ 80 – 300 millimetres per die

~ 1 cm


9 TM

The FET2 Model Architecture

A technology-independent approach: a platform for nonlinear FET models

J. Wood, P. H. Aaen et al, “A nonlinear electro-thermal scalable model for high-power RF LDMOS Transistors”, IEEE MTT Trans., Feb 2009, pp 282-292.


10 TM

The Model Extraction Process

[ ]Y

…at every value of (Vgs, Vds)

dVgs dVds Qg QdIg Id

Gate Drain

Source

De-embed manifolds, extrinsics Pulsed I-V & S-parameters

Small-signal model Large-signal model

10 20 30 40 50 60 700 80

-0

100

200

300

400

-100

500

VDS (V)

IDS

(m

A)

∫


11 TM

The Nonlinear Intrinsic Model

• Process-independent model architecture

• Gate current set to zero for LDMOS

• Measurement-based model • Analytic functions for better

convergence & extrapolation • Charge-conservative model for better

distortion modeling • Compatible with thermal model

Qg QdIg Id

Gate Drain

Source


12 TM

The Nonlinear Intrinsic Model

• Gate current set to zero for LDMOS, drain current:

• Analytic functions for better convergence & extrapolation • Charge-conservative model for better distortion modeling • Artificial Neural Networks (ANNs) model the Q-surfaces.

( ) ( )2

gst dsd ds

gstgst

1 tanh 1 11.0

VBREFFpsatplin

Beta V V AlphaI LAMBDA V K eVV

VL

⋅ ⋅= ⋅ + ⋅ ⋅ ⋅ + ⋅ +

0

200

400 -10

0

10

-100

-50

0

50

VgsVds

Qd

10 20 30 40 50 60 700 80

-0

100

200

300

400

-100

500

VDS (V)

IDS

(mA)

Model Measured


13 TM

Charge Surfaces

• Artificial Neural Networks (ANNs) model the Q-surfaces. • Extrapolation outside the measurement domain is smooth

0200

400 -20-10

010

20-50

0

50

100

VgsVds

Qg

-20 0 20 40 60 80 100-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

x 10-11

Vds

Qg

MeasuredANN


14 TM

• Link the thermal dynamics to power dissipation self-consistently

• Solve ODE for average power dissipation

• 'Derate' drain current from nonlinear intrinsic model

Adding the Thermal Model

( ) ( )0 0( ) ( ) ( ) avgdiss d ds avg thth

dP T T dP t i t v t P C T Tdt R dt

τ−

= = + = + −

0

( )1 ( )

isod

davg T amb

ii TP T Tδ γ

=+ + −

CthPdiss Rth

Vambient

Trise

δ = Rth/T0, and γT = δ/Rth = 1/T0


15 TM

Transistor Model Validation: Loadpull Contours

20 30 40 50 60 70 8050

60

70

80

90

100

110

Resistance (Ω )

Rea

ctan

ce (Ω

)

ModelMeasurement

Max PAE = 63.7 %

20 30 40 50 60 70 8050

60

70

80

90

100

110

Resistance (Ω )R

eact

ance

(Ω

)

ModelMeasurement

Max Simuated = 21.8 dB

Max Measured = 21.8 dB

Power-Added Efficiency Output Power

HV6 2.4 mm periphery; 2 GHz; Vdd = 28 V, Idq = 6 mA/mm

J. Wood, P. H. Aaen et al, “A nonlinear electro-thermal scalable model for high-power RF LDMOS Transistors”, IEEE MTT Trans., Feb 2009, pp 282-292.


16 TM

Transistor Model Validation: PAE & Output Power

-20 -15 -10 -5 0 5 10 15-20

-10

0

10

20

30

40

Out

put P

ower

(dB

)

Input Power (dBm)

-20 -15 -10 -5 0 5 10 150

20

40

60

PAE

(%)

-20 -15 -10 -5 0 5 10 150

10

20

30

40

50

60

-20 -15 -10 -5 0 5 10 150

10

20

30

40

50

60

-20 -15 -10 -5 0 5 10 150

10

20

30

40

50

60MeasuredNew Model

HV6 2.4 mm periphery; 2 GHz; Vdd = 28 V, Idq = 6 mA/mm


17 TM

Package and Matching Networks

• The passive components surrounding the die: − Package − Arrays of bondwires − Planar components: matching capacitors − Plastic encapsulation

• Bondwires are not parasitic elements they are integral components of the matching network

Die

Matching capacitors

Package Integrated capacitor

Internal Profile of a Power Transistor


18 TM

Array of Wires: Simulation vs. Measurement

spacing 20 mil 1.5 mil diameter, gold Loop height 50 mil

0 2 4 6 8 10-40

-30

-20

-10

0

Frequency (GHz)

|S11

| (dB

)

air

plastic

0 2 4 6 8 10-8

-6

-4

-2

0

Frequency (GHz)

|S21

| (dB

)

plastic

air

Measurement FEM


19 TM

Array of Wires: Simulation vs. Measurement

• To examine the effects of the loss the conservation factor can be computed from the S-parameters: CF = 1 - |S11|2 - |S12|2

0 2 4 6 8 100

0.005

0.01

0.015

0.02

0.025

0.03

Con

serv

atio

n Fa

ctor

Frequency (GHz)

Plastic

Air

Measurement Simulation


20 TM

Modeling Matching Capacitors

• Method-of-Moments (MoM) is used to simulate the MOS capacitor.

Cross Section

~125 um

Top Metal Oxide

Lossy Silicon

~ 1-2 um

Backside Metal

Microstrip transmission lines

MOS Capacitor

Exterior box of the simulator


21 TM

Modeling Matching Capacitors

• On-wafer transmission lines use to obtain material parameters. • Simulate as a planar microstrip circuit.

0 2 4 6 8 10-50

-40

-30

-20

-10

0

Frequency (GHz)|S

11| (

dB)

Width = 50 um

Width = 20 um

MeasuredSimulated

GSG transmission lines

P. H. Aaen et al., “On the development of CAD techniques suitable for the design of high-power RF Transistors,” IEEE MTT Trans., Oct 2005, pp. 3067-3074.


22 TM

Package Modeling

500 mil

390 mil

20 m

ilEmpty NI-880 package

0 1 2 3 4 5-180

-160

-140

-120

-100

-80

-60

-40

Frequency (GHz)Ph

ase

S 11

(deg

)

Measurement FEM

• Full-wave EM simulations are used to model the package.


23 TM

Modeling Package & Matching Networks

0 1 2 3 4-14

-12

-10

-8

-6

-4

-2

0

Frequency (GHz)

|S11

| (dB

)

MeasuredFull-waveInductance only

0 1 2 3 4-200

-100

0

100

200

Frequency (GHz)

Phas

e S 1

1 (d

eg)

MeasuredFull-waveInductance only

• NI-880 package • Four 22pF MOS capacitors • 16 wires, 1 mil diameter • Wire separation 10 mil


24 TM

Electromagnetic Design within ADS • All components have been designed for EM simulation • Layer files & substrates pre-setup • Add ports and simulate

Layout view 3D-EM view


25 TM

102mm ITM/OTM in NI780 Full FEM Model: S-Parameters

Bias: 28V, 600mA


26 TM

102mm ITM/OTM in NI780 Full FEM Model: Load Pull 2.14 GHz


27 TM

The Need for Multiphysics


28 TM

‘Typical’ Temperature Distribution

Unexpected Temperature Distribution

140 oC 115 oC

Layout & Performance Optimization • Small changes to gate manifold

metallization resulted in very dramatic differences in the device behaviour

Efficiency: 60-40% • Temperature distributions in

large power die known to sometimes exhibit unexpected behaviour

• Multiple peak temperatures – a function of load and frequency

E. M. Johnson, P. H. Aaen, et al, ARFTG79 pp125–129 (2012)


29 TM

Global Modeling Philosophy

• EM model of device metallization

• Thermal Impedance model of device structure

• Physical model of single gate finger gives terminal electrical behaviour

• Combine in ADS

• Fast simulation

Figures from: Denis, Snowden, Hunter, IEEE Trans MTT 54(6) pp2465-70 (2006)


30 TM

• NI-360 package: 8 wires on gate, 12 on drain

• 102-mm, with 6-mm dead • 500um UGW • Measured results: 40-60% PAE

depending on the gate manifold

Transistor Layout & Gate Metallization

Discrete-like Bondpads

Uniform Bondpad


31 TM

The Global Model

Active Area Metallization (Sonnet Simulation) Thermal Model (ANSYS Simulation)

GSG PAD and Launch (Measured Thru)

Manifolds (Sonnet Simulation)

Base FET model (one per Finger)

Gate

FT1 FT2 FT3 FT4 FT5 FT6 FT7 FT8

GB3_Thermal_Model X11

R R1 R=24 Ohm

G1

D1

Src FT1

SELFT=SELFT TSNK=TSNK

Base_FET2_GB3_1Finger X2

G2

D1

Src FT2



G2

D2

Src FT3



G3

D2

Src FT4



G4

D3

Src FT6



G4

D4

Src FT7



G5

D4

Src FT8



G3

D3

Src FT5



GM5 GM4 GM3 GM2 GM1

G1 G2 G3 G4 G5

DM4 DM3 DM2 DM1

D1 D2 D3 D4 GB3_extrinsic_network_Sonnet_noRtap_OptPort X10

D1 D2 D3 D4

DM1

DM2

DM3

DM4

G5 G4 G3 G2 G1

GM1

GM2

GM3

GM4

GM5

Drain

Src S2P SNP4 File="Loc-11-10-wfr03-x2y4-m1_FxB_dcEst.s2p"

2 1

Ref

Port P2 Num=2

Gate

Src

S2P SNP3 File="Loc-11-10-wfr03-x2y4-m1_FxA_dcEst.s2p"

2 1

Ref

Port P1 Num=1

Src Port P3 Num=3

GM5

GM1 GM4

GM2

GM3

Src

S6P SNP1 File="GB3_Manifolds_Gate_n_port_NoFeed.s6p"

1 5

4

6

3 Ref 2

DM3 DM2

DM4

DM1

Drain

Src

S5P SNP2 File="GB3_Manifolds_Drain_n_port_NoFeed.s5p"

5

1

4

3 Ref 2

VAR VAR1 TSNK=TSNK_C+273.15

Eqn Var

Thermal Model Transistors Metallization (buses)

Metallization (manifolds)

Bondwires, Package, etc.


32 TM

Transistor Simulation

• It’s impractical to use the schematic for realistic FETs; there are just to many to manage on a schematic page • Automated netlist approach

• Packaged FETs were re-measured and compared against measurement • Efficiency trend is present

• Incredible amount of data to analyze; voltages and currents available at every node. • 4 Mb file for every simulation

Simulation of the transistors at 2.2 GHz for 3 different manifolds, each terminated in its impedances for maximum efficiency with harmonics shorted.

(dashed is measured, solid simulated)

36 38 40 42 44 46 48 5010

20

30

40

50

60

70

Pout (dBm)PA

E(%

)

DiscreteUniformIn between


33 TM

Temperature Distributions

• Infrared microscopy measurements used to compare with simulated temperature distributions.

0 1 2 3 4 50

10

20

30

40

50

Distance Across Die (mm)Te

mpe

ratu

re R

ise

( oC

)

SimulatedMeasured

0 1 2 3 4 50

10

20

30

40

50

Distance Across Die (mm)

Tem

pera

ture

Ris

e ( o

C)

SimulatedMeasured

Uniform Bondpad Discrete Bondpad


34 TM

2030

40

0

2.5

5

-200

20406080

Pin (dBm)Position (mm)

Dra

in E

ffici

ency

(%)

Spatially Distributed Drain Efficiency vs. Pin

• With the voltages and currents available at all nodes we can compute many of the familiar PA metrics as functions of locations within the FET and of drive level.

• Dramatic differences are seen between the two cases.

Negative Drain efficiency?

2030

40

0

2.5

5 20

40

60

Pin (dBm)Position (mm)

Dra

in E

ffici

ency

(%)

Uniform Bondpad Discrete Bondpad


35 TM

Dynamic Loadline Construction

• The simulation results contain the voltages and currents at every node with full harmonic content. • simulated LSNA capabilities

• We can plot the loadlines of individual FETs to examine their behaviour.

• The individual FETs are operating very differently

Results for: Uniform Bondpad fo = 2.2 GHz Pin = [23, 37] dBm

0 10 20 30 40 50 60 70-0.1

-0.05

0

0.05

0.1

0.15

0.2

0.25

Drain Voltage (V)

Dra

in C

urre

nt (A

)

Location: End of die

-10 0 10 20 30 40 50 60 70-0.1

-0.05

0

0.05

0.1

0.15

0.2

0.25

0.3

Drain Voltage (V)

Dra

in C

urre

nt (A

)

Location: Middle of Die


36 TM

Spatially Distributed Waveforms

• From traditional FET theory and with the advent of LSNAs we can understand the behaviours of FETs from their time domain waveforms.

• In our large-transistors, we have many FETs all connected together distributed spatially

• We propose a new method to visualize the performance of large FETs. • Spatially Distributed Waveforms

Time

Volta

ge

Volta

ge

Time

Cur

rent


37 TM 20 40 60 80 100

1

2

3

4

5

6

7

Gate Runner No

Tim

e (n

s)

-2

-1

0

1

2

3

4

5

6

7

8Discrete Bondpad

Spatially Distributed Transistor Action • FETs are voltage

controlled current sources: • plot Vg and Id

• These plots are at P1dB

for each device

• Only the gate manifold changes in the simulation

• As expected what happens on the gate voltage changes the drain current.

20 40 60 80 100

1

2

3

4

5

6

7

Drain Runner No

Tim

e (n

s)

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

0.25

20 40 60 80 100

1

2

3

4

5

6

7

Drain Runner No

Tim

e (n

s)

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

0.25Current vs. time and position

Uniform Bondpad:

20 40 60 80 100

1

2

3

4

5

6

7

Gate Runner No

Tim

e (n

s)

-2

-1

0

1

2

3

4

5

6

7

8Voltage vs. time and position


38 TM

20 40 60 80 100

1

2

3

4

5

6

7

Drain Runner No

Tim

e (n

s)

0

10

20

30

40

50

60

Discrete Bondpad

Output Action of the FET

20 40 60 80 100

1

2

3

4

5

6

7

Drain Runner No

Tim

e (n

s)

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

0.25

20 40 60 80 100

1

2

3

4

5

6

7

Drain Runner No

Tim

e (n

s)

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

0.25Current vs. time and position

20 40 60 80 100

1

2

3

4

5

6

7

Drain Runner No

Tim

e (n

s)

0

10

20

30

40

50

60

Voltage vs. time and position Uniform Bondpad

• Plots of the drain voltage and current

• Again only the gate manifold changes in the simulation.

• These plots are at P1dB for each device

• Overlap of the current and voltage • This is why we had

a negative drain efficiency


39 TM

Conduction Angle / Area – Power Loss

• Conduction angle: the portion of the input cycle for which the transistor conducts and an output current flows. • The black areas are where power is being

conducted

• We have all of the harmonic information, effectively we can perform waveform engineering at the finger level using harmonic loadpull - distributed waveform engineering

20 40 60 80 100

1

2

3

4

5

6

7

Drain Runner No

Tim

e (n

s)

0

1

2

3

4

5

6

7

8

9

10

Power loss vs. time and position

Uniform Bondpad

20 40 60 80 100

1

2

3

4

5

6

7

Drain Runner No

Tim

e (n

s)

0

1

2

3

4

5

6

7

8

9

10

Discrete Bondpad


40 TM

Spatially Distributed Drain Current

Currents at the transistor drain 204 FET finger models

Discrete Bondpad Uniform Bondpad


41 TM

Spatially Distributed Power Loss

Discrete Bondpad Uniform Bondpad

Currents at the transistor drain 204 FET finger models


42 TM

Gate Manifold Simulated Current Distribution

• Current visualization on the manifolds shows differences between layouts.

• Simulations at P1dB for both cases. Currents visualized by linking ADS and Sonnet.

• Widely spaced discrete bond pads result in high current on the manifolds and in large voltage variations. − Poor excitation of FETs

Uniform Bondpad (~60% PAE at P1dB)

Discrete Bondpad (~40% PAE at P1dB)

Same current scale on both images


43 TM

Voltage at Gate Manifolds

• Voltage distribution across the gate manifolds results in transverse currents. − This distribution changes as function of time.

• For a FET to conduct the voltage on the gate must exceed the threshold voltage. − Not all FETs ‘turn-on’ at the same time


44 TM

Conclusions • We presented a detailed overview of the simulation and

modeling practices used to model our power transistors • Simulation enables accurate predictions of our power

transistors before they are built • We leverage a new paradigm of circuit simulation for our

large transistors whereby each finger is simulated in its realistic environment (EM, physical, and thermal).

• Developed a unique method and toolset for visualizing the spatial distribution of voltages, currents, powers, and temperatures, within the FET itself.

• Microscopic view proposes an alternative paradigm for device design and optimization.


45 TM

Acknowledgements • Daren Bridges • Dan Lamey • Lei Zhang • Travis Barbieri • Manuel Romero • John Wood

University of Surrey: • Prof. Sir Snowden • Prof. Kearney • John Everett

• Eric Johnson • Nelsy Monsauret • Jaime Plá

TM

Multiphysics Modeling of High-Power Microwave TransistorsAgendaIntroductionInside an RF Power TransistorConventional Modeling TechniquesThe Modeling ChallengeModeling ApproachThe Power TransistorThe FET2 Model Architecture The Model Extraction ProcessThe Nonlinear Intrinsic ModelThe Nonlinear Intrinsic ModelCharge SurfacesAdding the Thermal ModelTransistor Model Validation: Loadpull ContoursTransistor Model Validation: PAE & Output PowerPackage and Matching NetworksArray of Wires: �Simulation vs. MeasurementArray of Wires: �Simulation vs. MeasurementModeling Matching CapacitorsModeling Matching CapacitorsPackage ModelingModeling Package & Matching NetworksElectromagnetic Design within ADS102mm ITM/OTM in NI780�Full FEM Model: S-Parameters102mm ITM/OTM in NI780�Full FEM Model: Load Pull 2.14 GHzThe Need for MultiphysicsLayout & Performance OptimizationGlobal Modeling PhilosophyTransistor Layout & Gate MetallizationSlide Number 31Transistor SimulationTemperature DistributionsSpatially Distributed Drain Efficiency vs. PinDynamic Loadline ConstructionSpatially Distributed WaveformsSpatially Distributed Transistor ActionOutput Action of the FETConduction Angle / Area – Power LossSpatially Distributed Drain CurrentSpatially Distributed Power LossGate Manifold Simulated Current DistributionVoltage at Gate ManifoldsConclusionsAcknowledgementsSlide Number 46

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