ECE 556 Design Automation of Digital Systems

ByByProfProf. Charlie . Charlie ChungChung--Ping ChenPing Chen

ECE Department ECE Department UWUW--MadisonMadison

Outline

➤➤ Microprocessor Technology Trends and Design Microprocessor Technology Trends and Design IssuesIssues

➤➤ Interconnect delay trendsInterconnect delay trends➤➤ Circuit type trendsCircuit type trends➤➤ Research summaryResearch summary

Microprocessor Design Challenges

➤➤ High performance ( > 500 High performance ( > 500 MhzMhz))➤➤ Low cost (< $100)Low cost (< $100)➤➤ Low power consumption (< 10W mobile)Low power consumption (< 10W mobile)➤➤ More functionality (KNI MMX)More functionality (KNI MMX)➤➤ Shorter time to market (< 18 months)Shorter time to market (< 18 months)➤➤ Satisfies different market segments (server, subSatisfies different market segments (server, sub--

$1000)$1000)➤➤ CompetitionCompetition➤➤ ….….

Tentative Class Schedule

➤➤ Technology Trends (1 class)Technology Trends (1 class)➤➤ Interconnect Modeling and Optimization: (1 week)Interconnect Modeling and Optimization: (1 week)

➤➤ basic routing: mazebasic routing: maze--routingrouting➤➤ wirewire--sizing, buffersizing, buffer--sizing, buffersizing, buffer--insertioninsertion

➤➤ Introduction to Introduction to Verilog Verilog (1 week)(1 week)➤➤ Linear programming and Introduction to C and C++ language (1 weeLinear programming and Introduction to C and C++ language (1 week)k)➤➤ Routing: (2 week)Routing: (2 week)

➤➤ Clock routing (0.6 week)Clock routing (0.6 week)➤➤ Global and channel routing, Tree routing (1.4 week)Global and channel routing, Tree routing (1.4 week)

➤➤ Timing Analysis (1 week)Timing Analysis (1 week)➤➤ Delay Characterization, Power CharacterizationDelay Characterization, Power Characterization➤➤ PERL and Latch based timing analysis PERL and Latch based timing analysis

➤➤ Partitioning and Placement (1.5 week)Partitioning and Placement (1.5 week)➤➤ Floorplanning Floorplanning (1 week)(1 week)

Deal With It!

➤➤ Higher clock frequencies Higher clock frequencies ➤➤ New processes: 0.18 micron, copperNew processes: 0.18 micron, copper➤➤ Architecture levelArchitecture level

➤➤ SuperscalarSuperscalar, super, super--pipeline, outpipeline, out--ofof--order execution, order execution, speculative execution, EPIC, VLIW, ILP, speculative execution, EPIC, VLIW, ILP, multimulti--threadthread

➤➤ Circuit levelCircuit level➤➤ Aggressive dynamic circuits synthesisAggressive dynamic circuits synthesis➤➤ Sizing, parallel reSizing, parallel re--powering, logic minimizationpowering, logic minimization

➤➤ Physical DesignPhysical Design➤➤ PerformancePerformance--driven place and route, floorplaningdriven place and route, floorplaning➤➤ WireWire--sizing, buffersizing, buffer--sizing, buffersizing, buffer--insertioninsertion

Size of Team ExplodesSize of Team Explodes

Process Overview

➤➤ New process (0.18 um)New process (0.18 um)➤➤ High High aspectaspect ratioratio➤➤ Low sheet rho (resistance)Low sheet rho (resistance)➤➤ LowLow--εε dielectric (capacitance) (3.55 vs. 4.10)dielectric (capacitance) (3.55 vs. 4.10)➤➤ Good Good ElectromigrationElectromigration propertyproperty➤➤ 6 metal layers 6 metal layers

➤➤ M1 tight pitch for density (XM1 tight pitch for density (X--cap)cap)➤➤ M2M2--M3 middle pitch for density & performance (XM3 middle pitch for density & performance (X--cap)cap)➤➤ M4M4--M6 high pitch (low resistance) for performance (Inductance)M6 high pitch (low resistance) for performance (Inductance)

➤➤ FutureFuture➤➤ Copper Copper -- Less resistance more inductance effectLess resistance more inductance effect➤➤ SOI SOI -- the M1 coupling strangethe M1 coupling strange

0.25 Micron, 5 Layer Technology0.25 Micron, 5 Layer Technology

IEDM 96IEDM 96

M6

M5

M4

M3

M2

M1

0.18 Micron, 6 Layer Technology0.18 Micron, 6 Layer Technology

IEDM 99IEDM 99

5

10

15

20

25

120 130 140 150 160 170 180 190 200LGATE (nm)

Gat

e D

elay

(pse

c)

Vdd = 1.5V

Vdd = 1.3V

Gate Delay .v.s. ScalingGate Delay .v.s. Scaling

IEDM 99IEDM 99

0

20

40

60

80

100

120

0.0 0.5 1.0 1.5 2.0 2.5 3.0Pitch ( µm)

Shee

t Rho

(moh

m/s

q)

Al, 0.25um, ref [6]Al, 0.18um, this workCu, 0.22um, ref [7]

Interconnect Resistance Grows Super LinearlyInterconnect Resistance Grows Super Linearly

IEDM 99IEDM 99

Interconnect Delay Trend

IEDM 95

0

0.5

1

1.5

2

2.5

3

0.35 0.6 0.8 1 1.5Technology Generation (micron)

Rel

ativ

e R

C D

elay

IEDM 99IEDM 99

2020

Interconnect Complicated Design Flow

ArchitectureArchitecture

RTLRTL

LogicLogic

GateGate

LayoutLayout

Over tens of Over tens of iterations!iterations!

Signal Integrity A new design challenge

CrossCapCrossCap

1

2

CrosstalkCrosstalk

Inductance effect emerging

➤➤ An old clock treeAn old clock tree➤➤ FreqFreq domain up to 1Ghzdomain up to 1Ghz➤➤ PVL and PRIMA with order PVL and PRIMA with order

16 find the exact16 find the exact

➤➤ A newerA newer cktckt, a section of , a section of power gridpower grid

➤➤ Has L’sHas L’s➤➤ PVL and PRIMA with 60th PVL and PRIMA with 60th

orderorder➤➤ Frequencies more than 0.6Frequencies more than 0.6

GhzGhz are not coveredare not covered

Frequency (Ghz)

0 0.5 1 1.5 2-3

PRIMAPVL

|H(jw)|

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

|H(jw)|

PRIMA=PVL=EXACT

EXACT

70 72 74 76 78 80-550

-500

-450

-400

Multi-Point PRIMA-34

PRIMA-80

TIM

PVL-80

Some MOR result

Model order reduction

➤➤ We need We need efficient toolsefficient tools to analyze the interconnect to analyze the interconnect dominant circuits (power grids, packages etc.) accurately dominant circuits (power grids, packages etc.) accurately in a reasonable amount of timein a reasonable amount of time

⇒⇒ Promising Promising Model Order ReductionModel Order Reduction (MOR) techniques(MOR) techniquesNonlinear Elements

Linear Elements

Nonlinear Elements

Reduced Model

Power ConsumptionPower Consumption

➤➤ P P ∼∼ C VC V22 f, wheref, where➤➤ C = Capacitance ~ AreaC = Capacitance ~ Area➤➤ V = Supply VoltageV = Supply Voltage➤➤ f = Operation Frequencyf = Operation Frequency

Power TrendPower Trend

Supply Voltage TrendsSupply Voltage Trends

Deal With It!

➤➤ InterconnectInterconnect➤➤ WireWire-- and Repeaterand Repeater-- SizingSizing➤➤ Repeater InsertionRepeater Insertion➤➤ PerformancePerformance--driven noisedriven noise--aware routingaware routing➤➤ New material: Low resistance (Cooper), Low k material New material: Low resistance (Cooper), Low k material

(SiN2) (SiN2)

➤➤ GatesGates➤➤ Gate SizingGate Sizing➤➤ New Circuit Exploration New Circuit Exploration -- Dynamic Circuit, Dual VtDynamic Circuit, Dual Vt

➤➤ ….….

Standby Power TrendStandby Power Trend

Threshold Voltage v.s. Supply VoltageThreshold Voltage v.s. Supply Voltage

Vt v.s. Delay

Dual Vt circuitDual Vt circuit

High High VtVt

Low Low VtVt

Aggressive circuit styles Aggressive circuit styles

Clock delayed and Self-resetting dynamic circuitsClock delayed and Self-resetting dynamic circuits

Process limitations