digital processing applications for de2 card

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1 Digital processing Digital processing applications for DE2 applications for DE2 card card High Speed Digital Systems Lab High Speed Digital Systems Lab Winter 2008/09 Winter 2008/09 Instructor: Mony Orbach Instructor: Mony Orbach Students : Avner Reisz, Students : Avner Reisz, Natty Nizri Natty Nizri 1 semester project

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Digital processing applications for DE2 card. 1 semester project. High Speed Digital Systems Lab Winter 2008/09. Instructor: Mony Orbach Students : Avner Reisz , Natty Nizri. Introduction. The MSS (mixed signal system) from Alex & Rony’s project, combines analog and digital signals. - PowerPoint PPT Presentation

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Page 1: Digital processing applications for DE2 card

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Digital processing Digital processing applications for DE2 cardapplications for DE2 card

High Speed Digital Systems LabHigh Speed Digital Systems Lab

Winter 2008/09Winter 2008/09

Instructor: Mony OrbachInstructor: Mony OrbachStudents : Avner Reisz, Natty Students : Avner Reisz, Natty NizriNizri

1 semester project

Page 2: Digital processing applications for DE2 card

Introduction The MSS (mixed signal system) from Alex &

Rony’s project, combines analog and digital signals.

With the help of Alterra’s DE2, analog signals can be digitally processed after being sampled by the MSS.

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Page 3: Digital processing applications for DE2 card

Introduction This is the case handled:

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TopicsTopicsProject goalProject goal

Signal Signal regulationregulation

OutputsOutputs

Block diagramBlock diagram

Rates & frequenciesRates & frequencies

Time tableTime table

The applicationsThe applications

InputsInputs

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Project goalProject goal

Writing the DE2-MSS interface in VHDL.Writing the DE2-MSS interface in VHDL.

Designing of amplifiers, filters and noise Designing of amplifiers, filters and noise reductions for that interface.reductions for that interface.

Writing the digital processing applications. Writing the digital processing applications.

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Signal regulationSignal regulation

The MSS can get ±1v as input and ±1.4vThe MSS can get ±1v as input and ±1.4vas output. In order to enlarge these ranges, we as output. In order to enlarge these ranges, we put an attenuator at the input and an amplifier at put an attenuator at the input and an amplifier at the output.the output.

In addition, the unipolar output of the MSS is In addition, the unipolar output of the MSS is turned into a bipolar signal.turned into a bipolar signal.(the amplifier kills the 2.5v DC)(the amplifier kills the 2.5v DC)

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InputsInputsDE2

Function generator

MSS

8-bit BUS(100 kHz)

Attenuator+ LPF

1/101/10

50 kHz50 kHz

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OutputsOutputs

8-bit BUS(100 kHz)

DE2

MSS

Scope

Amplifier+LPF

10/1.410/1.4

50 kHz50 kHz

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Block diagramBlock diagram

Functiongenerator Scope

DE2

MSS Amp.att.

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Rates & frequencies: Rates & frequencies: MSSMSS

BW: 20Hz – 50kHz*BW: 20Hz – 50kHz*

Input:Input:± 1v (attenuated from ±10v) ± 1v (attenuated from ±10v)

Output:Output:2.5 ± 1.4v (then amplified to ±10v)2.5 ± 1.4v (then amplified to ±10v)

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Rates & frequencies: Rates & frequencies: DE2DE2

I/O:I/O:8 bit bus 8 bit bus 100kHz100kHz

Cyclone IICyclone II50/27 MHz50/27 MHz

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The Aplications:The Aplications:

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1. Saturation: Cuts to the signal to a max value whenever

crossing it.

2. Time stretch: Stretches the signal in time. (This is actually like freq. reduce)

3. DC: Applies a DC value of choice. (e.g. Vrms or peak of the original signal).

4.4. Division: Divides the signal (letting the user choose the

factor is an option..)

5. Filter.

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Time tableTime table Information gathering Information gathering                        

Characterization Characterization presentation presentation                        

Study sampling & Study sampling & reconstructionreconstruction Input decrease solution Input decrease solution + LPF+ LPF Output normalization + Output normalization + LPFLPF Quartus acquaintanceQuartus acquaintance VHDL reviewVHDL review Simple test application Simple test application (+ test)(+ test) Midterm presentationMidterm presentation                           

Algorithm designAlgorithm design                           

VHDL design (+ test)VHDL design (+ test)                           

WeekWeek 11 22 33 44 55 66 77 88 991100

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