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Digital processing Digital processing applications for DE2 cardapplications for DE2 card

High Speed Digital Systems LabHigh Speed Digital Systems Lab

Winter 2008/09Winter 2008/09

Instructor: Mony OrbachInstructor: Mony OrbachStudents : Avner Reisz, Natty Students : Avner Reisz, Natty NizriNizri

1 semester project

Introduction

The MSS (mixed signal system) from Alex & Rony’s project, combines analog and digital signals.

With the help of Alterra’s DE2 analog signals can be digitally processed after being sampled by the MSS.

Introduction

This is the case handled:

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TopicsTopics

Project goalProject goalInputsInputsOutputsOutputs

Block diagramBlock diagramRates & frequenciesRates & frequencies

Time tableTime table

The applicationsThe applications

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Project goalProject goal

Writing the applications in VHDL for Writing the applications in VHDL for the DE2the DE2

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InputsInputs

DE2

Function generator

MSS

8-bit BUS(100 kHz)

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OutputsOutputs

8-bit BUS(100 kHz)

DE2

MSS

Scope

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Block diagramBlock diagram

Functiongenerator Scope

DE2

MSS

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Rates & frequencies: Rates & frequencies: MSSMSS

Input:Input:± 1v± 1vBW: 20Hz – BW: 20Hz – 20kHz20kHz

Output:Output:2.5 ± 1.4v2.5 ± 1.4v

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Rates & frequencies: Rates & frequencies: DE2DE2

I/O:I/O:8 bit bus 8 bit bus 100kHz100kHz

Cyclone IICyclone II50/27 MHz50/27 MHz

The Aplications:The Aplications:

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1. Saturation: Cuts to the signal to a max

value (of choice) whenever crossing it.

2. Time stretch: Stretches the signal in time (This is actually like freq.

reduce)

The Aplications:The Aplications:

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3. DC: Applies a DC value of choise (e.g. Vrms or peak of the

original

signal).

4. Division: Divides the signal (letting the

user choose the factor is an option..)

5. Filter.

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Time tableTime table Information gathering Information gathering

                       

Characterization Characterization

presentation presentation                        

Study sampling & Study sampling & reconstructionreconstruction Input decrease solutionInput decrease solution Output normalizationOutput normalization Quartus acquaintanceQuartus acquaintance VHDL reviewVHDL review Simple test application (+ Simple test application (+ test)test) Midterm presentationMidterm presentation

                          

Algorithm designAlgorithm design                          

VHDL design (+ test)VHDL design (+ test)                          

WeekWeek 11 22 33 44 55 66 77 88 99 1010 1111 1212 1313 1414