digital fundementals

FloydFloydDigital Fundamentals, 9/eDigital Fundamentals, 9/e

Copyright Copyright 2006 by Pearson Education, Inc.2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

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Digital FundamentalsDigital Fundamentals

CHAPTER 7CHAPTER 7Latches, FlipLatches, Flip--Flops and TimersFlops and Timers




Latches Latches




LatchesLatches

SS--R (SetR (Set--Reset) latchReset) latch Gated SGated S--R latchR latch Gated D latchGated D latch




LatchesLatches

SS--R latchR latch




Figure 7Figure 711 Two versions of SETTwo versions of SET--RESET (SRESET (S--R) latches. Open file F07R) latches. Open file F07--01 and verify the operation of both latches. 01 and verify the operation of both latches.

Thomas L. FloydThomas L. FloydDigital Fundamentals, 9eDigital Fundamentals, 9e


All rights reserved.All rights reserved.







Figure 7Figure 722 NegativeNegative--OR equivalent of the NAND gate latch in Figure 9OR equivalent of the NAND gate latch in Figure 91(b). 1(b).




Figure 7Figure 733 The three modes of basic latch operation (SET, RESEThe three modes of basic latch operation (SET, RESET, noT, no--change) and the invalid condition. change) and the invalid condition.




Figure 73 The three modes of basic latch operation (SET, RESET, no-change) and the invalid condition.





Figure 7Figure 766 The latch used to eliminate switch contact bounce. The latch used to eliminate switch contact bounce.






Figure 7Figure 777 The 74LS279 quad latch. The 74LS279 quad latch.







LatchesLatches

Gated SGated S--R latchR latch




LatchesLatches

Gated D latchGated D latch




Figure 7Figure 71212 The 74LS75 quad gated D latches. The 74LS75 quad gated D latches.







EdgeEdge--Triggered FlipTriggered Flip--Flops Flops




EdgeEdge--Triggered FlipTriggered Flip--FlopsFlops

EdgeEdge--triggered Striggered S--R flipR flip--flopflop EdgeEdge--triggered D fliptriggered D flip--flopflop EdgeEdge--triggered Jtriggered J--K flipK flip--flopflop





EdgeEdge--triggered Striggered S--R flipR flip--flopflop

WaveformsWaveforms





EdgeEdge--triggered triggered SS--R flipR flip--flopflop




Figure 7Figure 71313 EdgeEdge--triggered fliptriggered flip--flop logic symbols (top: positive edgeflop logic symbols (top: positive edge--triggered; bottom: negative edgetriggered; bottom: negative edge--triggered). triggered).







Figure 7Figure 71414 Operation of a positive edgeOperation of a positive edge--triggered Striggered S--R flipR flip--flop. flop.







Figure 7Figure 71717 Edge triggering. Edge triggering.







Figure 7Figure 71818 FlipFlip--flop making a transition from the RESET state to the SET state oflop making a transition from the RESET state to the SET state on the positiven the positive--going edge of the clock pulse. going edge of the clock pulse.







Figure 7Figure 71919 FlipFlip--flop making a transition from the SET state to the RESET state oflop making a transition from the SET state to the RESET state on the positiven the positive--going edge of the clock pulse. going edge of the clock pulse.








EdgeEdge--triggered D fliptriggered D flip--flopflop

WaveformsWaveforms





EdgeEdge--triggered D fliptriggered D flip--flopflop





EdgeEdge--triggered Jtriggered J--K flipK flip--flopflop

WaveformsWaveforms





EdgeEdge--triggered Jtriggered J--K flipK flip--flopflop




Figure 7Figure 72222 A simplified logic diagram for a positive edgeA simplified logic diagram for a positive edge--triggered Jtriggered J--K flipK flip--flop. flop.







Figure 7Figure 72323 Transitions illustrating the toggle operation when Transitions illustrating the toggle operation when JJ = 1 and = 1 and KK = 1. = 1.







Figure 7Figure 72626 Logic symbol for a JLogic symbol for a J--K flipK flip--flop with activeflop with active--LOW preset and clear inputs. LOW preset and clear inputs.







Figure 7Figure 72727 Logic diagram for a basic JLogic diagram for a basic J--K flipK flip--flop with activeflop with active--LOW preset and clear inputs. LOW preset and clear inputs.







FlipFlip--Flop Operating Characteristics Flop Operating Characteristics




FlipFlip--Flop Operating CharacteristicsFlop Operating Characteristics

Propagation delay timesPropagation delay times SetSet--up timeup time Hold timeHold time Maximum clock frequencyMaximum clock frequency Pulse widthsPulse widths Power dissipationPower dissipation




Figure 7Figure 73232 Propagation delays, clock to output. Propagation delays, clock to output.







Figure 7Figure 73333 Propagation delays, preset input to output and clear inputPropagation delays, preset input to output and clear input to output. to output.







Figure 7Figure 73434 SetSet--up time (up time (ttss). The logic level must be present on the ). The logic level must be present on the DD input for a time equal to or greater than input for a time equal to or greater than ttss before the triggering edge of the clockbefore the triggering edge of the clock pulse for reliable data pulse for reliable data entry. entry.







Figure 7Figure 73535 Hold time (Hold time (tthh). The logic level must remain on the D input for a time equal t). The logic level must remain on the D input for a time equal to or greater than o or greater than tthh after the triggering edge of the clock pulseafter the triggering edge of the clock pulse for reliable data entry. for reliable data entry.







FlipFlip--Flop Applications Flop Applications




FlipFlip--Flop ApplicationsFlop Applications

Parallel data storageParallel data storage Frequency divisionFrequency division CountingCounting





Parallel data storageParallel data storage





Frequency divisionFrequency division





CountingCounting




OneOne--Shots Shots




OneOne--ShotsShots

NonretriggerableNonretriggerable oneone--shotshot RegriggerableRegriggerable oneone--shotshot




Figure 7Figure 74444 A simple oneA simple one--shot circuit. shot circuit.







OneOne--ShotsShots

NonretriggerableNonretriggerable oneone--shotshot




OneOne--ShotsShots

RegriggerableRegriggerable oneone--shotshot




The 555 Timer The 555 Timer




The 555 TimerThe 555 Timer

MonostableMonostable (one(one--shot) operationshot) operation AstableAstable operationoperation





MonostableMonostable (one(one--shot) operationshot) operation

ttww=1.1R=1.1R11CC11




Figure 7Figure 75555 OneOne--shot operation of the 555 timer. shot operation of the 555 timer.








AstableAstable operationoperation




Figure 7Figure 75757 Operation of the 555 timer in the astable mode. Operation of the 555 timer in the astable mode.







Figure 7Figure 75959 The addition of diode The addition of diode DD11 allows the duty cycle of the output to be adjusted to less thanallows the duty cycle of the output to be adjusted to less than 50 percent by making 50 percent by making RR11 < < RR22. .




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