digital design with verilog: course notes for first edition

8/8/2019 Digital Design with Verilog: Course Notes for First Edition

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2014-01-11 Notes for Digital VLSI Design with Verilog 1

Course Notes and Errata

for the 2008 edition of

Digital VLSI Design with Verilog

A Silicon Valley Technical InstituteAdvanced Course

byJohn Michael Williams

2014-01-11

Copright 20!"# $ohn %ichael &illia's(

Licensed free to Silicon Valle )echnical Institute for training*course use( All other

rights reserved(

[email protected]

NOTE: The new 2nd Edition is available as of June 2014

Course notes for it are downloadable at Scribd.


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)a+le of Contents

Introduction.............................................................................................................................1Course Description....................................................................................................................1

rere!uisites.................................................................................................................."

Class #rgani$ation and %aterials.............................................................................."

roprietar& Infor'ation and Licensing Li'itations................................................()e*t+oo,......................................................................................................................................

)e*t+oo, rrata /edition of 200............................................................................................

Supple'entar& eferences.....................................................................................................12

Supple'entar& )e*t+oo,s.........................................................................................1"

Interacti3e Language )utorial..................................................................................1"

eco''ended ree Verilog Si'ulator.....................................................................1"

VCS Si'ulator Su''ar& /distri+uted separatel& ............................................................. 1"

DC S&nthesi$er La+ 1 Su''ar& /distri+uted separatel& .................................................1"

DC S&nthesi$er Co''and e'inder /distri+uted separatel& .........................................1"

Course 5rading olic&.............................................................................................................14

5etting ead& for Class 6ttendance.....................................................................................1(

7ee, 1 Class 1......................................................................................................................1Introduction to this Course....................................................................................................18

7ee, 1 Class 2......................................................................................................................1ara'eter and Con3ersion La+ "..........................................................................................19

Non+loc,ing Control La+ 4.....................................................................................................21

7ee, 2 Class 1......................................................................................................................2"Si'ple Scan La+ (................................................................................................................ ...2"

7ee, 2 Class 2......................................................................................................................28LL Cloc, La+ ....................................................................................................................... 2

7ee, " Class 1......................................................................................................................"0%e'or& La+ 8..........................................................................................................................."1

7ee, " Class 2......................................................................................................................"2Counter La+ ...........................................................................................................................""

7ee, 4 Class 1......................................................................................................................"(Strength and Contention La+ 9............................................................................................."

LL :eha3ioral Loc,-In La+ 10............................................................................................."8

7ee, 4 Class 2......................................................................................................................"I# La+ 11............................................................................................................................. "9

7ee, ( Class 1......................................................................................................................42Scheduling La+ 12................................................................................................................ ...4(

7ee, ( Class 2......................................................................................................................4Netlist La+ 1"........................................................................................................................... 48

7ee, Class 1......................................................................................................................4Concurrenc& La+ 14.................................................................................................................49

7ee, Class 2......................................................................................................................(05enerate La+ 1(.......................................................................................................................(2

7ee, 8 Class 1......................................................................................................................(4Serial-arallel La+ 1.............................................................................................................(4

7ee, 8 Class 2......................................................................................................................(Co'ponent La+ 18...................................................................................................................(8

7ee, Class 1......................................................................................................................2Connection La+ 1..................................................................................................................."


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2014-01-11 Notes for Digital VLSI Design with Verilog "

;ierarch& La+ 19..................................................................................................................... 4

7ee, Class 2......................................................................................................................)i'ing La+ 20.......................................................................................................................... 8

7ee, 9 Class 1......................................................................................................................)i'ing Chec, La+ 21..............................................................................................................9

7ee, 9 Class 2......................................................................................................................81Se!uential Deseriali$er I La+ 22..........................................................................................82

7ee, 10 Class 1....................................................................................................................88Concurrent Deseriali$er II La+ 2"........................................................................................88

7ee, 10 Class 2...................................................................................................................."SerDes La+ 24.......................................................................................................................... "

7ee, 11 Class 1....................................................................................................................9Scan and :IS) La+ 2(.............................................................................................................90

)ested SerDes La+ 2..............................................................................................................92

7ee, 11 Class 2....................................................................................................................9SD La+ 28............................................................................................................................... 98

7ee, 12 Class 1....................................................................................................................9Scope of the inal *a'.........................................................................................................99Continued La+ 7or, /La+ 2" or later..................................................................................99

7ee, 12 Class 2..................................................................................................................10024.1. S&ste'Verilog


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Introduction

)his Course Note :oo, is pro3ided as a supple'ent to the re!uired )e*t+oo,. )his

Note :oo, descri+es course-related 'atters? su''ari$es the da&-+&-da& lectures and

la+s? and includes tool-related updates. 6ll D6 tools change rapidl&? so an& te*t+oo,?including ours? will +e so'ewhat o+solescent as soon as it has +een pu+lished.

)hese Notes soon will +e incorporated in a future edition of the )e*t+oo,.

6t present? all references in the )e*t+oo, and this Note :oo, are to I Std 1"4-

200( for 3erilog and not to the later SystemVerilogStd docu'ent -- unless otherwise

stated. *cept /a for inclusion of e*isting Cor C++code? or /b for co'ple* assertion

co'position? SystemVerilogand 3erilog 200( differ 3er& little? as e*plained in detail in

the final lecture +elow.

)he )e,t+oo- soon will +e availa+le in print as the second edition of

Digital VLSI Design with Verilog( So'e changes in the second editionare.

%an& 'inor t&pographical errors ha3e +een corrected? as ha3e +een se3eral

other errors newl& disco3ered in the te*t and figures.

%aBor upgrades in the second edition areA

%odified Da& 1 presentation 'a,ing it 'ore useful to 3erilog +eginners

Do$ens of new figures

*pansion or clarification of e*planations on al'ost e3er& page

>pgrade of the si'ulation figures to +e in color

New co3erage of the features of SystemVerilogand VerilogA/MS

6 new su''ar& introduction to each chapter and la+ e*ercise

I Stds references include S&ste'Verilog as well as 3erilog

6 new? optional la+ chec,list for recording learning progress

6n& corrections or updates of the second edition will +e posted on Scribd.

)here will +e no 'ore updates to Scribdconcerning the first edition.

Course Description)his hands-on course presents the design of digital integrated circuits? using the

3erilog digital design language as descri+ed in I Standard 1"4 /2001 and after.

:& a +alanced 'i*ture of lectures and la+s? the students are introduced to language

constructs in a progressi3el& 'ore co'ple* proBect en3iron'ent. During the course?

students are fa'iliari$ed with the use of the S&nops&sDesign Compilerto s&nthesi$e

gate-le3el netlists fro' +eha3ioral? )L? and structural Verilog code. )he s&nthesis

constraints 'ost useful for area and speed opti'i$ation are e'phasi$ed. 6l'ost all the


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class proBect wor, is done in the s&nthesi$a+le su+set of the language logic si'ulation is

treated as a 3erification 'ethod in preparation for s&nthesis.

)he S&nops&s VCSsi'ulator? or optionall&


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Course )opic List /partial.

Lecture and La+. %odules and hierarch& :loc,ingnon+loc,ing assign'ent

Co'+inational logic Se!uential logic :eha3ioral 'odelling )L 'odelling

5ate-le3el 'odelling ;ardware ti'ing and dela&s Verilog para'eters :asic

s&ste' tas,s )i'ing chec,s 5enerate state'ent Si'ulation e3ent schedulingace conditions S&nthesi$er operation S&nthesi$a+le constructs Netlist

opti'i$ation S&nthesis control directi3es Verilog influence on opti'i$ation >se

of SD files )est structures rror correction +asics.

1ands*on ro3ects. Shift and scan registers counters 'e'or& and I#

'odels digital phase-loc,ed loop /LL serial-parallel /and vv con3erter

seriali$er-deseriali$er /serdes pri'iti3e gates switch-le3el design netlist +ac,-

annotation.

rere4uisites

6 +achelor@s degree in electrical engineering or the e!ui3alent? with digital designe*perience. a'iliarit& with progra''ing in a 'odern language such as C.

Class 5rgani6ation and %aterials

)he course is intensi3el& hands-on. )here will +e 12 wee,s of instruction? two "-hour

lecture 'eetings per wee,? for a total of 82 hours in class? plus another 4 hours per wee,

of 'andator& la+. )he instructor will +e present for a 'ini'u' of 2 of the 4 hours per

wee, of 'andator& la+. 6ttendance will +e ta,en on all these da&s? which total 'ore

than 110 hours o3er the twel3e wee,s of the course.

In addition? the la+ co'puters will +e 'ade a3aila+le for additional ti'e? as re!uested

+& the attendee. %an& la+ e*ercises will +e held during lecture 'eeting ti'e others will+e scheduled or continued outside class in the dedicated la+ ti'e.

6 +rief !ui$ will +e held e3er& lecture da& e*cept during the first and last wee,s and?

there will +e a final e*a'. ;o'ewor, will +e assigned in the for' of )e*t+oo, and

outside readings. During the course? students will +e allowed as 'uch additional access

to training co'puters as the& re!uire for course stud&? ho'ewor,? or la+s.

e!uired )e*t+oo,

)he )e*t+oo, for this course isDigital V!S" Design #ith Verilog/see +elow for

citation. )he )e*t+oo, contains e*planations? ho'ewor, readings? and all the la+

instructions. )he CD which ships with the hardcop& edition of the )e*t+oo, contains the

original 3ersions of the answers which are pro3ided in the Lab$$wor,ing directories.

It is notreco''ended that &ou purchase the D edition of the )e*t+oo, for this

course &ou will want a hard cop& an&wa&? to ta,e 'arginal notes and? 3iewing it on-

screen will 'a,e &our la+ wor, 'uch 'ore difficult than if &ou had the capacit& to page

through a +oo, independent of what &our co'puter was doing. If &ou did get the D

edition? &ou could read it on &our own laptop co'puter during lecture or la+? +ut &ou will

not +e per'itted access to an& co'puter during the /open-+oo, final e*a'? so notes in

&our co'puter will +e una3aila+le.


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)e*t+oo, CD-#%

age ** /twent& of the )e*t+oo, +riefl& suggests how to use the contents of the CD-

#% which acco'panies it. 6s a suggestion? a good wor,ing en3iron'ent in which to

organi$e the contents of the CD-#% would +e set up as shown in the following figureA

If &ou create the DCand VCSdirectories as suggested? &ou will ha3e used e3er&thing in

the CD-#% miscdirector&? so &ou will not need a miscdirector& in &our wor,ing

en3iron'ent.

)he 'aBorit& of the e*ercise answer su+directories which depend upon the

tcbn90ghp_v2001.vsi'ulation li+rar& contain a $ero-length cop& of that .vfile. )his

was done to reduce the space occupied +& the answer CD-#%. 7hene3er &ou

encounter a $ero-length file na'ed tcbn90ghp_v2001.v? &ou should replace it with a

full-length 3ersion fro' &our VCS director& /see a+o3e or fro' the miscdata director&

on &our CD-#%.

)he _vimrcfile in the CD-#% miscdirector& is a con3enient startup file for the vim

te*t editor? which is the reco''ended te*t editor for 3erilog. )he _vimrcfile should +e

rena'ed to .vimrcand copied to &our ho'e director& /E~E? if running Linu* or >ni*. If

&ou are running 7indows? _vimrcshould +e copied to the startup director& which &ou

ha3e configured for vim.

Course Note :oo,

)he Course Note :oo, is a printout of these Notes pro3ided to each attendee it 'a& +e

used as an aid to the ta,ing of notes during lecture. :ring &our Course Note :oo, and

)e*t+oo, to e3er& class and la+. 6lwa&s read the la+ instructions in the )e*t+oo, at

least once +efore the da& on which the la+ is scheduled. )he Note :oo, will +e updated

as necessar& during the course to acco''odate additional lecture 'aterial and toolsoftware i'pro3e'ents /'ainl& in the area of s&nthesis.

Class 6ttendance

Co''it'ent to attendance at all lectures and la+s is ad3isedA )his course is not an

eas& one an& 'issed 'andator& session should +e 'ade up as soon as possi+le. )he

school pro3ides for as 'an& as three 'a,eup lecture sessions during the course and? a

total of two 'issed sessions /lecture or la+? not 'ade up? is allowed. 6ttendance not

'eeting these criteria 'eans that a certificate will not +e granted.


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2014-01-11 Notes for Digital VLSI Design with Verilog (

roprietar Infor'ation and Licensing Li'itations)his Course Note :oo, includes no proprietar& infor'ation +e&ond that which is

cop&righted +& the present author. ;owe3er? during the course? students will +e e*posed

to features of the S&nops&s and %entor 5raphics tools which 'a& +e considered

proprietar& in other wa&s. roprietar& infor'ation generall& 'a& include an&thing

pro3ided to users directl& +& the 'anufacturer. In addition? licensing pro3isions 'a&li'it repu+lication of specific perfor'ance details. )o a3oid including such infor'ation

in the Course Note :oo,? and to 'a,e the Course Note :oo, as porta+le a'ong different

3endor tools as possi+le? the following approach has +een adoptedA

VCSA 6l'ost all options con3enient to run the VCS si'ulator are entered 'anuall&

according to a separatel&-distri+uted sheet? or are set up in a shell co''and alias. )he

la+ e*ercise answers and e*ercises generall& are co'pati+le withAldec@s or an& other

3endor@s si'ulator. ;owe3er? the later la+ e*ercises will +e too +ig to +e run on the

li'ited-capacit& de'o 3ersion of Silos pro3ided with the supple'entar& te*t+oo,s na'ed

in the eferences.

Design CompilerA Instruction on the operation of the DC s&nthesi$er will +e

presented al'ost entirel& in la+ a handout sheet will +e pro3ided with a su''ar& of

in3ocation options and s&nthesis constraints. Students 'a& use these constraints in

their la+ wor, as will +e e*plained +& la+ instructions during the course.

QuestaSimA )his %entor 5raphics tool? for'erl& na'ed ModelSim? 'a& +e a3aila+le

in the future upon student re!uest if so? infor'ation on its operation will +e pro3ided on

a separate handout sheet.

u+lishing of operational perfor'ance details of VCS? Design Co'piler? or FuestaSi'

'a& re!uire written per'ission fro' S&nops&s or %entor? and students are ad3ised not

to cop&? duplicate? post or pu+lish an& of their wor, showing specific tool properties

without 3erif&ing first with the 'anufacturer that trade secrets and other proprietar&

infor'ation ha3e +een re'o3ed. )his is a licensing issue unrelated to cop&right? fair

use? or patent ownership.

)he sa'e applies to the TSMC library filesa3aila+le for 3iewing +& attendees +ut

not distri+uted. )hese front-end li+raries are designed for s&nthesis? floorplanning? and

ti'ing 3erification and 'a& contain trade secrets of )S%C. Do not 'a,e copies of

an&thing fro' the )S%C li+raries? including )S%C docu'entation? without special

per'ission fro' )S%C and S&nops&s.

)he 3erilog si'ulation 'odels in the files? !ibrary%ame_v2001.v? are cop&righted +ut

not otherwise proprietar& and are a3aila+le for cop&ing? stud&? or 'odification in the

conte*t of this course. )hese 'odels are si'ple +ut so'ewhat inaccurate the& areintended for training use? onl&? and the& nevershould +e used for design wor,.

Verilog netlists produced +& the s&nthesi$er are not proprietar&? although the !iberty

li+rar& 'odels co'piled for use +& the s&nthesi$er are proprietar& and owned +&

S&nops&s. 3aluations of netlist !ualit& in association with 'ention of S&nops&s or

Design Co'piler 'a& +e considered proprietar& and should not +e pu+lished or

distri+uted without special per'ission. )he ti'ing in +ac,-annotated netlists 'a& +e

considered proprietar& +& S&nops&s or )S%C.

:otto' lineA >se what &ou ,now and understand? not what &ou cop&.


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2014-01-11 Notes for Digital VLSI Design with Verilog

Tetboo!7illia's? G. %. Digital V!S" Design #ith Verilog. Springer? 200. )his is the re!uired

te*t+oo, and la+ e*ercise +oo, for the course. IS:NA 98-1-4020-44(-4.

Tetboo! "rrata#edition of $%%&'

>pdates and additional e*planations are a'ong the wee,l& chapters +elow. )he

,nown 'inor errors are as follows /a few length& corrections are with the wee,l& notesA

1. p. i*? refaceA Change EownerE to Eco-ownerE /the other co-owner of the school is He3in

Lash,ari.

2. p. ** in the IntroductionA In 2.1 Contents of the CD-#%? the last sentence of the

third paragraph 'isspells the na'e of the %entor si'ulator? which should +e

QuestaSim.

". p. **i? in eferencesA Delete the entire first reference /E6non&'ousEA 6ccellera no

longer has a S&ste'Verilog draft standard posted it is now +& I? as descri+ed in

the Supplementary &e'erences+elow.4. p. ? in La+ 1A )he caption of igure 1.8 'isspells the na'e of the %entor si'ulator?

which should +e QuestaSim.

(. pp. 9 - 10 in La+ 1A )he figure la+elled 1.9 is of the hierarchical /not ungrouped

netlist which was s&nthesi$ed earlier in the la+ there is no design_visionsche'atic

for the ungrouped /flattened netlist? so the last paragraph on p. 9 is not correct.

. p. 1"A In the paragraph +eginning EIt usuall& is . . .E? the literal e*pression in !uotes

should +e E1'b0E? with the single-!uote character /' in a fi*ed-width font such as

Courier.

8. p. 2A In the second sentence of the third paragraph? the +olded tic, s&'+ol should +e

in a fi*ed-width font such as Courier? thusA E. . . deli'iting tic, s&'+ol /'? . . .E.. p. 29? La+ "? Step 1A )he 3erilog 'odule na'e on the 2nd line includes a space it

should +e? ParamCounterop.v.

9. p. "0? La+ "? Step 26A 6fter the second declaration? there is an e*tra E! #E. Delete

this? lea3ing E...$ % &( # % ) * $(...E.

10. p. 40A In the second D latch code e*a'ple? in the else +ranch? Eena1_nE should +e

ena_n.

11. p. 44A In Section ".1.2? the last +ullet should +e?

+egin with a letter /alpha? underscore /@_@? or +ac,slash /@+@.

12. p. 4(A )he section header was wrapped +& 'ista,e. It should +e? E7(!( 9ac-us*Naur :or'at /9N:E.

1". p. 4A In the paragraph a+o3e Latches and %u,es? the assign'ent in the second

fro' the last sentence includes a spurious space it should read? E,reg % )-$E.

14. p. 4A In the final paragraph? the as&nchronous control na'es are gar+led and should

+e the sa'e as in the preceding code e*a'ple. )he +eginning of the first sentence

should read? EIn this 'odel? priorit& is gi3en to Preset_no3er Cear_n...E.

1(. p. ("A Change the second sentence in the first paragraph after igure ". to read?

E. . .? we shall install the 'u*es so that the& switch the flip-flops out of the designE.


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1. p. A In the second paragraph? 4th line? the units are wrong? and there is a period

/@.@ 'issing. )he line should read? E...of a+out "(0 %:s. 6 parallel ...E.

18. p. 80A Change the paragraph +elow igure 4. to read? E. . . the hori$ontal grids in

ig. 4. are spaced 3erticall& at a+out "00 'V di3isionsE.

1. p. 81A In the second paragraph? second line? there is an e*tra EofE the correct wording

should +e? E. . . we can create a netlist? . . .E.

19. p. 8"A )he first beginin the code e*a'ple is capitali$ed /%icrosoft 7ord +ug it

should +e EbeginE.

20. p. 8(A In the first paragraph in Step "? the reference should +e to figure 4.10? not

Efigure ".10E.

21. p. 8A In the last line of the code e*a'ple? the E2'h00E should +e 2'b00.

22. p. 88A In the second sentence following the code e*a'ple? for consistenc& with the

code e*a'ple? the second sentence should +egin? ESo? E/i$it'b1E would not +e a legal

incre'ent e*pression.E

2". p. (A In the paragraph +elow the second code e*a'ple? the first few words should +e?E)o declare a 'e'or&? ...E.

24. p. A In the first sentence? it should +e? E... 'ore than three ...E.

2(. p. A )he last +ullet on the page no longer is correct. It should +e changed to?

%an& si'ulators such as the Silosde'o 3ersion can not displa& a 'e'or&

storage wa3efor' new VCS? QuestaSim? andAldeccan.

2. p. 90A In the last paragraph? the end of the first sentence should +e changed to? E... for

p1 and the rest of the +its.E.

28. p. 94A )wo of the fra'ing-error e*a'ples are gar+led. )here are ten +its per fra'e?

so the correct fra'ing should appear this wa&A

0'b_$#P_$#P_$#P_$#P

)he &$fra'ing error lagging should appear this wa&A

0'b_#P$_#P$_#P$_#P$

)he &$fra'ing error leading is correct as printed.

2. p. 9(A In the second sentence of Step 2? the 'odule na'e should not ha3e spacesA

Eem1342E.

29. p. 9A )he first line on tip should read? E. . . gi3en in the preceding . . .E.

"0. p. 9A )he ig. (.4 la+el@s 'odule na'e should not ha3e spacesA Eig. (.4 )he

em13426% sche'aticE.

"1. p. 98A In the 5dispa6of the code e*a'ple? the for'at-specifier !uote characters

should +e dou+le-!uotes? thusA 5dispa678...8! 5time! . . .(. #f course?

E. . .E represents a for'at specifier.

"2. p. 101A igure .1 caption is 'issing a period /@.@ after the word E3aluesE.

"". p. 11"A In section 8.1.1? "rd paragraph? there is a period instead of a co''aA It

should read? E... assign'ent of @:@? there is ...E.

"4. p. 121A In the S&'+ol)&pe list at the top of the page? the last s&'+ol on the left is

re3ersedA It should +e? E;;; shift /arithE.


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2014-01-11 Notes for Digital VLSI Design with Verilog

"(. p. 141A In the code e*a'ple? the co''ented offset nu'+ers and the 4-+it pac,et

should line up 3erticall& this wa&A 0 0 40 20 10 0

42109 ?=>4210 9?=>42 109?=> 42109?= >42109 ?=>4210

='b01100001_00011000_01100010_00010000_01111001_00001000_01111010_00000000(

". p. 149A )he last paragraph +efore Section .1." refers to a file [email protected] inthe La+11 director&. )his file can +e found instead in the discussion of La+11 +elow.

"8. p. 1(9A )he normaone of the fi3e si'ple states at the top of the page should refer to

a 4-state I#? not a E4-registerE I#. Si'ilarl&? the ig. .1" te*t should descri+e a

I# with fi3e or 'ore storage states.

". p. 180A )he figure caption for ig. 9.1 should call the cloc, C3? not EC1AE.

"9. p. 18"A )he figure caption for ig. 9.2 has two periods after the word Queue/instead

of one.

40. p. 18A In Case 2? step 9? the case? of course? should +e Case 2? not ECase 1E.

41. p. 189A In the la+ Step 1? left code e*a'ple? the second aBa6s+loc, has two @5@

t&poesA It should +e? EaBa6s7a b ;% a(E.

42. p. 190A In the first paragraph after ig. 10.4? the second sentence should +e? E7ith #

% 1? if ngoes to 0? Eand En+oth go to 1 if nthen returns to 1? there is a latched

3alue? +ut it is indeter'inate? +ecause if either Eor Enshifts to 0sooner than the

other? it can cla'p or re3erse the other to its original 13alue.E

4". p. 192A 6t ti'e 8 in the truth-ta+le? the FD3alue should +e 0? not E1E.

44. p. 20"A In the ne*t-to-last te*t paragraph? the third sentence should +egin with? EIf

one input +it ne3er toggles? then each change of Chec3n$uswill spawn a new Gor3&

Hoin+loc, e3ent in 'e'or&? ...E.

6lso? the last te*t paragraph should +e preceded +& this new oneAE)he aBa6s-+loc, e*a'ple a+o3e also suffers fro' this pro+le'? +ut to a lesser

e*tent.E

4(. p. 20(A Delete the words? E? for te'porar& use? e3enE? in the first sentence of the

second paragraph on this page. See the Supple'entar& Note on this section for an

e*planation and a rewrite of the last paragraph on this page.

4. p. 20A )he +eginning of the first sentence in the first te*t paragraph should +e

changed to sa&? EVaria+les declared in a tas3? li,e those in an& other na'ed +loc,? are

static and hold their 'ost recent 3alue . . .E.

6lso? the third sentence in the first paragraph should +egin? E)his last holds . . .E.

6lso on this page? the last two sentences of the third te*t paragraph should read this

wa&A

E)as, local 3aria+les are staticreg-t&pe 3aria+les shared a'ong all calls of a gi3en

tas, so? of course? the& share the sa'e declaration. So'eti'es this sharing 'a& +e

desira+le? +ecause it allows different running instances of the tas, to co''unicate

with each other.E

48. p. 224A )he first code e*a'ple contains an incorrect aBa6s+loc,. It should +e the

sa'e as the others? na'el&?

aBa6s7)bus :1 temp ;% -)bus(


12/114


4. p. 22(A In the first line of the La+ rocedure? EgenerateE should not end with a space

+efore E.E.

49. p. 22(A )he second sentence in Step 4 should read? E:elow the instructions in Step 4

:? is a slightl& . . .E.

(0. p. 22A )he La+ 1(? Step 4C instruction following igure 12.9 should +e changedA Do

add a ""rd +it for parit& howe3er? lea3e the ""rd +it unused for now.

(1. p. 22A )he figure caption to ig. 12.11 should 'ention that the wa3efor's are for a

s&nthesi$ed netlist si'ulation? not for a si'ulation of the 3erilog source.

(2. p. 2"2A In the 'iddle of the second paragraph? there is an e*tra EorEA Change it to?

E... or? instead of such a flag? we 'ight pro3ide ...E.

(". p. 2(0A )he first sentence of the second paragraph in %5S SwitchesJis

gra''aticall& incorrect? +eginning with the se'icolon. It should +e changed to? . . .

'ore negati3e? and an N-channel transistor /nmos conducts . . .J.

(4. p. 2(8A )he sche'atic in ig. 14. shows a fourth triregconnecting the output? +ut

the wa3efor's in igs. 14. and 14.10 are for a design in which that trireghas +een

o'itted. )hese figures are corrected in the Supple'entar& Notes +elow.

((. p. 2(9A )he second parametere*a'ple in 1(.1.1 contains an unnecessar& E&E.

(. p. 28(A In the first code e*a'ple? delete the iG7@astCoc3%%1'b1as redundant.

(8. p. 2A In the first paragraph? second sentence in 1.2.4? specparamis 'isspelled.

(. p. 2A )he first paragraph after the last code e*a'ple on this page should read? EIn

the first state'ent a+o3e? assu'e that C3cloc,s in Dto I1 ...E.

(9. p. 29A In )i'ing La+ 20? Lab (rocedure? 1st paragraph? all occurrences of

ESpectE should +e in Courier /fi*ed-width font.

0. p. 291A or clarit&? the first sentence in Step ": should +e rephrased to? EChange the

dela& in the speciG6+loc, to . . .E. 6lso? in the second paragraph of Step ":? delete? E.

. . and? in a change fro' ? the longest dela& is used.E

1. p. 29A In 18.1."."? in the e*planation of 5recover6? the 'iddle of the first sentence

should +e? E... control? such as a set or clear? to effecti3e ...E. 6lso? the last sentence in

the 5setuphoddiscussion should +e? ESee the e*planation in the section +elow on

negati3e ti'e li'its.E

2. p. 299A igure 18.1 is incorrect in regard to 5remova it and the e*planation of

5removashould +e corrected as in the Supple'entar& Note +elow. )he second

sentence in the 5removae*planation? continued onto this page? should sa&? E... how

long after that edge does an as&nchronous control ha3e to re'o3e itself in order for the

cloc, edge to +e ignoredKE

In 18.1."."? the last sentence on 5recremshould +e? ESee the discussion +elow on

negati3e ti'e li'its.E


13/114


(. p. "08A )he "rd paragraph is Step should sa&? E6dd a speciG6+loc, after the

modueheader declaration in D@@C? setting . . ..E

. p. "12A In the caption to ig. 1.1? the final sentence should +e changed to? ENone of

the PLL? @@J? and DesDecoderwill s&nthesi$e correctl&? +ut all will si'ulate

usa+l&.E

8. p. "18A In ig. 1.8? the Coc3nto the E(E two-+it counter should not +e la+elledE/dela&edE. )he paragraph +efore this figure should +e ignored.

. p. "2"A 6t the +otto' of the page? the third editting instruction should +eA

ena'e the test+ench 'odule to PLLopst.v.

9. p. "28A In the paragraph +eginning? Erepare to set . . .E? change the last sentence to?

E6ssign a default 3alue of ( /for 2( "2 words.E

80. p. ""0A In the second code e*a'ple? the last line of the port 'ap has an incorrect

underscore. It should +e? E! .Kmpt67@@JKmpt6E.

81. p. "42A In ig. 19."? the input port should +e na'ed C3? not the EC,7E which is

shown in a Supple'entar& Note for that page.82. pp. "(1-"(2A or i'pro3ed reada+ilit& in +oth the incrMeadand incrritetas3s?

the first esein each of these should ha3e e*pressions re3ersed to EiG

7Mead)r%%JdMead)rE and EiG 7rite)r%%Jdrite)rE.

8". p. "(A In Step 9? first paragraph after the first code e*a'ple? change the second

sentence to read? EStart +& re'o3ing the SerVaidgate . . ..E.

84. p. "(A )he 4th +ulletted ite' should end with a period @.@.

8(. p. "1 ffA )hroughout Chapter 20 /Wee) *, Class - and La+ 2"? EserdesE should +e

spelled ESerDesE? and Edeseriali$erE should +e EDeseriali$erE? when referring

specificall& to the class proBect design.

8. p. "8A In the 'iddle of the third paragraph? the reference to a Ecell arra&E should +e

Ecell 3ectorE? for consistenc& with 3erilog ter'inolog&.

88. p. ""A In La+ 2(? Step 2? the final words in the 1st paragraph should +e separatedA

E... our larger SerDesdesign.E

8. p. "99A In the last line on this page? there is an e*tra +lan, +efore the co''a

following EDeseriaiNerE.

89. p. 401A )he ELoose 5litch Sin,s ChipsE pun should +e in a 5othic t&peface? such as

7indows MariageDA

0. p. 402A In Step 6? second paragraph? the scan-insertion co''ands are in

Lab2>_)ns


14/114


4. p. 41(A In the +ulletted list of o'itted topics? Edesign_visionE has +een split into

two words.

(. p. 41A In the s&ste' tas, and function ta+ulation? 5readmemband 5readmemh

should not +e +oldface the& were 'entioned +ut ne3er e*ercised.

. p. 428A In the +ulletted S&ste'Verilog feature list? the Qtimescaeshould +e +ac,-

!uoted in fi*ed-width font? not single-!uoted? thusA

timeunitand timeprecisiondeclarations instead of Qtimescae.


15/114


Supplementary )eferences

NoteA 6cti3e-;DL? Design Co'piler? Design Vision? DV? ;SIC? Li+ert&? %odelSi'?

NanoSi'? FuestaSi'? Silos? VCS? and Verilog /capitali$ed are trade'ar,s of their respecti3e

owners.

6non&'ous. I Std 100-2012A Standard 'or SystemVerilog. Verilog is a proper

su+set of S&ste'Verilog and ceases to +e an independent standard with the Std

1"4-200( edition. 6fter 2010? all updates to the L% for 3erilog ha3e +een in

I Std 100? onl&. ;appil&? this 'eans little further change in 3erilogper se.

)he co'plete S&ste'Verilog 'anual currentl& /201"-0 is a3aila+le free for

personal users at httpRni3ersit& of )ennessee /See erratu' at

httpR


16/114

2014-01-11 Notes for Digital VLSI Design with Verilog 1"

7ood? :. E:ac,plane tutorialA apidI#? CIe? and thernetE. DS5 Designline? Ganuar&

14? 2009 issue. osted at httpR


17/114


Course ,rading (olicy

Co'pletion of the course with passing score of ( or a+o3e 'eans award of a

Certificate of 6chie3e'ent otherwise? a Certificate of 6ttendance 'a& +e awarded if no

'ore than 2 of the " scheduled 'eetings were 'issed. )he score is a weighted su' of

!ui$ score plus final e*a' score? with !ui$ weighting as +elow.

Qui**es

)here will +e a !ui$ e3er& scheduled lecture da&? e*cept during the first and last wee,s

of the course. )he total of 20 !ui$$es pri'aril& are 'eant to +e instructional.

5enerall&? !ui$$es will include 'aterial presented in the current or 'ost recent la+ or

lecture.

ach !ui$ will +e +rief? a+out 1( 'inutes? and will count 10 points? for a total of 200

points o3er the whole course. Fui$$es are teaching as well as testing instru'ents? so

poor perfor'ance on !ui$$es need not 'ean 3er& 'uch for an enrollee@s final status.

No 'a,eup will +e allowed for an& 'issed !ui$.

=ui6 weighting rule. ound the !ui$ a3erage percent up to the ne*t 10 then? for

e3er& 10 a+o3e (0? or an& !ui$ 'issed? add 1 to the +aseline ( weight of the

!ui$$es.

*a'plesA

1. 6n enrollee ta,es e3er& !ui$ and a3erages 9(A 9( &&T100. )he !ui$$es

therefore e!ual ( O ( * 1 10 of the total course score. )he final e*a'

contri+utes 90.

2. 3er& !ui$ is 'issedA 0 &&T0. )he 0 !ui$ a3erage will +e weighted as ( O 20* 1 2( of the total course score. )he final e*a' contri+utes 8(.

". 3er& !ui$ is ta,en and the !ui$ a3erage is "4A "4 &&T40. )he "4 !ui$

a3erage then contri+utes ( of the total course score.

4. 1 !ui$ is 'issed and the !ui$ a3erage is (A ( &&T80. )hen? the ( counts

as ( O 2 * 1 O 1 * 1 of the total course score.

-inal "am

)he final e*a' will +e a two-hour? open-+oo, co'prehensi3e e*a' scheduled after the

final class lecture da& of the course. )he e*a' will +e paper-and-pen no electronic

assistance. nrollees will +e e*pected to answer content-related !uestions and to code

3erilog. 6 'a,eup 'a& +e ta,en for the final? if the scheduled final e*a' should +e

'issed for good reason.

Qui* or "am Information Sharing

6ll enrollees or others e*posed to the course are on their honor not to share an&

content /!uestions or answers of an& !ui$ or e*a' with an&one.


18/114

2014-01-11 Notes for Digital VLSI Design with Verilog 1(

,etting )eady for Class .ttendance

6t the ti'e of this writing? the )e*t+oo, is a+out fi3e &ears old. :efore doing an&thing

else?

1. >se the preceding ErrataE in these Notes to fi* all )e*t+oo, errors.

2. >se the ESupple'entar&E 'aterial +elow in these Notes to update the3arious parts of the )e*t+oo, indicated.

%odification of the )e*t+oo, 'a& +e done with stic,& notes? or +& writing corrections

on the )e*t+oo, pages.

If &ou are attending the course? it is strongl& reco''ended to read each )e*t+oo, class

lecture and la+ at least once +efore the scheduled da&.


19/114


&ee- ! Class !)oda>s Agenda.

Introductor Lecture

)opicsA Course content and organi$ation.

Su''ar&A )his is a 3erilog language course. It is hea3il& la+-oriented and itsgoal is netlist s&nthesis? 'ore than si'ulation? as a content-related s,ill.

;o'ewor, reading assign'ents are of ut'ost i'portance? +ut neither la+s nor

ho'ewor, are graded. Dail& !ui$$es /after the first wee, and the final e*a'

are graded.

Introductor La+ !

)his introduces tool operation of the s&nthesi$er and si'ulator. It is 'eant to +e

e*ecuted +& rote e*planations will follow.

La+ ost'orte'

6fter ha3ing seen a 3erilog design through the tool flow? the enrollee is e*plainedthe +asic language constructs which were in3ol3ed.


20/114


Introduction to this Course

)he course is on the 3erilog language? as e*ercised +& concentrating on logic s&nthesis

with the SynopsysDesign Co'piler. Si'ulation will +e to 3erif& the 3erilog for

s&nthesis rather than to teach si'ulation techni!ues.

)he grading polic& is e*plained at the +eginning of this Course Note :oo,. Qou are on&our honor not to share an& content /!uestions or answers of the !ui$$es or an& e*a'

with an&one? whether the& are enrolled in this course or not.

)ead the Course /ote 0oo! section#s' and Tetboo! chapter for each day

before the day the class is held. )his will gi3e &ou the opportunit& to for'ulate

!uestions and deepen understanding +efore the presentation. Don@t put off this readingR

*cept for the introductor& la+ toda&? reading la+ instructions for the first ti'e in the la+

'a& +e difficult? error-prone? and discouraging.

9asic ?round pdates to the current Note

:oo, pri'aril& will reflect changes in tool operation or perfor'ance.

Lecture. Lectures usuall& will not +e 3er& long? so none'ergenc& +rea,s are

discouraged. lease do interrupt if the lecture presentation has &ou lost. ;owe3er?

please sa3e detailed? ela+orati3e? or speculati3e !uestions for la+.

Co''unication inhi+its learning. lease do not use lectureti'e to wor, at the cell-phone or other co'puter.

Lab. )a,e a +rea, an& ti'e during la+. )he la+ 'achines are for &our use an& ti'e

during the course? e*cept during lecture.

La+s often are cu'ulati3eA Don@t discard results fro' &our la+s sa3e the' where &ou

co'pleted the' or in a +ac,up su+director&.

1omewor!. Neither la+ wor, nor assigned ho'ewor, is graded.


21/114


&ee- ! Class 2

)oda>s Agenda.

Lecture. %ore language constructs

)opicsA )raditional 'odule header for'at. Co''ents? procedural +loc,s?integer and logical t&pes? constant e*pressions? i'plicit t&pe con3ersions and

truncations? para'eter declarations? and 'acro /QdeGine definitions.

Su''ar&A 7e e*pand on the pre3iousl& introduced? +asic 3erilog constructs

allowed within a 'odule. )he e'phasis is on procedural +loc,s and 3ector

3alue con3ersions. Verilog para'eters are introduced as the preferred wa& of

propagating constants through the 'odules of a design the 'ain alternati3e?

glo+all& QdeGined 'acro co'pilation? also is presented.

)pe Conversion La+ 7

6 tri3ial design illustrates the use of QdeGineto control para'eters? and the use

of co''ents. 7e e*ercise constraints to s&nthesi$e for area and for speed.7e also do e*ercises in signed and unsigned 3ectors? and in 3ector assign'ents

of different width.

La+ post'orte'

)his is 'ostl& la+ FP6 also? the use of 3ector negati3e indices is discussed.

Lecture. Control constructs@ strings and 'essages

)opicsA )he iG? Gor? and case the conditional e*pression e3ent controls the

distinct conte*ts for +loc,ing and non+loc,ing assign'ents. )he Gorever

+loc, and edge e3ent e*pressions. %essaging s&ste' tas,s. Shift registers.

Su''ar&A rocedural control and the +asic iG? Gor? and casestate'ents are

introduced. )he relationship of iGto the conditional /EURE is descri+ed? with

warning a+out @@ e3aluations. :loc,ing assign'ents for uncloc,ed logic

non+loc,ing assign'ents for cloc,ed logic. )he Gorever+loc, is presented +ut

its use is not encouraged. posedgeand negedgefor se!uential logic are

presented. 6ssertions +ased on 5dispa6? 5strobe? and 5monitorare

ad3ocated as good design practice. inall&? a shift register is presented +riefl&

to prepare for the ne*t la+ session.

Non+loc-ing Control La+ "

6fter flip-flop and latch 'odels? 3erilog for a serial-load and parallel-load shift

register is coded? si'ulated? and s&nthesi$ed. 6 si'ple procedural 'odel of a

shift-register is gi3en.

La+ post'orte'

In addition to la+ FP6? so'e thought-pro3o,ing !uestions a+out s&nthesis and

assertions are as,ed.


22/114


Supple'entar Noteon )e*t+oo, p. 2"? 3erilog co''ent e*a'plesA In the codeat the +otto' of the page? the +oolean operators 'a& +e replaced for si'plicit& with

+itwise ones in all three assigne*a'plesA Gust change E--E to &? and EE to |

e3er&where.

Supple'entar Noteon )e*t+oo, p. 2? width adBust'entA Steps 1-4 in the'iddle of the page hold for 'ost of the +inar& operators. ;owe3er? according to IStd 1"4? Section (.4.1? logical and reduction operators are treated speciall&A Such

e*pressions are e3aluated first then the width is adBusted to that of the destination

/L;S? as shown in the code e*a'ples on the sa'e page. or e*a'ple? for regW4R0X )!

$( reg ,( , % ) -- $(? )and $each are e3aluated true or false as 4-+it 3ectors

then? the logical andis ta,en. Li,ewise? if regW4R0X ,( reg )! $( , % ) -- $(?

the andof )and $is e3aluated then? the result is lengthened for assign'ent to ,.

Supple'entar Noteon )e*t+oo, p. 28. 6 macroalso 'a& +e called acompiler directive. In 3erilog? the& al'ost alwa&s 'erel& are defined or assigned a

te*t 3alue to +e su+stituted. In principle? a 'acro could +e used? as in C? to e*ecute codeduring si'ulation? +ut not all tools will accept e*ecuta+le su+stitutions.

Supple'entar Noteon 5dispa6. 6dd a new paragraph a+o3e the first codee*a'ple on p. 2A E)he 5dispa6s&ste' tas, is li,e printGin Cor COOA It for'ats a

'essage to +e printed to the ter'inal window of the si'ulator. It is ignored during

netlist s&nthesis. 7e shall discuss details of 5dispa6later toda&.E

(arameter and Conversion Lab 2

)opic and LocationA Si'ple use of defined 'acro 3alues and para'eters in

s&nthesis. )&pe con3ersions? truncations? and nu'erical interpretation of 3ector 3alues.

7or, in the Lab04director& for these la+ e*ercises.

reviewA In this la+ we present a s'all 3erilog design consisting of a counter and a

+it-con3erter the latter represents hardware which refor'ats the counter@s output +&

padding it with $eroes to a configura+le width. )his design is para'eteri$ed alread&?

and the student 'erel& changes the 'acro controlling the para'eter 3alues and

s&nthesi$es the design. :asic constraints for netlist opti'i$ation then are e*ercised.

)he la+ then changes topic to ele'entar& signed and unsigned arith'etic operations to

+e chec,ed +& si'ulation. inall&? so'e ele'entar& e*ercises are si'ulated on

truncation and widening of 3erilog 3ectors.

Delivera+lesA 1. 6n area-opti'i$ed netlist and a speed-opti'i$ed netlist s&nthesi$ed

in Step 1. 2. 6 second set of Step 1 area and speed opti'i$ed netlists with the

Converterpadding 3alue changed. ". #ne or 'ore new 3erilog 'odules in a file na'ed

ntegers.v? with assign'ent state'ents as descri+ed in Step 2. 4. 6 3ariet& of

assign'ent state'ents in one or 'ore 'odules in a file na'ed runcate.v? to fulfill

Step ".


23/114


Supple'entar Noteon )e*t+oo, p. 29? La+ "? Step 1A )his particular s&nthesis.sctfile +egins with nu'erous D";-specific co''ands? Bust to show how a s&nthesi$er

'ight ha3e to +e configured to generate an D";netlist for fa+rication purposes. Such

co''ands will +e o'itted in all our su+se!uent la+s.

6lso? if &ou si'ulate theParamCounterop

design? ignore the )e*t+oo, instruction to

Euse the DC'acroEA )he QiGdeG DCconstruct alread& has +een added.

inall&? the following two paragraphs should +e added after the paragraph +eginning?

EDon@t +other si'ulating? . . .EA

EIn this and all su+se!uent la+s? to run the s&nthesi$er? use the la+-specific .sct

s&nthesis script file pro3ided for &ou. 7hen none is pro3ided? &ou should create &our

own +& cop&ing an e*isting .sctfile and 'odif&ing it in a te*t editor. Such 'odification

generall& will include changes in the na'es of the 3erilog input files? the na'e of the

s&nthesis li+rar& /wor,ing director&? and the na'es of log files and s&nthesi$ed netlists.

)he .sctconstraints will ha3e to +e 'odified with special attention to the intended

design functionalit&.

E;ardl& an&one in practice writes down a s&nthesis script file e*cept +& starting fro' a

copied te'plate.E

Supple'entar Noteon )e*t+oo, p. "0? La+ "A In new VCS? 3ector displa&for'ats are associated with 3aria+les? not with displa&ed traces so? it is not possi+le to

3iew a 3aria+le in 'ore than one radi* at a ti'e.

Supple'entar Noteon )e*t+oo, pp. "2 - "" discussion of cloc,ed logic and cloc,generatorsA

;ere are e*a'ples of code paired with e!ui3alent sche'aticsA

aBa6s7posedge C3 I ;% D

aBa6s7negedge C3 I ;% D

initia Coc3 % 1'b0(...aBa6s7Coc3:10 Coc3 ;% FCoc3(


24/114


Supple'entar Noteon cloc, gating and recon3ergence. 7hile the si'ple andgate shown in igure 2.2 /)e*t+oo, p. "

illustrates the point? with the logic shown? an

as&nchronous ShiGtKnacould cause a glitch on

the gated cloc,? with unpredicta+le results. 6

realistic cloc, gate would use a transparent latchwhich was ena+led +& the inacti3e edge of the

cloc, to +e gated? as shown to the right.

#f course? the additional dela& of the latch would 'a,e the recon3ergence dela& longer?

possi+l& re!uiring 'ore design effort to a3oid it.

/onbloc!ing Control Lab 3

)opic and LocationA %odels and assertions for D flip-flops? D latches also for shift

registers? serial- and parallel-load? +uilt using the flip-flop 'odels.7or, in the Lab0director&. Create su+directories under Lab0if &ou want.

reviewA Non+loc,ing assign'ent state'ents are used for cloc,ed se!uential logic

ele'ents such as flip-flops. In this la+? we 'odel single flip-flops with 3arious features

such as as&nchronous preset or clear. 7e also 'odel latches to see how this is done. 7e

then use the flip-flop 'odels to construct a shift register with serial load of data. )his

shift register is tested +& si'ulating it. )hen? we 'odif& the shift register +& adding

'ultiple*ers so that it can +e loaded all +its in parallel. )his last design is s&nthesi$ed

for area and for speed. inall&? a 3astl& si'pler procedural shift register is presented

and su+tleties of its design are e*plored in si'ulation and s&nthesis.

Delivera+lesA Step 1A 6 3erilog source 'odule with three different D flip-flop 'odels.

S&nthesi$ed netlists of this 'odule opti'i$ed for area and speed. Step 2A 6 si'ulata+le

3erilog source 'odel. Step "A 6 source 'odule with three different latch 'odels and

s&nthesi$ed netlist plus? assurance that latches were s&nthesi$ed as e*pected. Step 4A

6 structural? serial-load shift register 'odel in at least two different files which

si'ulates correctl&. Step (A 6 structural parallel-load shift register 'odel in at least

three different files this should si'ulate correctl& and should +e s&nthesi$ed to two

different netlists? one opti'i$ed for area and the other for speed. Step A )wo

si'ulation 'odels of a procedural shift register? one using non+loc,ing assign'ents and

the other +loc,ing.

Supple'entar Noteon Step 1 of La+ 4A 6dd a new paragraph on p. "8 at theend of Step 1A E:ecause these three aBa6s+loc,s will coe*ist in the sa'e 'odule? their

procedural 3aria+les /regs will ha3e to +e declared with three different na'es. 6lso? to

put the three regs into the /hardware si'ulation design? each one will ha3e to +e wired

to a 'odule output port with its own continuous assign'ent state'ent.E

6 glitch-proof gated cloc, assu'ed acti3e high.


25/114


Supple'entar Noteon ig. 2.( of p. 40A 6 'inor i'pro3e'ent to this figurewould +e to re3erse the two top inputs to the left'ost 'u*? li,e thisA


26/114


&ee- 2 Class !

)oda>s Agenda.

Verilog Lecture

)opicsA Varia+lereg

and net t&pes constants +asic si'ulation and relation to

s&nthesis +asic s&ste' tas,s P LI. Internal scan.

Su''ar&A )his ti'e we stud& a 3ariet& of features of the 3erilog language. 7e

+egin +& e*plaining regand net 3aria+les again? and we distinguish se3eral of

the t&pes of net a3aila+le in 3erilog. 7e 'ention :N for'at for clarif&ing

s&nta*. 7e then return to se!uential logic s&nthesis? using latch and 'u*

si'ilarities to illustrate how co'+inational logic should +e 'odelled. 7e

introduce the +asics of cloc, si'ulation and point out so'e si'ple wa&s of

a3oiding race conditions. 7e wrap up with a +rief presentation of internal and

+oundar& scan? which increase o+ser3a+ilit& of design state in the hardware.

Si'ple Scan La+

>sing the co'+inational ntro_opdesign of the first la+ of the course? we add a

G)65 port? register all inputs and outputs using flip-flops? install 'u*es? and

lin, the flip-flop 'u*es to for' a scan chain. inall&? we add an assertion to

+e sure the scan 'ode operates correctl&.

La+ ost'orte'

7e discuss glitches and scan-chain operational refine'ents.

Simple Scan Lab 4

)opic and LocationA 6n internal-scan chain for'ed fro' 'u*ed flip-flops.

reviewA 7e 'odif& the original Lab01de'o design? ntro_op? so that it includes

so'e design-for-test /D) logic as followsA 7e add a G)65 port and then insert

se!uential co'ponents /flip-flops on e3er& I#. )hus? we con3ert our purel&

co'+inational ntro_opdesign into a s&nchronous one. 6fter that? +ecause our design

now includes se!uential ele'ents? we can replace these ele'ents with scanna+le ones.

7e do this first +& adding 'u*es to Eshort-circuitE the data flow awa& fro' the flip-flops?

under control of the 'u* select state. 7e then chain the flip-flops together? two 'u*es

for each flip-flop? so that one select state connects all flip-flops into a shift register? and

the other select state Bust lea3es the flip-flops on the I#@s in the design. inall&? we add

an assertion to report 'isuse of the chain when the design is in the scan state.

Delivera+lesA Step 1A 6 single 3erilog 'odule? correctl& si'ulating? with se3en

independent D flip-flops connected separatel& to the 'odule I# ports also? two

s&nthesi$ed netlists? one opti'i$ed for area and the other for speed. Step 2A 6 correctl&

si'ulating 3erilog 'odel of a flip-flop with s&nchronous clear. Step "A 6 si'ulation

'odel and s&nthesi$ed netlists as in Step 1? +ut with D latches instead of flip-flops

results of inspecting the netlists for correctness. Step 4A )wo or 'ore 3erilog 'odule

source files 'a,ing up a correctl& si'ulating serial-load shift-register. Step (A )hree or

'ore 3erilog 'odule source files 'a,ing up a correectl& si'ulating parallel-load shift

register also? two netlists /s&nthesi$ed for area and speed. Step A 6 procedurall&-


27/114


'odelled serial-load shift-register in a single 3erilog source file /test+ench 'a& +e in a

separate file one s&nthesi$ed netlist? opti'i$ed an& con3enient wa&.

Supple'entar Noteon procedural +loc,sA #n p. 4(? change the "rd ite' in the+ulletted list of +loc, contents toA

procedural control state'ents /iG Gor case Gorever

Supple'entar Noteon pp. 4(-4? :NA )he e*a'ple should +e replaced with a+etter one as followsA

E. . .. or e*a'ple? suppose for si'plicit&@s sa,e that the :N for a logical operator

was?

ogic_op RR% booean_op |bitBise_op

booean_op R% -- | |F

E)hen? fro' this we 'a& deduce that a logical operator alwa&s will +e a +itwise

operator or a +oolean --? ? or F. 6n atte'pt to use su+traction /& as a logical

operation then would +e an error easil& recogni$ed fro' the :N gi3en in this e*a'ple.E

Supple'entar Noteon 'odelling se!uential logicA #n p. 4? the first sentencein the first paragraph on ECloc-sE should +e re3ised toA E6 cloc,ed +loc, in 3erilog is an

aBa6s+loc, with an e3ent control containing an edge e*pression? posedgeor

negedge.E

Supple'entar Noteon as&nchronous controls? p. 49A 6dd a new paragraph Busta+o3e the section? E


28/114


Supple'entar Noteon )e*t+oo, La+ ( Step 2? p. (4A 7hen this Step isco'plete? the original ntro_opdesign? fro' La+ 1? should ha3e +een changed so that

it@s sche'atic would loo, li,e thisA

Supple'entar Noteon )e*t+oo, La+ ( Step 8A )he new VCS shows theassertion 'essages li,e thisA


29/114


Supple'entar Noteon )e*t+oo, La+ ( #ptional Step 9A 6dd a new lastparagraph at the +otto' of p. (A E5i3e &our flip-flops instance na'es +eginning with

EE? for e*a'ple? @@#? @@? and @@, this is for consistenc& with the s&nthesis .sctfile

pro3ided for &ou in &our Lab0>director&. If &ou use other instance na'es? &ou will ha3e

to edit the set_ma_dea6co''and in the .sctfile accordingl&.


30/114


&ee- 2 Class 2

)oda>s Agenda.

Lecture on SerDes

)opicsA Serial 3s parallel data transfer?5C" $press? LL functionalit&.Seriali$er-Deseriali$er and LL design.

Su''ar&A 7e introduce our class proBect? a full-duple* seriali$er-deseriali$er

/serdes? +& discussing serial +us transfer ad3antages and the perfor'ance

specifications of a5C" $pressserdes lane. 7e then loo, at the seriali$er and

deseriali$er ends of a serdes on a +loc, le3el. 7e also see how a LL wor,s on

a +loc, le3el. 7e decide to start our proBect +& designing and i'ple'enting

the LL which will +e instantiated at each end of each serial line.

LL Cloc- La+

6fter designing and testing a digital LL? we s,etch out and si'ulate a

preli'inar&? generic parallel-serial con3erter. 7e finish with a parallel-to-

parallel fra'e encoder which 'a& +e used to prepare data for seriali$ation.

La+ ost'orte'

7e discuss si'ulator ti'e resolution and digital for'ats? co'parator features?

and our choice of fra'e encoding.

Supple'entar Noteson the )e*t+oo, section "ntroduction to SerDes and 5C"$pressA

or further insight into serdes? read the 7ood /2009 article cited in the eferences

a+o3e.

)he standard docu'ent for CIe 3ersion " was finished in 2012 the specified speed is

5+s per direction per lane? co'pared with 2.( 5+s and ( 5+s for 3ersions 1 and 2?

respecti3el&. )he pac,et for'at will +e changed so that 3er& co'ple* deseriali$ation

algorith's will per'it a for'at o3erhead of onl& a+out 2 +its per 1"0 +it data pac,et.

:ecause of la+ ti'e li'itations? our serdes does not perfor' an& pac,et

ac,nowledge'ent? 'a,ing our serdes perhaps a +it 'ore li,e thernet than CIe.

Supple'entar Noteon the LL co'paratorA #n p. 4? in the wa3efor's ofigure 4."? a @*@ 'eans that the /iCountis incre'ented on that Coc3nedge a @0@

'eans that it is reset to 2'b0on the opposite edge.


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(LL Cloc! Lab 5

)opic and LocationA LL si'ulation and s&nthesis? parallel-serial data con3ersion?

and fra'ing of data for seriali$ation.

:egin this la+ +& logging in and changing to the Lab0=director&.

reviewA In preparation for our serdes class proBect? we i'ple'ent a 3erilog LL

co'posed of V#? cloc, co'parator? and counter-'ultiplier 'odules. or a rough grasp

of for'at con3ersion pro+le's? we then co'plete a pro3ided s,etch of a generic parallel-

serial con3ersion 'odule. inall&? we loo, into a wa& of preparing parallel data into

fra'es for later seriali$ation.

Delivera+lesA Step 1A our .v'odule files with 'odules and port declarations

'odules are na'ed PLLsim? V@J? Coc3Comparator? and utiCounter. 6 fifth

test+ench file which instantiates the top-le3el 'odule? PLLsim? for si'ulation. Step 2A

6 3erilog 'acro Qincudefile na'ed PLLsim.incwhich contains V# operating

characteristic definitions. 6 wor,ing V# si'ulation 'odel pro3ided with a te'porar&?

fudged test+ench input which e'ulates Coc3Comparatorinput. Step "A 6 3erilog

'odel of the Coc3Comparator? to +e si'ulated later. Step 4A 6 3erilog 'odel of the

utiCounter? to +e si'ulated later. Step (A Si'ulation of the co'pleted PLLsim

'odule which 3erifies that our LL will trac, its input cloc, fre!uenc&? howe3er coarsel&.

Step A 6 co'pleted generic parallel-serial 'odel +ased on the inco'plete 3erilog 'odel

pro3ided? and which si'ulates correctl&. Step 8A 6 correctl& si'ulating fra'e encoder

s&nthesi$ed netlists of this encoder which atte'pt opti'i$ation for area and speed.

Supple'entar Noteon the La+ procedureA igure 4.10 should +e 'odifiedslightl& to 'a,e it o+3ious that the )dH@reEwire is a 2-+it +usA


32/114


Supple'entar Noteon last part of La+ A )he for'at of our class proBectSerDes serial pac,ets will +eA

='b00011000000100000000100000000000

)he last part of La+ is to Bust to perfor' a refor'at of "2 +its of data to the a+o3e

,ind of 4-+it pac,etA

Data2 Data$ Data+ Data%

+eco'es

Data2 (ad2 Data$ (ad$ Data+ (ad+ Data% (ad%

)his can +e done procedurall&? if &ou wish or? +& continuous assign'entA

assign Pac3etW=4R>=X % Data4(

assign Pac3etW>>RX % Pad4( ... etc0...


33/114

2014-01-11 Notes for Digital VLSI Design with Verilog "0

&ee- 7 Class !

)oda>s Agenda.

Lecture on 'e'ories and verilog arras

)opicsA %e'or& chip si$e descriptions? 3erilog arra&s? parit& chec,s and data

integrit& fra'ing for error detection?

Su''ar&A 7e loo, into how the storage capacit& /in +its of a 'e'or& chip can

+e descri+ed? and then we show how to 'odel 'e'or& storage +& 3erilog

arra&s. 7e then stud& parit&? chec,su's? and error-correcting codes /CC as

wa&s of trac,ing data integrit& in stored 'e'or& contents -- or? in data storage

in general. 7e then show how parit& 'a& +e used in 10-+it serial data fra'es

to e*tract a serial cloc,.

La+ on


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s&ste' /e0 g0? +& identified crash of a specific hard disc +efore the CC is in3o,ed.

Supple'entar Noteon the Etoggle +itE e*planation? )e*t+oo,? p. 94. )o e*pandupon the discussion of the lagging frame error? consider the following three specific

data +it-patterns? each for'atted in errorA

A. Data 'b0000_0000A 1$for'ats the serial fra'e as 10'b0000_0000_01? inwhich the LS: is the in3erted %S: toggle +it and the preceding +it is the parit& /with

toggle +it ignored. 7ith a lagging 1-+it fra'e error? &$drops the %S: as part of the

pre3ious fra'e and calculates parit& +ased on this pattern? 10'b0000_0000_1. )he @@

is the ignored LS:. )he resulting parit& of @1@ e!uals a parit& error.

9. Data 'b1000_0000A 1$for'ats the fra'e as 10'b1000_0000_10 &$recei3es

10'b0000_0001_0and calculates a parit& error.

C. Data 'b0000_0001A 1$for'ats the fra'e as 10'b0000_0001_11 &$recei3es

10'b0000_0011_1and again calculates a parit& error.

Memory Lab 6

)opic and LocationA Single-port 6% and a si'ple wa& to 'a,e 'e'or& I# ports

+idirectional.

reviewA 7e e*ercise 3arious ,inds of 3erilog arra& assign'ent. )hen? we use an

arra& to design a single-port static 6% "2 +its wide and "2 addresses deep? with parit&.

7e add a Gorloop in our test+ench to chec, the addressing and data storage of this

'odel we use the si'ulator 'e'or& or 5dispa67to loo, inside the 'e'or&. inall&?

we 'odif& the 6% fro' two? unidirectional input and output data +usses to a single?

+idirectional input-output data +us. 7e use the concept of a EwrapperE 'odule to

co'+ine the original data +usses. inall&? we s&nthesi$e the +idirectional? single-port6%.

Delivera+lesA Step 1A 6 3erilog 'odule in a file with the specified declarations and

assign'ents si'ulated. Step "A 6 corner-case-correct single-port 6% si'ulation

'odel with parit& and an assertion which reports an& parit& error. Step 4A 6 test+ench

including a Gorloop with e*hausti3e testing and displa& of data storage +& the 6%

'odel. Step A 6 'odified? correctl&-si'ulating 6% 'odel with one? +idirectional data

+us. Step 8A )wo s&nthesi$ed 3erilog netlists of the +idirectional 6% 'odel? one

opti'i$ed for area and the other opti'i$ed for speed.

Supple'entar Noteon Section (.2.2Additional Study? p. 99A Since this we+site was 3isited last? 7agner@s 1he !a#s o' Cryptography #ith Java Codehas +een

pu+lished in D for'at? with the ;a''ing code presentation as one chapter. It is

a3aila+le at httpR


35/114


&ee- 7 Class 2

)oda>s Agenda.

Lecture on counters and the verilog for the'

)opicsA Hinds of counter +& se!uence. Counter structures discussedA ripple?

s&nchronous? one-hot? ring? gra& code.

Su''ar&A 6fter defining what we 'ean +& a EcounterE? we e*a'ine t&pical

ter'inolog& used to descri+e ;DL 'odelling in general. )hen? we e*a'ine

se3eral ,inds of counter t&picall& used in hardware designA ipple?

s&nchronous /carr& loo,-ahead? one-hot? ring? and gra& code.

Counter La+

7e write? si'ulate? and s&nthesi$e se3eral different ,inds of counter? showing

how the rarel&-used Bornet 'a& +e applied in one of the'. 7e finish +&

using our old LL cloc, output to dri3e three of the' in the sa'e design.

Supple'entar Noteto Section .1A 6 +inar& up-counter can +e progra''ed tocount Bust ten? instead of 1? 3alues in at least two different wa&sA

1. rogra' the wrap-around. )his is the 'ost co''on wa& and gi3es a count o3er

the nu'erical 3alues 0..9A

aBa6s7posedge C3! posedge Mst

iG 7Mst %% 1'b1

Count ;% 'h0(

ese begin

iG 7Count ; 9

Count ;% Count * 1(

ese Count ;% 'h0( end

2. reload the counter to +ias the wrap-around. )his gi3es a count o3er an& ten

contiguous? ascending 3alues. or e*a'ple? for the ten highest 3alues?

regW4R0X Count(

aBa6s7posedge C3! posedge Mst

iG 7Mst %% 1'b1 Count %% 'hG

Count ;% 'h=(

ese Count ;% Count * 1(

Supple'entar Note on ripple counter noiseA In Section .1.4.1? the lastparagraph? final sentence should sa& that the instantaneous power consu'ption andnoise are reduced? when co'pared with a s&nchronous counter of the sa'e width and

cloc, speed. #f course? the total power also would +e less for the ripple counter.


36/114

2014-01-11 Notes for Digital VLSI Design with Verilog ""

Counter Lab &

)opic and LocationA 7e write 3erilog counter 'odels? si'ulate the'? and

s&nthesi$e the' to co'pare perfor'ance of the s&nthesi$ed netlists. 7e also create a

new design in which our old LL is used to cloc, three different counter structures.

7or, in the Lab0director& for this la+.

reviewA 7e start with 3erilog for a ripple counter? using flip-flop 'odels fro'

pre3ious la+s. 7e s&nthesi$e a netlist fro' the ripple-counter 'odel and co'pare its

si'ulation speed with a netlist s&nthesi$ed fro' a s&nchronous-counter 'odel. 7e also

write a +eha3ioral 3erilog 'odel of a counter and si'ulate and s&nthesi$e it. 6fter this?

we replace ore*pressions in the s&nchronous-counter 'odel with a Bornet? to see how a

wired or wor,s. inall&? we create a new 'odel +& instantiating our old LL and one

each of the ripple? s&nchronous? and +eha3ioral counters in a single? top-le3el 'odule

na'ed Coc3ed$6PLL we end the la+ +& si'ulating this 'odel.

Delivera+lesA Step 1A 6 correctl&-si'ulating ripple counter and two s&nthesi$ed

netlists? one opti'i$ed for area and the other for speed. 6lso? a record of the fastest cloc,

speed at which this 3erilog source 'odel will count correctl&. Step 2A )he sa'e as Step

one? +ut for a s&nchronous counter. 6lso? a dual-netlist si'ulation? using speed-

opti'i$ed s&nthesi$ed 3erilog netlists for the ripple-counter of Step 1 and the

s&nchronous counter of this Step. Step "A 6 +eha3ioral 3erilog counter? and netlists

s&nthesi$ed for area and speed. 6 +eha3ioral counter 'odified to count down and

si'ulated correctl&. Step 4A )he s&nchronous counter 'odel of Step 2 with orgates /or

e*pressions replaced +& Bornets. Step (A 6 correctl& si'ulating 'odel in which a LL

instance supplies the cloc, to dri3e a ripple counter instance? a s&nchronous counter

instance? and a +eha3ioral counter instance.

Supple'entar Notes. La+ rocedure Bpdate.

)esting counter speeds. >seQtimescae 1ns


37/114


)hen? use D@@? not D@@C? in &our s&nchronous counter. If &ou do this? after s&nthesis

the ripple counter netlist will contain a declaration of a D@@C? and the s&nchronous

counter netlist will contain a declaration of an otherwise identical D@@ this resol3es the

na'e conflict.


38/114

2014-01-11 Notes for Digital VLSI Design with Verilog "(

&ee- " Class !

)oda>s Agenda.

Lecture on strength# contention# and operator precedence

)opicsA Verilog dri3e and charge strength? race conditions? and operator

precedence in e*pressions.

Su''ar&A Verilog charge strength and dri3e strength are defined and ran,ed in

order to show how contention a'ong different logic le3els is resol3ed. )hen?

race conditions which lead to contention are discussed. inall&? the

precedence of 3erilog operators is presented? so that the logic in co'plicated

e*pressions 'a& +e handled correctl&.

La+ on strength and contention

Verilog dri3e strengths and race conditions are si'ulated. So'e of this la+ is

optional if &ou ha3e the Silos si'ulator pro3ided with )ho'as and %oor+& or

alnit,ar? &ou should +e a+le to do the optional parts at ho'e.

La+ ost'orte'

Si'ulation of contention.

Lecture on LL snchroni6ation

)opicsA Na'ed +loc,s? and +eha3ioral and patterned e*traction of serial cloc,s.

Su''ar&A Na'ed +loc,s are presented to pro3ide 'eans of ter'inating

e*ecution of a procedural loop. )hen? the general pro+le' of trans'itting a

cloc, with serial data is sol3ed? for purposes of the class serdes proBect? +&

specif&ing "2 +its of inert padding for e3er& "2 +its of data trans'itted. 6n

uns&nthesi$a+le +eha3ioral /procedural LL is descri+ed as an optional

digression +ut is not used. )he lecture lea3es for la+ the detailed de3elop'entof a patterned 3erilog solution for LL cloc, e*traction.

La+ on LL snchroni6ation

)his la+ e*ercises so'e sophisticated procedural code for serial cloc, e*traction.

It then shows how a co'+inational-logic +it swi$$le can +e e!uall& effecti3e and

'uch si'pler than a purel& procedural solution.

La+ ost'orte'

*traction of a serial cloc,A ;ow to deal with loss of s&nchroni$ationK

Supple'entar Note on assigndeassign? p. 11A 6long with deGparam? theseconstructs are strongl& discouraged in recent I Std 100 releases up through 2012and are li,el& to +e re'o3ed fro' future Std docu'ents.


39/114


Strength and Contention Lab 7

)opic and LocationA Verilog three-state pri'iti3es? contention +etween different

dri3e strengths? race conditions? and +itwise vslogic operators.

Do the nonoptional wor, of this la+ in the Lab09director&. )he Silos si'ulator 'a&

+e used at ho'e for the optional Steps of this la+? a wire strength e*ercise. If &ou dothese optional Steps? &ou 'a& want to +ring in copies of &our results and ,eep the' in

Lab09for s&nthesis in optional Step ( and for possi+le later reference.

reviewA )he optional Steps use two decoders in one 'odule to appl& all possi+le

pairs of 3erilog strengths? at opposite le3els? to a single 'odule output +it. 6 test+ench

counter guarantees e*hausti3e e*ercise of all possi+le contentions. )he la+ returns to

nonoptional Steps with coding e*a'ples of race conditions. 6 final e*ercise shows the

i'portant difference +etween +itwise and logical operators in 3erilog.

Nonoptional Delivera+lesA Step 1A 6 4-to-1 decoder 'odelled +& a casestate'ent?

which handles un,nown input +its and si'ulates correctl& then? two of these

i'ple'ented in one aBa6s+loc, in a 'odule na'ed Oetter. Step A 6 race condition

si'ulation 'odel. Step 8A 6 si'ulation 'odel showing the difference +etween @-@ and

@--@ when applied to 3ector operands.

5ptional Delivera+lesA e!uires Silos or a si'ilar old-st&le si'ulator. Step 4A )he

Oetter'odel fro' Steps 2 - "? with all buGiG1outputs tied together to a single net?

dri3ing a one-+it 'odule output port. Step (A 6 correctl& si'ulating Oetter'odel

de'onstrating correct contention output s&nthesi$ed netlists for area and speed.

Supple'entar Notes on dri3e strength? Section 8.1.1.1A )here is a fifth dri3e

strength na'ed high


40/114


/@@. 6s for the netlists? DC does not s&nthesi$e gates capa+le of relia+le resolution of

contention? and the s&nthesis li+raries don@t include such gates? an&wa&. Contention

al'ost alwa&s is an error in VLSI design? e*cept onl& contention vs. @N@ -- which VCS and

DC handle correctl&. )he onl& reason for running VCS on the 3erilog source in these

Steps is for a good s&nta* chec,.

(LL 0ehavioral Loc!8In Lab +%

)opic and LocationA eorgani$ation of LL 'odules +eha3ioral e*traction of a

serial cloc, fro' a serial strea'.

7or, in the Lab10director&.

reviewA 7e@ll de3elop here so'e understanding which will help us later in our

serdes class proBect. 7e first cop& o3er our LL 'odel fro' Lab0? rena'ing so'e

things and isolating the LL fro' its Lab0counters. )hen? we@ll edit a cop& of the

@indPattern'odel /de3eloped in the )e*t+oo, so that it wor,s to detect serial pac,et+oundaries in a fa,ed? constant serial strea' test pattern. 7e shall not &et hoo, the LL

to the pac,et-+oundar& detector e*traction of the pac,et +oundaries and thus of the

serial e'+edded cloc, will +e co'pleted later.

Delivera+lesA Step 1A 6 cleanl& isolated and rena'ed PLLop'odule representing

our full& functional LL 'odel of Lab0. Step 2A 6 correctl& si'ulating counter cloc,ed

+& PLLop. Step "A 6 +eha3ioral 'odel which si'ulates correctl& the e*traction of our

pac,et +oundar& patterns for the fi*ed test-pattern serial strea' supplied.

Supple'entar Note concerning Step "A @indPattern$ehis a si'ulation

'odel? onl&. It can not +e s&nthesi$ed.


41/114


&ee- " Class 2

)oda>s Agenda.

Lecture on :I:5 state*'achine design

)opicsA )as,s? functions? Gor3-Hoin+loc,s? state 'achines? and I#sSu''ar&A 6fter introducing tas,s and functions? we descri+e the procedural

concurrenc& of the for,-Boin +loc,. 7e then discuss the +est use of 3erilog in

state 'achine design. 6fter that? we descri+e operation of a I# in detail?

focussing on the read and write address controls. 7e end +& descri+ing how to

code a I# controller state 'achine in 3erilog.

La+ on :I:5 design

6fter a war'up on tas,s? a si'ple I# state 'achine is coded.

La+ ost'orte'

I# design across cloc, do'ains gra& code counters.

Supple'entar Note on tas,s and functions. #n )e*t+oo, p. 148? add a newlast paragraph to .1.1.1A EState'ents to +e run +& a tas, or function 'ust +e placed

+etween its beginand end,e&words. Local 3aria+le declarations /reg? integer? rea

'ust appear +efore the begin. 6 tas, e*its? returning nothing? after its last state'ent

has +een e*ecuted a function returns the 3alue assigned to its na'e /or? the last

e*pression assigned? if nothing is assigned to its na'e.

Supple'entar Noteon @indPattern.von p. 149A See the end of toda&s notes.

Supple'entar Note concerning Gor3&Hoin. #n )e*t+oo, p. 1(0? the two codee*a'ples could +e i'pro3ed +& su+stituting the following twoA

;ere? Jut$usMegis updated 4 ns after cloc,? and the change in Data$usW4Xis not

seen until the ne*t cloc,A

aBa6s7posedge C3

begin

:1 Data$usW0X ;% 1'b0(


:4 Data$usW2X % 1'b0(

: Data$usW4X ;% 1'b1(


42/114


7ith this Gor3&Hoin? Jut$usMegis updated with all changes ( ns after cloc,A

aBa6s7posedge C3

begin

Gor3


:2 Data$usW1X ;% 1'b1( :4 Data$usW2X % 1'b0(

: Data$usW4X ;% 1'b1(

Hoin

:1 Jut$usMeg % Data$us(


43/114


============== FindPattern.v? as 'entioned in the )e*t+oo, p. 149A


44/114



45/114


&ee- Class !

)oda>s Agenda.

Lecture on rise*fall delas and the verilog event 4ueue

)opicsA egular and scheduled dela&s? rise 3s. fall? e3ent controls? and the 3erilogsi'ulation e3ent-scheduling !ueue.

Su''ar&A 7e descri+e regular vs. scheduled /intraassign'entdela& state'ents

inline in the 3erilog code? which represent gate-to-gate or 'odule-to-'odule

dela&s? onl&. 7e then see how to specif& different rise and fall dela&s? and

different dela&s for high-i'pedance? in these state'ents. 6fter that? we loo,

into how the 3erilog language re!uires a si'ulator to !ueue up? e3aluate? and

schedule assign'ents to 3aria+les. 7e finish with the two different 3erilog

e3ent controls? @@ and @Bait@.

La+

Dela& state'ents and e3ent scheduling.

La+ ost'orte'

F P 6 on the e3ent !ueue? la+ results? and so'e fine points on dela&s.

Supple'entar Notes concerning t&pes of dela& e*pression. #n p. 19 of the)e*t+oo,? the last sentence +efore the code e*a'ple refers onl& to procedural dela&s and

should sa&? Eor procedural state'ents? the possi+ilities are?E. 7hat the )e*t+oo,

descri+es as scheduleddela&s are not allowed in continuous assign'ents.

6lso? the )e*t+oo, ter'inolog&? Escheduled dela&sE? is nonstandard the I Std 1"4

/Section 9.8.8 uses intraassignment delaysto refer to this construct.

Supple'entar Note concerning 'ulti3alue wire dela&s. #n p. 181 of the)e*t+oo,? it is 'entioned that the ti'e to@@ uses the shortest a3aila+le dela&? whether 2-

3alued or "-3alued. %ore specificall&? when the transition isfrom@@? the specified dela&

to the target le3el is used onl& when the transition isfrom@@ to@N@ and Bust two 3alues

are gi3en? the shorter dela& is used.

Supple'entar Notesconcerning )e*t+oo, p. 182? it should +e e'phasi$ed thatone cannot create contention with single procedural assign'ents? alone.

A. )he first code e*a'ple on p. 182 is irrele3ant and should +e replaced.

Instead of this e*a'ple? consider the following one? which points out how +loc,ingassign'ents are affected +& :0dela&s. )he following is poorl& written and

uns&nthesi$a+le? +ut it is legal verilogA


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...

reg ! 6! N(


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9(Initiali$ation +efore si'ulation ti'e is set to 0. In igure 9.2? the +loc, pointing to

the Eset t 0E +loc, should sa&? Eead past


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Scheduling Lab +$

)opic and LocationA 3ent scheduling +& t

digital design with verilog: course notes for first edition

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