digital design: fundamental mode sequential circuits part - ii

Chapter 18

FUNDAMENTAL MODE SEQUENTIAL

CIRCUITS

Ch18L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

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Lesson 2

ANALYSIS OF ASYNCHRONOUS

SEQUENTIAL CIRCUIT


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Outline

• Analysis Procedure• Excitation cum Transition table• State table and state Diagram• Flow table and diagram


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Analysis Procedure —Fundamental Mode circuit

• Step 1: Draw logic circuit diagram to be analyzed

• Step 2: Draw circuit such that feedback-lop is clear, feedback loop minimized to have minimum feedback inputs and outputs. Find circuit x’q1, x’q2 , ... and inputs yq0, yq1 and yq2 inputs to memory section are there.


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Analysis Procedure• Step 3: Perform state variables xQ

assignments and excitation variables yQ (means latches and other delay-circuit elements inputs) assignments. [For example state variable assignments xq1 and xq2 and excitation variables yq0, yq1 and yq2.]


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Analysis Procedure• Step 4 (i) Find the expressions for the

excitations from the flip-flop characteristics equations as per the excitations. In other words, find Y = Fo(Xi, xQ) and thus Yj and yQ. (ii) Make an excitation table.


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Analysis Procedure• Step 5 Make excitation-cum-transition

table (or simply transition table) from the expressions for xQ’ = FQ (Xi, xQ,yQ) .


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Analysis Procedure• Step 6 Show the stable states and

transitions by horizontal and vertical directed arcs at excitation-cum-transition table and make flow diagram by making the state, flow and primitive flow tables

• Step 7: Find reduced flow table for the restricted inputs. Flow diagram is then drawn for final result of analysis. [Refer next lesson]


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Example: Draw Logic Circuit-i

X

J

K

D Q1

Q1

Q2

Q2


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Example: Draw Feedback loop and combination circuit distinctly

yq0, yq1, yq2m- latches Memory Section

Combinational Circuit

xq0

xq1

xq2

xq

Present state

Y0

yq0

yq1

yq2

Next state

Feedbackyq0, yq1, yq2

X

xq0, xq1, xq2


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Example: Find Expressions for Delay Section Inputs

• D = yq0

• J = yq1

• K = yq2


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Example: Find expressions for Combinational Circuit Inputs

• X = 0 or 1• xq1 = D = yq0 after a delay• xq2 = J. xq2 + K. xq2 after a delay

= yq1. xq2 + yq2. xq2 after a delay


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Example: Find Expressions for Combinational Circuit Outputs

• Y0= X . xq2.+ xq1

• yq0 = X . (xq2 + xq1 ) = D • yq1 = xq1 = J• yq2 = K = X


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Outline

• Analysis Procedure• Excitation cum Transition table• State table and State Diagram• Flow table and diagram


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Excitation cum Transition table

• Tabular representation of present state xqinput of the latches, X input, next state yqoutput, which will be feedback to the latches from the next state Y [YO and yq at the output stages].

• Gives the memory-section outputs that follow the excitations from yq outputfeedback


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Excitation Table for YO = X. Q2 +Q1; Q1’ =D and Q2’ = Qn+1 = J. Q n + K. Q n

State Excitation Inputs YO(Q1,Q2) [D, (J, K)]X=0 [D, (J, K)]X=1 X=0 X =1

�Y is present output state after the X inputs but before transition

(0, 0) 0, (0, 0) 1, (0,1) 0 0

(0, 1) 0, (0, 0) 1, (0,1) 1 0(1, 0) 0, (1, 0) 1, (1,1) 1 1

(1, 1) 0, (1, 0) 1, (1,1) 1 1


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Excitation-cum-Transition Table for Y = X. xq2 + xq1;

xq1’ =D and xq2’ = xqn+1 = J. xq n + K. xq

nState Transition Outputs Y (Q, Q2) [Q1’, Q2’]X=0 [Q1’, Qq2’]X=1 X=0 X =1

(0, 0) 0, 0 1, 0 0 0

(0, 1) 0, 1 1, 0 1 0(1, 0) 0, 1 1, 1 1 1

(1, 1) 0, 1 0, 0 1 1


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Outline

• Analysis Procedure• Excitation cum Transition table for

drawing flow table and diagram• State table and State Diagram• Flow table and diagram


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State Table • State table can made easily from excitation-

cum-transition table• A set of present Q0, Q1,.. denotes a state• Each set assigned a state-name Si as

follows:• (Q1, Q2) = (0,0) → S0• (Q1, Q2) = (0,1) → S1• (Q1, Q2) = (0,0) → S2• (Q1, Q2) = (0,0) → S3


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State table showing stable next states

• A state table gives the stable next state and output before this state. This state is that which finally exists after one or more feedback-cycles of next states from the memory section after change of an input Xk. That is fine when the finally what state(s) is achieved that matters

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State Table for Y = X. xq2 + xq1; xq1’ =D and xq2’ = xqn+1 = J. xq n +

K. xq n

State Next State-Transition Outputs YO

(yq) [xq]X=0 [xq]X=1 X=0 X =1

S0 S0 S2 0 0S1 S1 S2 1 0

S3 S1 S0 1 1S2 S1 S3 1 1

�YO is present output state after the xq outputs but before transition yq next state


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State Diagram for transitions to stable states

S0

S2

S3

S1

0/0

1/0

1/1

1/1

0/10/1

1/0 0/1


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State Minimization• A set of present (xq 0, xq1, … , xqm – 1) is

denoted by a state. There are z (=2m) maximum possible stable states S0, S1, S2, … , Sz–1 in asynchronous circuit with z-memory or delay section circuits. [The 2n

stable states can be reduced by state minimization method of finding the equivalent states. In that case state table will have less number of rows and state diagram less number of nodes


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State table showing intermediate states

• A state table also gives the unstable next states shown by vertical arcs in excitation cum transition table and output changes before this state. The final state is that which finally exists after one or more feedback-cycles of next states from the memory section after change of an input Xk. That is fine when the finally what state(s) is achieved that matters

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State Table for Y = X. xq2 + xq1; xq1’ =D and xq2’ = xqn+1 = J. xq n +

K. xq n


(yq) [xq]X=0 [xq]X=1 X=0 X =1

S0 S0 S2 0 0S1 S1 S2 1 0

S3 S1 S0 1 1S2 S1 S3 1 1



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State Diagram for transitions to stable states

S0

S2

S3

S1

0/0

1/0

1/1

1/1

0/10/1

1/0 0/1

Note that for X = 1, S0 first changes to intermediate state S2 and then to S3


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State table giving all states, whether certain set of inputs X, Y exist or not

• A state table gives all the next state(s) whether a certain set of inputs is specific as nonexistent after a certain sequence of set on inputs or existent. For example, when two simultaneous input bit changes not permitted (in fundamental mode circuit), at S2, the 01 will not follow 11 when X changes first


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Example, when 10 changes to 01

• S0 →S2 →S3 → S1 if Y changes first• S0 →S2 →S1 if X changes first


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State Diagram for transitions to stable states through intermediate states in two paths

S0

S2

S3

S1

0/0

1/0

1/1

1/1

0/10/1

1/0 0/1

When 1/0 becomes 0/1, it does not happen simultaneously. State table is showing both paths

S0 →S2 →S3 → S1 S0 →S2 →S1


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State table does not give

• The information about state that will not exist due to certain specified input constraints as it gives entries for all cases


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State table gives too much

• The information about state that will not exist due to certain specified input constraints as it gives entries for all cases


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State table does not give too much

• It does not provide the information about the flow (next sequence) of the stable states and outputs for the final stable existence after one or more feedback-cycles of next states from the memory section after change of an input Xk For a condensed view of the asynchronous circuit behavior, the flow part is required


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Outline

• Analysis Procedure• Excitation cum Transition table• State table and state Diagram• Flow table and diagram


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State table does not give

• It does not provide the information about the flow (next sequence) of the stable states and outputs for the final stable existence after one or more feedback-cycles of next states from the memory section after change of an input Xk For a condensed view of the asynchronous circuit behavior, the flow part is required


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Flow table• Gives the present state, for the

different input combinations next states (stable) and present outputs, which corresponds to ones leading to stable state. These states exist after one or more feedback-cycles to next stable states at the memory section after change of an input Xk

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Flow Table for Y = X. xq2 + xq1; xq1’ =D and xq2’ = xqn+1 = J. xq n +

K. xq n


(yq) [xq]X=0 [xq]X=1 X=0 X =1

S0 S0 S3 0 -

S3 S1 S0 1 1S2 S1 S3 0 1



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Flow Table in Example• Does not show row for S1, because S2

has Y= 1 for both X= 0 and 1, therefore, transition for S1 to S2 for X/Y = 1/0 is unstable and flow table shows only stable states,

• Shows dash for Y as for S0 the excitations X/Y = 1/0 does not exist in stable case


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Flow Diagram for transitions to stable states

S0

S3

S2

S1

0/0

11/1

1/1

0/10/1

1 0/0

When 1/0 becomes 0/1, it does not happen simultaneously. Flow table is showing one path and stable state only


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Flow diagram

• States S0, S1, S2 and S3 are labeled at the centers of each circle representing a node

• Each arc or circular arc is labeled with present input and the present output at the transition. If there is dash, then slash sign and Y for that are not shown


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Flow diagram

• Each arc or circular arc can have more then one set of (pre-transition input/ post transition output) labeled on it if there are more than one sets of (pre-transition input/ post transition output) that are having the same transition from a node to another.


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Flow diagram• If there are only inwards arcs at a node from

other nodes , it shows that from that state, there are no transitions that are stable and eventually state will flow back to the same.

• In flow table, it shows missing row(s) for that node

• In flow table, dash at Y shows, that output will undergo transition and that X/Y non existent in stable states after intermediate cycles


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Flow Table

• Unstable states, which lead to other unstable states, are not shown in flow table and at a table next state entry, only the eventually occurring states are shown. Flow table gives the condensed view of the circuit

Summary

• Analysis of a asynchronous fundamental mode circuit is done by drawing circuit, from which memory section and combinational circuits, from which excitation-cum-transition tables, state table and finally flow table is drawn

• Excitation-cum-transition table shows the excitation input change by horizontal directed arc, stable states by marking over it.

• Table shows the excitation input change by horizontal directed arc, stable states by marking over it

• Then state table is drawn by assigning a state to each set xq.

• Flow table and flow diagram are then drawn for final result of analysis

End of Lesson 2 on ANALYSIS OF

ASYNCHRONOUS SEQUENTIAL CIRCUIT


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