dig(dpsd) lab manual
DESCRIPTION
the manual for the dig lab.TRANSCRIPT
EASWARI ENGINEERING COLLEGE
DEPARTMENT OF INFORMATION AND
TECHNOLOGY
LABORATORY MANUAL
DIGITAL LABORATORY
Subject Code : CS2207
Semester : III
Year : II
Department : IT
PREPARED BY HOD
Ms.L.Bhagyalakshmi
Ms.S.Deepa
Ms.S.Uma
CS 2207 DIGITAL ELECTRONICS LAB 0 0 3 100
1. Design and implementation of Adders and Subtractors using logic gates.
2. Design and implementation of code converters using logic gates
(i) BCD to Excess-3 code and vice versa
(ii) Binary to Gray Code and vice-versa
3. Design and implementation of 4 bit binary Adder/ subtractor and BCD
adder using IC 7483
4. Design and implementation of 2 bit Magnitude Comparator using logic
gates 8 Bit Magnitude Comparator using IC 7485
5. Design and implementation of 16-bit odd/even parity checker and
generator using IC 74180.
6. Design and implementation of Multiplexer and De-multiplexer using logic
gates and study of IC 74150 and IC 74154
7. Design and implementation of encoder and decoder using logic gates and
study of IC 74145 and IC 74147
8. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12
Ripple counters
9. Design and implementation of 3-bit synchronous up/down counter
10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip-
flops
LIST OF EXPERIMENTS
1) Study of Logic Gates
2) Verification of Boolean theorems using digital logic gates
3) Design and implementation of combinational circuits using basic
gates for arbitrary Boolean function
4) Design and implementation of Adders and Subtractors using logic
gates.
5) Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa
(ii) Binary to gray and vice-versa
6) Design and implementation of 4 bit binary Adder/ Subtractor using
basic gates.
7) Design and implementation of 4 bit binary Adder/ Subtractor and
BCD adder using IC 7483
8) Design and implementation of 2 Bit Magnitude Comparator using
logic gates 8 Bit Magnitude Comparator using IC 7485
9) Design and implementation of Even/Odd Parity Generator /
Checker using basic gates.
10) Design and implementation of Multiplexer and De-multiplexer
using logic gates and study of IC 74150 and IC 74154
11) Design and implementation of Boolean Function using
Multiplexers.
12) Design and implementation of Encoder and Decoder using logic
gates and study of IC 74145 and IC74147
13)a) Construction and Verification of 4 – Bit Ripple Counter, Mod-
10 Counters Using JK Flip-Flop
b)Design and implementation of 3-bit synchronous up/down
counter.
14) Implementation of SISO, SIPO, PISO and PIPO shift registers
using Flip- flops.
15) Coding combinational circuits using Hardware Description
Language (HDL software required)
16) Coding sequential circuits using Hardware Description Language
(HDL software required)
PIN DETAILS OF LOGIC GATES
IC 7400 IC 7402
IC 7404 IC 7408
IC 7432 IC 7486
IC 74266
Ex. No: 1 STUDY OF LOGIC GATESDate:
AIM:To study the working of the logic gates and verify their truth tables.
COMPONENTS REQUIRED:S.No. Apparatus Specifications Quantity
1. IC Trainer kit -- 1 no2. Logic gate IC’s IC 7404, IC 7408, IC 7432 1no each3. Logic gate IC’s IC 7402, IC 7400, IC 7486 1no each4. connecting wires -- 1 set
THEORY:
Positive Logic : In Positive Logic, +5 V is associated with Binary 1 while GND is associated with Binary 0.Negative Logic : In Negative Logic, +5 V is associated with Binary 0 while GND is associated with Binary 1.
Electronic circuits whose terminal characteristics correspond to various Boolean operations area called as Gates.
AND gat e: It has one output and two or more inputs. The output will equal 0 for all combinations of input values except when all inputs equal 1.
OR gate : It has one output and two or more inputs. If all inputs are caused to equal 0, the output will also equal 0. The presence of a 1 bit at one or more inputs leads to an output of 1.
NOT gate : It produces the INVERT operation. This logic element has one input and one output. The output level is always opposite to the input level.
Universal gates: Universal gates are the ones which can be used for implementing any Boolean function using gates like AND, OR and NOT, or any combination of these basic gates; NAND and NOR gates are universal gates. But there are some rules that need to be followed when implementing NAND or NOR based gates.
NOR gate: It is simply an OR gate followed by a NOT gate.
NAND gate: It is simply AND gate followed by a NOT gate. EX-OR gate: It is expanded as Exclusive-OR gate. It has one output and two or more
inputs. It produces an output of 1 if the inputs are of different logic levels and an output 0 if inputs are of the same logic level.
LOGIC GATES :
AND GATE NAND GATE
TRUTH TABLE TRUTHTABLE
OR GATE NOR GATE
TRUTH TABLE TRUTH TABLE
NOT GATE EX – OR GATE
TRUTH TABLE TRUTH TABLE
EX-NOR GATE:
A B Y=A.B0011
0101
1110
A B Y=A.B0011
0101
0001
A B Y=A+B0011
0101
0111
A B Y=A+B
0011
0101
1000
A Y=A00
10
A B0011
0101
0110
IC 7408
IC 7432
IC 7404
IC 7400
IC 7402
IC 7486
TRUTH TABLE
A B
0011
0101
1001
PROCEDURE:
1. Place the IC on the IC trainer kit and give the supply and ground
connections.
2. Apply the inputs to the logic gates through the input switches.
3. Observe the output of the gates in the LED indicators.
4. Verify the truth table of each logic gate.
RESULT:
Thus the working of the logic gates were studied and their truth tables were verified.
Viva Questions
1) What are universal logic gates
2) What is an inverter
3) What are the uses of AND-OR-INVERTER gates
4) An Ex-OR gate can be used as an inequality comparator. Justify
5) Distinguish between an inclusive OR and an Exclusive OR gate
6) Realize NOT, AND, OR, NOR, Ex-OR gates using only NAND gate.
7) Realize NOT, AND, OR, NAND, Ex-OR gate using only NAND gate
Exp.No:2Date:
VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES
AIM:To implement and verify the Boolean theorems using logic gates.
COMPONENTS REQUIRED:
S.No. Apparatus Specifications Quantity1. IC Trainer kit -- 1 2. Logic gate IC’s IC 7404, IC 7408,IC 7400 13. Logic gate IC’s IC 7402, IC 7486,IC 7432 14. Connecting wires -- Few
Theorems:
1. Idempotent laws:a) x+x =xb) x.x=x
2. Identity law:x+1 = 1
3. Null law:x.0 = 0
4. Involution law (or) double negation law:
(x ΄) ΄ = x
5. Associative law:x+(y+z) = (x+y)+zx. (y.z) = (x.y).z
6. Demorgan’s law:(x+y)΄ = x΄ . y΄(x.y)΄ = x΄ + y΄
7. Absorption theorem:x+(x.y) = xx.(x+y) = x
Procedure:
1. Draw the truth table for the respective Boolean theorem.
2. Decide the corresponding logic gates to be used to implement the
respective Boolean theorem.
3. Draw the logic diagram for the LHS and RHS expression of the
theorem.
4. Construct the logic circuit using the above gates.
5. Verify the truth table.
1. Idempotent laws:a) x+x =x
IC 7432 Truth Table
b) x.x=x Truth Table
IC 7408
2. Identity law:x+1 = 1 Truth Table
IC 7432
3. Null law:x.0 = 0 Truth Table
IC 7408
4. Involution law (or) double negation law:(x ΄) ΄ = x Truth Table
IC 7404 IC 7404
x x+x=x0 01 1
x x.x=x0 01 1
x x+1=10 11 1
x x.0=00 01 0
x x΄ (x΄)΄=x0 1 01 0 1
5. Associative law:a) x+(y+z) = (x+y)+z
Truth Table
L.H.S
IC 7432 IC 7432
R.H.S
IC 7432 IC 7432
b) x.(y.z) = (x.y).z
Truth Table
x y z y+z x+(y+z) x+y (x+y)+z
0 0 0 0 0 0 00 0 1 1 1 0 10 1 0 1 1 1 10 1 1 1 1 1 11 0 0 0 1 1 11 0 1 1 1 1 11 1 0 1 1 1 11 1 1 1 1 1 1
L.H.S
IC 7408 IC 7408
R.H.SIC 7408 IC 7408
6. Demorgan’s law:a) (x+y)΄ = x΄ . y΄
L.H.S
IC 7402 Truth Table
R.H.S
x y z y.z x.(y.z) x.y (x.y).z
0 0 0 0 0 0 00 0 1 0 0 0 00 1 0 0 0 0 00 1 1 1 0 0 01 0 0 0 0 0 01 0 1 0 0 0 01 1 0 0 0 1 01 1 1 1 1 1 1
x y x+y (x+y) ΄ x΄ y΄ x΄. y΄0 0 0 1 1 1 10 1 1 0 1 0 01 0 1 0 0 1 01 1 1 0 0 0 0
IC 7404 IC 7408
b) (x.y)΄ = x΄ + y
Truth Table L.H.S
R.H.S
7. Absorption theorem:
Truth Tablea) x+(x.y) = x
b) x.(x+y) = x Truth Table
x y x.y (x.y) ΄ x΄ y΄ x΄+y΄0 0 0 1 1 1 10 1 0 1 1 0 11 0 0 1 0 1 11 1 1 0 0 0 0
x y x.y x+(x.y)=x0 0 0 00 1 0 01 0 0 11 1 1 1
x y x+y x.(x+y)=x0 0 0 00 1 1 01 0 1 11 1 1 1
TRUTH TABLE:
A B C A΄ B΄ A΄C A΄B AB΄C BC F=-A΄C + A΄B + AB΄C + BC
0 0 0 1 1 0 0 0 0 0
0 0 1 1 1 1 0 0 0 1
0 1 0 1 0 0 1 0 0 1
0 1 1 1 0 1 1 0 1 1
1 0 0 0 1 0 0 0 0 0
1 0 1 0 1 0 0 1 0 1
1 1 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 1 1
LOGIC DIAGRAM OF GIVEN BOOLEAN FUNCTION:
K-Map Simplification
BCBC BC BC BCA
From K-map technique, the reduced expression obtained is : F = C+AB
LOGIC DIAGRAM OF SIMPLIFIED BOOLEAN FUNCTION:
0 1 1 1
0 1 1 0
A
A
Result:
Thus, the Boolean theorems are implemented and verified using logic gates.
Viva Questions
1) State Demorgan’s theorem for three variables2) What is associative law?3) What is distributive law?4) What is commutative law?5) What is duality law?6) State Idempotent law?7) What is the use of Demorgan’s theorem8) What is Concensus Theorem?
(AB + A’C + BC = AB + A’C)9) What are the NOT laws in Boolean Theorem10) What are the AND laws in Boolean Theorem10) What is the OR laws in Boolean Theorem11) Write the laws, which are useful for reducing Boolean expression
Exp.No:3Date:
DESIGN AND IMPLEMENTATION OF BOOLEAN
FUNCTION
AIM:To implement and verify the given Boolean function using logic gates.
COMPONENTS REQUIRED:
S.No. Apparatus Specifications Quantity1. IC Trainer kit -- 1 2. Logic gate IC’s IC 7404, IC 7432 1 3. Logic gate IC’s IC 7408 24. Connecting wires -- Few
Given function is: F= A΄C + A΄B + AB΄C + BC
Procedure: 1. Draw the truth table for the given Boolean function.
2. Determine the simplified expression for the output variable using K-Map.
3. Decide the corresponding logic gates to be used to implement the Boolean
function simplified using K-Map.
4. Draw the logic diagram according to simplified Boolean function.
5. Construct the logic circuit using the above gates.
6. Verify the truth table.
TRUTH TABLE:
A B C A΄ B΄ A΄C A΄B AB΄C BC F=-A΄C + A΄B + AB΄C + BC
0 0 0 1 1 0 0 0 0 0
0 0 1 1 1 1 0 0 0 1
0 1 0 1 0 0 1 0 0 1
0 1 1 1 0 1 1 0 1 1
1 0 0 0 1 0 0 0 0 0
1 0 1 0 1 0 0 1 0 1
1 1 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 1 1
LOGIC DIAGRAM OF GIVEN BOOLEAN FUNCTION:
Result:
Thus, the given Boolean function is implemented and verified using logic gates.
Viva Questions
1) What is K-map?1) What is the use of K-Map2) What are the limitations of K-Map3) Give the other name for K-Map4) What is a prime implicant5) What are don’t care terms6) What is meant by an incompletely specified function7) Distinguish between incompletely specified function and completely specified
function8) Explain the general procedure that could be adopted in reducing Boolean
expression9) List the two types of standard forms in Boolean algebra10) Give the two canonical forms of Boolean function11) What is a min term and max term12) What are hybrid functions
Exp.No: 4
Date:
DESIGN AND IMPLEMENTATION OF ADDERS AND
SUBTRACTOR
AIM:
a. To design a half adder / subtractor and verify the function
b. To design a full adder / subtractor and verify the function.
c. Realize a full adder using two half adders and logic gates.
APPARATUS REQUIRED:
S.NO COMPONENTS RANGE/TYPE QUANTITY
1
2
3
4
5
IC 7408
IC 7486
IC 7404
IC TRAINER KIT
CONECTING WIRES
AND
EX-OR
NOT
-
-
1
1
1
1
FEW
THEORY:
HALF ADDER:
Half adder is a circuit, which can add two numbers and produce two outputs,
sum and carry. From the truth table it is clear that sum represent the logic output of an
EX-OR gate and carry, that of an AND gate. Thus a half adder can be built using two
gates.
FULL ADDER:
When the carry is generated by the addition of two bits, this has to be added to
next bit sum. Half adders do not allow this. There are only two inputs present. A full
adder can be used for this purpose. Here three inputs are given, addend augends and
the previous carry.
SUBTRACTORS: The subtraction of two binary numbers is done by either
taking two’s complement of subtrahend and adding the numbers or by direct method
where bit-subtraction is carried out to form a difference bit and if necessary, a
borrow-bit just as in adders, there are half and full subtractor.
HALF SUBTRACTORS:
The two inputs, minuend and subtrahend are given to get two outputs, difference
and borrow. It is found that D is the same as S output of Half adder and B resemble C
of half adder except that input A is complemented.
FULL SUBTRACTORS:
This performs subtraction between two bits, taking into account that one may have
been borrowed by a lower significant stage. Three inputs minuend, subtrahend and
previous borrow to get two outputs borrow and difference.
PROCEDURE:
1. Draw the truth table of the respective adder/subtractor.
2. Determine the simplified expression for the output variable using K-Map.
3. Decide the corresponding logic gates to be used to implement the above
expression.
4. Draw the logic diagram according to output expression.
5. Construct the adder/Subtractor circuit using the above gates.
6. Verify the truth table.
HALF ADDER:
TRUTH TABLE:
Logic Diagram Of Half Adder
INPUT OUTPUT
A B SUM CARRY
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
HALF SUBTRACTOR:
TRUTH TABLE:
Logic Diagram Of Half Subtractor
INPUT OUTPUT
A B DIFFERENCE BORROW
0
0
1
1
0
1
0
1
0
1
1
0
0
1
0
0
FULL ADDER:
TRUTH TABLE
INPUT OUTPUT
A B Cin SUM CARRY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Logic Diagram Of Full Adder
FULL SUBTRACTOR:
TRUTH TABLE:
INPUT OUTPUT
A B Cin DIFF BORROW
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
1
Logic Diagram of Full Subtractor
RESULT:
Thus the full/half adder and subtractor circuits were designed and constructed
and the truth tables were verified.
Viva Questions
1) Define half adder and full adder2) Design half adder using only NAND gates3) Design half adder using only NOR gates4) Design half adder using only EX-OR and AND gates5) Design full adder using only NOR gates6) Distinguish between Half adder and full adder
Exp.No: 6
Date:
DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER
/SUBTRACTOR USING BASIC GATES
AIM:
To design and implement the four bit binary adder/subtractor using basic gates.
APPARATUS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY
1 EX-OR GATE IC7486 3
2 AND GATE IC 7408 2
OR GATE IC 7432 1
3 BREADBOARD - 1
4 CONNECTING WIRES - FEW
5 IC TRAINER KIT - 1
THEORY:
The addition and subtraction operations can be combined into one circuit with one common binary adder. The mode input M controls the operation of the circuit. When M=0, the circuit is an adder and when M=1, the circuit becomes a subtractor. Each ex-or gate receives input M and one of the inputs of B. When M=0,we have B0=B. The full adder receives the value of B, the input carry is 0 and the circuit performs the addition of A and B i.e. A+B. When M=1 we have B1=B’ and Cin=1.The B inputs are complemented and a one is added through input carry. The circuit performs the operation A plus2’s complement of B i.e. A-B.PROCEDURE:
1. Draw the truth table of the respective 4-bit binary adder/subtractor.
2. Determine the simplified expression for the output variable using K-
Map.
3. Decide the corresponding logic gates to be used to implement the
above expression.
4. Draw the logic diagram according to output expression.
5. Construct the 4-bit binary adder/Subtractor circuit using the above
gates.
6. Verify the truth table.
.
Truth Table:
Input A Input B SUM CARRYA3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Cout3 Cout2 Cout1 Cout0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 1 0 0 0 1 0 0 1 0 0 0 0 10 0 1 0 0 0 1 0 0 1 0 0 0 0 1 00 0 1 1 0 0 1 1 0 1 1 0 0 0 1 10 1 0 0 0 1 0 0 1 0 0 0 0 1 0 00 1 0 1 0 1 0 1 1 0 1 0 0 1 0 10 1 1 0 0 1 1 0 1 1 0 0 0 1 1 00 1 1 1 0 1 1 1 1 1 1 0 0 1 1 11 0 0 0 1 0 0 0 0 0 0 0 1 0 0 01 0 0 1 1 0 0 1 0 0 1 0 1 0 0 11 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0
1 0 1 1 1 0 1 1 0 1 1 0 1 0 1 11 1 0 0 1 1 0 0 1 0 0 0 1 1 0 01 1 0 1 1 1 0 1 1 0 1 0 1 1 0 11 1 1 0 1 1 1 0 1 1 0 0 1 1 1 01 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
K-Map Simplification
Logic Diagram for 4-Bit Binary Adder/Subtractor
Logic Diagram for Full Adder
RESULT:
Thus a 4-bit binary adder/subtractor were constructed using basic gates and the
output was verified
Exp.No: 7
Date:
DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER
/SUBTRACTOR USING IC 7483
AIM:
To design and implement the four bit binary adder/subtractor using IC7483.
APPARATUS REQUIRED:
S.NO COMPONENTS SPECIFICATION QUANTITY
1 EX-OR GATE IC7486 1
2 FOUR BIT BINARY
ADDER/SUBTRACTOR
IC7483 1
3 BREADBOARD - 1
4 CONNECTING WIRES - FEW
5 IC TRAINER KIT - 1
6 PATCH CORDS - FEW
PROCEDURE:
1. Draw the sample input table of the 4-bit binary adder/subtractor.
2. Decide the corresponding logic gates to be used to implement the truth table.
3. Draw the logic diagram.
4. Construct the 4-bit binary adder/subtractor circuit using the above gates.
5. Verify the truth table.
Sample Inputs:
ADDER(M=0):
A B S Cout
A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0
0 0 0 0 0 0 1 0 0 0 1 0 0
1 0 0 0 1 1 0 0 0 1 0 0 1
0 1 1 0 0 1 1 1 1 1 0 1 0
0 1 0 1 1 0 0 1 1 1 1 0 0
SUBTRACTOR(M=1):
A B S Cout
A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0
0 0 0 1 0 0 0 0 0 0 0 1 0
0 0 1 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 0 1 1 0 0 0 0 0
1 0 0 1 0 0 1 0 0 0 1 1 0
PIN DIAGRAM OF IC 7483
Logic Diagram 4-Bit Binary Adder
RESULT:
Thus a four bit binary adder/subtractor was constructed using IC7483 and the
output was verified.
Viva Questions
1) Draw a n-bit binary parallel adder2) What is a decimal adder? Name any decimal adder.3) What is the minimum no of inputs and outputs required for a decimal adder4) What do you mean by carry propagation delay5) Design the 4-bit BCD adder using 4-bit binary adders6) Draw the 4-bit BCD subtractor using 9’s and 10’s complement method7) Design 16-bit adder using two 7483 IC’s
Exp.No: 8
Date:
DESIGN AND IMPLEMENTATION OF 2-BIT MAGNITUDE
COMPARATOR USING LOGIC GATES AND 8-BIT
MAGNITUDE COMPARATOR USING IC 7485
AIM:
To design and implement the 2-bit and 8-bit magnitude comparator using logic
gates and IC 7485 respectively.
APPARATUS REQUIRED:
S.NO COMPONENTS SPECIFIACTION QUANTITY
1 AND GATE IC7408 3
2 OR GATE IC7432 1
3 EX-OR GATE IC7486 1
4 NOT GATE IC7404 1
5 4-BIT MAGNITUDE
COMPARATOR
IC7485 2
6 BREAD BOARD - 1
7 CONNECTING
WIRES
- FEW
8 IC TRAINER KIT - 1
-
THEORY:
2-BIT MAGNITUDE COMPARATOR;
The comparison of two numbers is an operation that determines if one number is
greater than, less than or equal to the other number. A Magnitude Comparator is a
combinational circuit that compares two numbers A & B and determines their relative
magnitudes. Depending upon the relative magnitudes, one of the outputs will be high.
The outcome of the comparison is specified by 3 binary variables that indicate
whether A>B, A=B or A<B.
IC 7485 (4-BIT MAGNITUDE COMPARATOR):
The IC7485 is a four-bit magnitude comparator .it can be used to compare 2 four
bit binary codes. These IC’s can be cascaded to compare words of utmost any length.
Its four bit inputs are weighted (A0-A3) and (B0-B3) where a3 and b3 are the most
significant bits.
The figure shows the logic symbol and pin diagram of IC7485.its operation is
described in functional table, showing all possible logic conditions. The 8-bit
comparator is implemented using two 7485 IC’s.
PROCEDURE For 2-Bit Magnitude Comparator:
1. Draw the truth table of the 2-bit magnitude comparator.
2. Determine the simplified expression for the output variable using K-Map.
3. Decide the corresponding logic gates to be used to implement the above
expression.
4. Draw the logic diagram according to output expression.
5. Construct the 2-bit magnitude comparator circuit using the above gates.
6. Verify the truth table.
BLOCK DIAGRAM OF 2-BIT MAGNITUDE COMPARATOR:
INPUT
A B
A>B A=B A<B
OUTPUTS
TRUTH TABLE: 2-BIT MAGNITUDE COMPARATOR
Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
K-MAP SIMPLIFICATION
K-Map For A > B:
K-Map For A = B:
K-Map For A < B:
Logic Diagram of 2-bit Magnitude Comparator
COMPARING
INPUTS
CASCADING INPUTS OUTPUTS
A B A>B A=B A<B A>B A=B A<B
A>B X X X 1 0 0
A=B 1 0 0 1 0 0
X 1 X 0 1 0
0 0 1 0 0 1
A<B X X X 0 0 1
RESULT:
Thus 2-bit magnitude comparator is designed and implemented using basic logic
gatesand their outputs are verified.
Viva Questions
1) What is a magnitude comparator2) Why comparison of numbers is necessary.
Exp.No: 9Date:
DESIGN AND IMPLEMENTATION OF EVEN AND ODD PARITY CHECKER/GENERATOR USING BASIC GATES
AIM:
To design and implement 3–bit even and odd parity checker and generator.
COMPONENTS REQUIRED:
S.No. Apparatus Specifications Quantity1. IC Trainer kit -- 1 no2. Logic gate IC’s IC 7486 1 no 5. Connecting wires -- 1 set
THEORY:A parity bit is used for the purpose of detecting errors during transmission of
binary information. A parity bit is an extra single bit included with a message. An error is detected if the checker parity does not correspond with the one transmitted. The parity which is transmitted along with the message is called generated parity bit. The parity, which is received, is called as checker parity bit.
The parity bit, P= X Y Z. The three message bits together with the parity bit are transmitted to the destination where they are applied to parity checker to check possible errors in transmission. The output of the parity checker should have even number of ones for accurate transmission. If an error is encountered, then it will have odd number of ones. The parity checker can be implemented with exclusive OR-gate.
C= (X Y) (Z P).PROCEDURE:
1. Draw the truth table of the even and odd parity generator/checker circuit.2. Determine the simplified expression for the output variable using K-Map.3. Decide the corresponding logic gates to be used to implement the above
expression.4. Draw the logic diagram according to output expression.5. Construct the even and odd parity generator/checker circuit using the above
gates.6. Verify the truth table.
EVEN PARITY GENERATOR: K-Map Simplification:
Truth Table
K-Map Simplification
Logic Diagram of even Parity Generator:
X Y Z P0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 01 1 0 01 1 1 1
0 1 0 1
1 0 1 0X
X
YZ Y Z Y Z YZXYZ
ODD PARITY GENERATOR: K-Map :Truth Table
K-Map Simplification
Logic Diagram of odd Parity Generator:
X Y Z P0 0 0 10 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0
1 0 1 0
0 1 0 1X
X
YZY Z Y Z YZXYZ
EVEN PARITY CHECKER: K-Map Simplification:
From K-Map :
Logic Diagram of even Parity Checker:
X Y Z P C0 0 0 0 00 0 0 1 10 0 1 0 10 0 1 1 00 1 0 0 10 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 11 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 01 1 0 1 11 1 1 0 11 1 1 1 0
0 1 0 1
1 0 1 0
0 1 0 1
1 0 1 0
XYZP
XY
XY
XY
XY
ZPZPZPZP
ODD PARITY CHECKER: K-Map Simplification:
From K-Map :
Logic Diagram of odd Parity Checker:
X Y Z P C0 0 0 0 00 0 0 1 10 0 1 0 10 0 1 1 00 1 0 0 10 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 11 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 01 1 0 1 11 1 1 0 11 1 1 1 0
1 0 1 0
0 1 0 1
1 0 1 0
0 1 0 1
XY
ZP
XY
XY
XY
XY
ZPZPZPZP
Truth table of 16 Bit Parity Generator :
Input OutputNo. of high
inputs in the bits I0 –I7
PE PO ∑E ∑O
Even 1 0 1 0Odd 1 0 0 1Even 0 1 0 1Odd 0 1 1 0
CIRCUIT DIAGRAM of 16 Bit Parity Generator
PIN DIAGRAM OF IC 74180
EI – Even Input OI – Odd Input Σe – Even parity output Σo – Odd parity output
RESULT:
Thus, 3-bit even/odd parity generator and checker was designed and implemented.
Viva Questions1. What is a Parity Generator?2. What is a Parity Checker?3. What is the use of parity checker?4. What are the advantages of Parity Generator and Checker?
Exp.No: 10Date:DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND
DE-MULTIPLEXER USING LOGIC GATES
Aim: To design and implement Multiplexer and Demultiplexer using logic gates.
Apparatus required:S.NO. COMPONENTS SPECIFICATION QUANTITY1. 3 input AND gate IC 7411 22. 4 input AND gate IC 7422 23. NOT gate IC 7404 14. OR gate IC 7432 15. IC trainer kit - 16. Bread board - 17. Connecting wires - Few
Theory:
Multiplexer:The term multiplexer means “many into one”. Multiplexing is the
process of transmitting a large number of information over a single line. A digital multiplexer (MUX) is a combinational circuit that selects one digital information from several sources and transmits the selected information on a single output line.Demultiplexer:
A demultiplexer is a circuit that receives information on a single line and transmits this information on one of the 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines. For eg., in a one to four demultiplexer a single input variable Din has a path to all four outputs, but the input information is directed to only one of the output lines.
Procedure:
1. Draw the function table of the 4: 1 Multiplexer and 1: 4 Demultiplexer circuit.2. Decide the corresponding logic gates to be used to implement the circuit.3. Draw the logic diagram according to function table.4. Construct the 4: 1 Multiplexer and 1: 4 Demultiplexer circuit using the above
gates.5. Verify the function table.
4 : 1 Multiplexer Block Diagram: Function Table:
Logic Diagram:
E S1 S0 Y
1 X X 0
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1: 4 Demultiplexer:Block Diagram: Function Table:
Logic Diagram:
E S1 S0 Din Y0 Y1 Y2 Y3
0 X X X 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0
1 0 1 0 0 0 0 0
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 0
1 1 1 1 0 0 0 1
PIN DIAGRAM OF 3-INPUT AND GATE
PIN DIAGRAM OF 4-INPUT AND GATE
Result:
Thus the design and implementation of multiplexer and demultiplexer were designed and implemented using logic gates and the multiplexer IC 74150 and demultiplexer IC 74154 were studied.
Exp.No: 11Date:
DESIGN AND IMPLEMENTATION OF BOOLEAN FUNCTION USING MULTIPLEXERS
Aim: To design and implement a Boolean function using Multiplexers.
(a) F = Σ m (1,3,5,6)(b)F = Σ m (0,1,3,4,8,9,15)
Apparatus required:S.NO. COMPONENTS SPECIFICATION QUANTITY1. 4:1 Multiplexer 12. 8:1 Multiplexer 13. NOT gate IC 7404 14. IC trainer kit - 15. Bread board - 16. Connecting wires - Few
Theory:Implemention of a Boolean Function Using Multiplexers
A multiplexer consists of a set of AND gates whose outputs are connected to single OR gate. Because of this construction any Boolean unction in a SOP form can be easily realized using multiplexer. Each AND gate in a multiplexer represents a minterm. By connecting the function variable directly to the select inputs, a multiplexer can be made to select the AND gate that corresponds to the minterm in the function. If a minterm exists in a function, we have to connect the AND gate data input to LOGIC 1; otherwise it is connected to LOGIC 0.
Deriving Multiplexer Inputs from the Implementation Table:1. If the two minterms in a column are not circled, 0 is applied to the
corresponding multiplexer input.2. If the two minterms in a column are circled, 1 is applied to the corresponding
multiplexer input.3. If the minterm the second row is circled, the minterm the first row is not
circled; A is applied to the corresponding multiplexer input.4. If the minterm the first row is circled, the minterm the second row is not
circled; A’ is applied to the corresponding multiplexer input.Procedure:
6. Draw the truth table for the given Boolean function.7. Decide the corresponding multiplexer to be used to implement the given
function.8. Derive the inputs for the multiplexer using the implementation table.9. Draw the logic diagram.10. Construct the Multiplexer implementation circuit 11. Verify the truth table.
a. F = Σ m (1,3,5,6)
Truth Table
Minterm A B C F0 0 0 0 01 0 0 1 12 0 1 0 03 0 1 1 14 1 0 0 05 1 0 1 16 1 1 0 17 1 1 1 0
Implementation Table:
Multiplexer Implementation Diagram:
b. F = Σ m (0,1,3,4,8,9,15)
Truth Table
Minterm A B C D F0 0 0 0 0 11 0 0 0 1 12 0 0 1 0 03 0 0 1 1 14 0 1 0 0 15 0 1 0 1 06 0 1 1 0 07 0 1 1 1 08 1 0 0 0 19 1 0 0 1 110 1 0 1 0 011 1 0 1 1 012 1 1 0 0 013 1 1 0 1 014 1 1 1 0 015 1 1 1 1 1
Implementation Table:
Multiplexer Implementation Diagram:
Result:Thus the given Boolean functions were designed and implemented using the multiplexers and the outputs were verified.
Exp.No: 12
Date:DESIGN AND IMPLEMENTATION OF ENCODER AND
DECODER USING LOGIC GATES
AIM:
To design and implement 3-8 Decoder and 8-3 Encoder using logic gates.
COMPONENTS REQUIRED:
S.No. Apparatus Specifications Quantity
1. IC Trainer kit -- 1 no
2. IC’s IC7408, IC7404, IC7432, IC7445,
IC74147
1 no
7. Connecting wires -- 1 set
THEORY:
Decoder:
A Decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.
The outputs are mutually exclusive because only one output can be equal to 1 at any one time. The output line whose value is equal to 1 represents the minterm equivalent of the binary number presently available in the input lines.Encoder:
An Encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n (or fewer) input lines and n output lines. The output lines generate the binary code corresponding to the input value.
The output activate conditions can be expressed by the following output boolean functions C = D1 + D3 + D5 + D7
B = D2 + D3 + D6 + D7
A = D4 + D5 + D6 + D7
If two or more inputs are activated in the same time then the output of the encoder is indeterminate. In such conditions a Priority Encoder is used in which the input having the highest priority will take precedence.
PROCEDURE:
1. Draw the truth table of the 3-8 Decoder and 8-3 Encoder circuit.2. Decide the corresponding logic gates to be used to implement the circuit.3. Draw the logic diagram according to truth table.4. Construct the 3-8 Decoder and 8-3 Encoder circuit using the above gates.5. Verify the truth table.
TRUTH TABLE OF 3-8 DECODER:
Input Output
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
3:8 DECODER
TRUTH TABLE OF 8-3 ENCODER:
Input Output
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
8:3 ENCODER
RESULT:Thus the decoder and encoder were implemented using logic gates and
their operations were verified.
Exp.No: 13.
Date:
CONSTRUCTION AND VERIFICATION OF 4 – BIT RIPPLE
COUNTER, MOD-10 COUNTERS USING JK FLIP-FLOP
AIM:To construct and verify 4–Bit Ripple Counter and MOD-10 Ripple Counter.
APPARATUS REQUIRED:S.NO COMPONENTS SPECIFICATION QUANTITY1 JK FLIPFLOP IC 7476 22 NAND GATE IC 7400 13 BREADBOARD - 14 IC TRAINER KIT - 15 CONNECTING
WIRES- FEW
THEORY:MSI counters come in two categories: Ripple Counters and Synchronous
Counters. In a Ripple counter, the flip-flop output transition serves as a source for triggering other flip-flops. In other words, the CP inputs of all flip-flops(except the first) are triggered not by the incoming pulses, but rather by the transition that occurs in other flip-flops. A Binary Ripple Counter consists of a series connection of complementing flip-flops (T or JK type), with the output of each flip-flop connected to the CP input of the next higher order flip-flop. The flip-flop holding the least significant bit receives the incoming count pulses.
The flip-flops change one at a time in rapid succession, and the signal propagates through the counter in a ripple fashion. Ripple counters are sometimes called as Asynchronous Counters.
In case of MOD-10 Ripple Counter the count sequence is 0-9 after which the counter resets to 0. In order to achieve this operation, the Clear input of the flip-flops is connected to appropriate flip-flop outputs which satisfy the Reset condition. For example, Since MOD-10 counter must reset after count sequence 9, the outputs QD
and QB (that correspond to 10102 = 1010) are connected to the NAND gate to achieve the reset conditions of the flip-flops.
PROCEDURE:
1. Draw the truth table of the 4-Bit and Mod 10 ripple counter.2. Decide the corresponding logic gates and the corresponding flip flops to be
used 3. Draw the logic diagram according to truth table.4. Construct the 4-Bit and Mod 10 ripple counter using the above gates and the
Flip-flops.5. Clear all the flip-flops6. Activate the preset enable input and notice the output varying from 0000 to
1111 for every clock pulse.
TRUTH TABLE 4-BIT RIPPLE COUNTER(MOD-16) :
QD QC QB QA QD+1 QC+1 QB+1 QA+1
0 0 0 0 1 1 1 10 0 0 1 0 0 0 00 0 1 0 0 0 0 10 0 1 1 0 0 1 00 1 0 0 0 0 1 10 1 0 1 0 1 0 00 1 1 0 0 1 0 10 1 1 1 0 1 1 01 0 0 0 0 1 1 11 0 0 1 1 0 0 01 0 1 0 1 0 0 11 0 1 1 1 0 1 01 1 0 0 1 0 1 11 1 0 1 1 1 0 01 1 1 0 1 1 0 11 1 1 1 1 1 1 0
TRUTH TABLE MOD-10 RIPPLE COUNTER :
QD QC QB QA QD+1 QC+1 QB+1 QA+1
0 0 0 0 0 0 0 10 0 0 1 0 0 1 00 0 1 0 0 0 1 10 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 0 1 1 10 1 1 1 1 0 0 01 0 0 0 1 0 0 11 0 0 1 0 0 0 0
Pin Diagram of IC 7476(J-K Flip-Flop)
RESULT: Thus the 4–Bit Ripple counter and MOD-10 Ripple Counter was constructed and output was verified.
Viva Questions
1) What is a ripple counter2) Give the truth table of J-K Flip-flop.3) What is meant by edge triggered flip-flop4) Design a 4-bit ripple counter using T Flip-flop5) Name the two problems that may arise in ripple counter6) Draw the MOD-8 ripple counter using J-K Flip-flop and give the
timing diagram7) Design a ripple counter for MOD-5 count up operation
Exp.No: 15Date:
CODING OF COMBINATIONAL CIRCUITS USING HDL
AIM: To code combinational circuits using hardware description language (verilog HDL) and verify it through simulation.
REQUIREMENT: HDL software (model sim)
THEORY: A hardware description language describes the hardware of digital systems in a textual form. It resembles a programming language, but is specifically oriented towards describing hardware structures and behaviour. It can be used to represent logic diagrams, Boolean expressions and other more complex digital circuits. The language content can be stored and retrieved easily and processed by computer software in an efficient manner. There are two steps in HDL processing.
1) Simulation.2) Synthesis.
1.SIMULATION: Logic simulation is the representation of the structure and behaviour of a digital logic system through the use of computer. A simulator interprets the HDL description and produces readable output such as a timing diagram that predicts how the hardware will behave before it is actually fabricated. Simulation allows the detection of functional errors in a design without having to physically create the circuit. The stimulus the tests the functionality of the design is called” Test bench”.
2.SYNTHESIS:Logic synthesis is the process of deriving a list of components and their
interconnection from the model of a digital system described by HDL. The gate level net list can be used to fabricate an integrated circuit or to layout a printed circuit board. Logic synthesis is similar to compiling a program in a conventional high-level language.
ALGORITHM:
1.Start the module.2.Define the inputs and outputs.3.Define registers.4.Define signals 5.Write the procedural assignment for the combinational logic circuit(adder)6.End module
PROCEDURE
1.Create a project2.Create a file in Verilog HDL by writing the procedural assignment for the required
circuit3.Write a test bench file.
4.Add these two files to the project.5.Compile the project.6.Simulate the project.7.Get the waveform and verify the result.
HDL coding
1.Half Adder module half-adder(s,c,x,y) input x,y ; output s,c; xor g1(s,x,y) ; and g2(c,x,y) ; endmodule
2. Full Adder: module full-adder (s,c,x,y,z) input x,y,z; output s,c; wire s1,d1,d2;
half-add Ha1(s1,d1,x,y),Ha2(s,d2,s1,z)
or g3(c,d1,d2) end module
3. Four Bit Binary adder:
module four-bit-add (sum,c4,A,B,c0) input [3:0] A,B;
input c0; output [3:0] sum; output c4; wire c1,c2,c3, c4; full-add FA0(sum[0],c1,A[0],B[0],c0) FA1(sum[1],c2,A[1],B[1],c1)
FA2(sum[2],c3,A[2],B[2],c2) FA3(sum[3],c4,A[3],B[3],c3)
end module
HDL CODING
// JK FF (JK FLIP FLOP)
module JK_FF (J, K, CLK, Q, Qnot)
output Q,Qnot;
input J,K,clk;
reg Q;
assign Qnot=NQ;
always @(posedge clk)
case ({J, K})
2’b00:Q=Q;
2’b01:Q=1’b0;
2’b10:Q=1’b1;
2’b11:Q=NQ;
end case
end module
// D_FF (D flip flop)
module D_FF (D, clk, Q)
input D, clk;
output Q;
reg Q;
always @ (posedge clk)
Q=D;
end module
Result
Thus the HDL coding for the combinational circuits half adder, full adder and four bit binary adder were written and verified through stimulation using Verilog HDL
Ex. No: 16 Date:
Design Of Sequential Logic Circuits For An Arbitrary
Sequence
Aim:
To design the sequential logic circuits which will count through the
Sequence 0,1,3,5,7 using T flip-flops.
Equipments and components required:
1.Digital IC trainer kit
2. T flip flop
3. Power supply
4. Bread board
Theory:
A sequential circuit consists of a combinational logic block along with memory
elements, which will temporarily store the outputs and feed them back to the circuit as
inputs for the next stage synchronous sequential circuit. Use clock signal to control
the operation in stages.
A sequential circuit can be Moore type where the output depends only on the state
of the circuit or Mealy type where the output depends on the circuit state and primary
inputs. Sequential circuits are also called finite state machine (FSMs).
Procedure:
1. Design the circuit by forming the state table, then the excitation table for T-flip
flop and finally the simplified expression for the T input.
2. Connect the circuit and switch on the power supply and clock input.
3. Observe the sequence (Ta Tb Tc) and verify it against the given sequence.
Result:
Thus the sequential circuit has been designed using T flip-flops for the given
arbitrary sequence.
Exp.No:Date:
STUDY OF MULTIPLEXER IC74150 AND DEMULTIPLEXER IC74154
Aim: To study the multiplexer IC74150, and the demultiplexer IC74154.
Components Required: Digital trainer kit, IC74150, Connecting wires IC74154
Theory:
Multiplexer:
The term multiplex means “Many into one”. Multiplexing is the process of transmitting a large number of information over a single line. A digital multiplex (MUX)is the combinational circuit that selects one digital information from several sources and transmits the selected information on a single output line.A multiplexer is also called a data selector since it selects one of many and sends the information to the output.
Demultiplexer:
A one to four demultiplexer, has a single input(D) from output (y0 to y3) and two selected inputs (S1 and S0). The truth table of 1:4 Demux is shown. The data input is connected to output y0. When S1=0 and S0=0 and the data input is connected to output y1 when S1 = 0 and S0= 0Similarly the data input is connected to output y2 and y3 when S1=1 and S0=0 and when S1=0 and S0=1 respectively.
Procedure:
1. The IC is connected to the bread board in digital trainer Kit.2. Give the possible inputs to the input pins in the IC.3. Connect the output pins to the LED output through connecting wires 4. Check the outputs with the truth table for all possible combinations of input.
Result:
Thus the operation of the multiplexer IC74150 and Demultiplexer IC74154 are studied.
Viva Questions
1) What is a multiplexer2) What is a demultiplexer3) What are the leads present in a multiplexer4) What is the function of the strobe in a multiplexer 5) Give the other names for multiplexer and demultiplexer6) What is the function of enable input in multiplexer7) Why multiplexer is called as data selector8) Give the other names for multiplexer and demultiplexer9) What is the function of enable input in multiplexer10) Why multiplexer is called as data selector11) Realize OR function using 2:1 multiplexer12) Implement a 16: 1 multiplexer using two 8:1 multiplexer13) Implement 2 input NAND gate ,And gate using 2:1 multiplexer14) State some major applications of multiplexer15) What is the Difference between a multiplexer and a demultiplexer16) What is the number of control lines required for 1:8 demultiplexer17) State the uses and the major applications of demultiplexer
Exp.No:Date:
STUDY OF ENCODER IC 74145 AND DECODER IC74147
Aim: To study the Encoder IC 74145 and Decoder IC 74147.
Components Required: Digital trainer kit, IC 74145, IC 74147,Connecting wires .
Theory:
Decoder:
A Decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.
The outputs are mutually exclusive because only one output can be equal to 1 at any one time. The output line whose value is equal to 1 represents the minterm equivalent of the binary number presently available in the input lines.Encoder:
An Encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n (or fewer) input lines and n output lines. The output lines generate the binary code corresponding to the input value.
The output activate conditions can be expressed by the following output boolean functions C = D1 + D3 + D5 + D7
B = D2 + D3 + D6 + D7
A = D4 + D5 + D6 + D7
If two or more inputs are activated in the same time then the output of the encoder is indeterminate. In such conditions a Priority Encoder is used in which the input having the highest priority will take precedence.
Procedure:
1. The IC is connected to the bread board in digital trainer Kit.
2. Give the possible inputs to the input pins in the IC.
3. Connect the output pins to the LED output through connecting wires
4. Check the outputs with the truth table for all possible combinations of input.
Result:
Thus the operation of the Encoder IC 74145 and Decoder IC 74147 are studied.
Viva Questions
1) What do you mean by encoder2) Implement the following function using 3:8 decoder
F(A, B, C) = Σ m(0,1,4,5,7)3) What do you mean by decoder.4) What is the difference between encoder and decoder.5) Design the full adder circuit using decoder6) Can a decode function as a demultiplexer7) Construct 4 X 16 decoder with 3 X 8 decoders8) Distinguish between decoder and demultiplexer