designing soc/fpga with srio interface · 2020. 6. 12. · the mobiveil team • leadership –...
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Designing SOC/FPGA with SRIO Interface
“The IP enabled solutions provider”
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AGENDA
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
11/7/2013 2013 Copyright Mobiveil Inc. 2
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The Mobiveil Team • Leadership
– Management with 25+ years experience in Semiconductor/Silicon IP/Systems software
– Previously founded GDA Technologies, Inc and grew to strong IP and Services group , 500+ engineers strong.
– Working on SRIO IP & Solutions since 2003 Key differentiators
Developed several key high speed serial interconnect IP blocks in the last 10+ years (PCI Express, Hyper Transport, Serial RapidIO, SPI4.2, DDR4/3,Flash Controllers etc) Platforms/ Solutions approach to services Dependable scale and breadth Alliances, Industry affiliations and partnerships
Locations
Headquarters in Milpitas, CA India design centers: Chennai & Bangalore
Agenda 11/7/2013 2013 Copyright Mobiveil Inc. 3
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
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Configurable & Feature Rich
Agenda 11/7/2013 2013 Copyright Mobiveil Inc. 4
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
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Mobiveil Digital Controllers
VIP Integration
• Exhaustively verified with many BFM/VIP
• Mobiveil provides Verification Test bench based on Customer VIP Speeds up Chip
level verification All VIP
Integration and setup issues are resolved upfront
© Mobiveil, Inc- Confidential
RTA BFM
Internal BFM
Company Overview
Silicon IP Expertise
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Mobiveil IP Advantages
Market leading & most exhaustively proven cores in the market: Industry leaders are using these cores
Consortium Participation : RIO – Member, PCISIG –
Member, HMC – Member, NVM Express - Member Superior Technical Solution: Most Feature rich IP,
Complete Customization and delivery Solution Support: Clear IP Focus & Worldwide Support 3rd Party Partnerships for complete Solution:
(Verification and PHY IPs) Standard Body Certified Cores: All Mobiveil IPs are
validated and certified: PCI Plug fest, UNH, RTA
Agenda 11/7/2013 2013 Copyright Mobiveil Inc. 6
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
![Page 7: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/7.jpg)
RTL IP Portfolio IP Family Product Platinum
(Proven in Silicon
Gold (Proven in
FPGA)
Under Development
PCI Express Gen1 Y Y
Gen2 Y Y
Gen3 Y Y
Switch Y Y
SRIO Gen1 Y Y
Gen2 Y Y
Gen3 Y
Ethernet 1G Y Y
10G & HiGig
Y Y
Agenda 11/7/2013 2013 Copyright Mobiveil Inc. 7
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
![Page 8: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/8.jpg)
RTL IP Portfolio
Agenda 11/7/2013 2013 Copyright Mobiveil Inc. 8
IP Family
Platinum (Proven in
Silicon)
Gold (Proven in
FPGA)
Under Development
DDR4/3 Y
Flash Controller
Y
eSDHC Y
SPI4.2 Y Y
LPDDR3/2 Y
NVM Express Y
mPCIe/ HMC Y
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
![Page 9: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/9.jpg)
Generic RapidIO Controller (GRIO)
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GRIO Architecture
© Mobiveil, Inc- Confidential 10
Logical Config Reg
R
IO IN
TERF
ACE
PBUS INTERFACE
USE
R L
OGI
C IN
TERF
ACE
Physical Inbound Protocol
Physical
Outbound Protocol
Logical & Transport Layer Physical Layer
PHY PMA Inbound (III PARTY)
PCS
PHY
Inbound
User Logic Outbound Controller
User Logic Inbound
Controller
PBUS CONTROLLER
Physical Config. Reg
PHY PMA Outbound (III PARTY)
PHY
PCS
Outbound
Logical Inbound
Protocol
DPRA
M
Logical Outbound
Protocol
DPRA
M
III PARTY BLOCK
Highly Configurable
Technology Independent
System Validated
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
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Highlights
• Silicon IP used by many leading edge Base station Processors and ASICs
• Leverages Mobiveil’s high speed IO design expertise and market leadership
• Supports all PHY specifications and data rates • Interoperability tested against the RTA BFM
and test suites • System validation on FPGA platform • High performance, low gate count, low latency
solution • Targets both FPGA and ASIC technologies • Support for mainstream technologies, tools
and flows • Highly configurable design to optimize
implementations
© Mobiveil, Inc- Confidential 11
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
Highly Configurable
Technology Independent
System Validated
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Logical and Transport Layer
Physical Layer
sRIO SERDES Interface
AXI Bridge (PIO, DMA, DME, DS)
AXI Interface
GRIO
RapidIO to AXI Bridge (RAB)
© Mobiveil, Inc- Confidential
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
Highly Configurable
Technology Independent
System Validated
![Page 13: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/13.jpg)
RapidIO Plan
© Mobiveil, Inc- Confidential 13
• Mobiveil is working on 10xN (Gen3.0) Implementation • Added support for 10.3125 GBPS Baud rate • Use of 64/67b encode/decode as opposed to
8b/10b for Gen1/Gen2. Providing significant jump in data rate as overhead is much less compare to Gen1/Gen2.
• Maintains backward compatibility for upper layers (Transport and logical layers).
• Mobiveil is part of Part S and NGSIS task force
defining Next Generation Space Interconnect • Enhancements needed for Longer cable
length • Enhancements needed for Error
Management and reliability • Enhancement needed for possible Non-
posted Multicasting
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
Highly Configurable
Technology Independent
System Validated
![Page 14: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/14.jpg)
GRIO+RAB Test bench View
14
GRIO + RAB (DUT)
RIO Driver
APB Monitor
AXI Slave
Driver
RIO Auto Responder
RIO Module
APB Driver
AXI Master Driver
AXI Monitor
AXI Slave
Responder
AXI Interface Driver
REQ
Request
RIO Bus checker
RESP
(Requests) Mem,MSG Doorbell Maintenance Response
Monitors Requests Responses Maintenance Pkts
Response Validation
End2End Data Check
Log Message for Unexpected System Behavior End2End Checker
STIMULUS GENERATOR
Company Overview
Silicon IP Expertise
![Page 15: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/15.jpg)
RapidIO 10xN VIP Offering
• UVM based environment • Extensive Compliance Test Suite • Simplified Verification Flow and corresponding
reduction in Chip Level Verification Effort • Coverage Driven Constrained Random
Verification • Multiple levels of Verbosity for Easy Debug • Comprehensive Traffic Tracking and Report
Generation (Packet and Symbol level) • Score Board • Functional Coverage • Protocol Monitor
15
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
![Page 16: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/16.jpg)
ASIC Design Services
ASIC Services Offered – ASIC/SoC design and verification – block level and
chip level – FPGA prototyping – FPGA Validation
Resource Augmentation – Skilled resources with design, verification and
validation with varied domain expertise – Resource deployment for short term/ long term in
APAC, Europe, North America Offshore Development Center
– All round in house expertise (HW, SW) to independently manage design or verification effort
– Ability to quickly ramp up and provide a minimum risk execution model
11/7/2013 2013 Copyright Mobiveil Inc. 16 Agenda
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
![Page 17: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/17.jpg)
P3041 AMC Card Features: • Single Width AMC card | Upto 4GB on-board DDR3 SDRAM • Two Ethernet Interface in Face Plate | Optional GPS clock • Dual SATA 2.0 Interface | Linux Operating System • Virtual COM port for Debug | IPMI support for MMC – Pigeon
Point • sRIO and PCIe interfaces to backplane | Two CIPRI Interface in
Face Plate • Support Mezzanine Card interface with sRIO and CPRI interface
for Baseband expansion
Agenda 11/7/2013 2013 Copyright Mobiveil Inc. 17
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
![Page 18: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/18.jpg)
SRIO Services Offering
11/7/2013 2013 Copyright Mobiveil Inc. 18
• Team in Mobiveil has Expertise in building AMC boards for Wireless Base Stations with SRIO interconnects – P3041 Freescale Board with sRIO for DSP expansion – P2020 with MSC8156 add on board with sRIO Switch – Developed Faraday based DSP boards – MPC8540/MPC8560 based AMC board – MSC8122 and MSC7119 Freescale DSP for Voice
Encoding • Software
– Modified open Source driver to integrate the SRIO configuration between Processor and DSP
– Worked on Smart DSP OS (SDOS) from Freescale – Worked on Remote DMA and sRIO boot in
MPC8540/8560 – Provide Loopback function for Manufacturing diagnostics – 8122/7119 DSP configured for data movement using
sRIO for Voice encoding in GSM base station
Agenda
Company Overview
Silicon IP Expertise
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
![Page 19: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/19.jpg)
SRIO Services Offering
11/7/2013 2013 Copyright Mobiveil Inc. 19 Agenda
Company Overview
Silicon IP Expertise
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
• SRIO Switching hub using IDT chipset • Processing card with SRIO backplane
(x86/ARM) • Wireless Base station in AMC form
factor • Video Solutions with DSP form with
Codec supports for Broadcast Segment
• FPGA based SRIO solutions for custom requirements
• Form factor – ATCA/AMC form factors
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IP Enabled Solutions Provider
6/1/2012 © Mobiveil, Inc - Confidential 20
Protocol Engineer
ing
Test/ validation
SRIO RTL IP
BSP/Firmware
HW Design
SOC Design
Company Overview
Silicon IP Expertise
SRIO IP & VIP Offering
Services Offering
Summary
![Page 21: Designing SOC/FPGA with SRIO Interface · 2020. 6. 12. · The Mobiveil Team • Leadership – Management with 25+ years experience in Semiconductor/Silicon IP/Systems software –](https://reader033.vdocuments.us/reader033/viewer/2022060823/609d2b5f191caa73c21f1082/html5/thumbnails/21.jpg)
MILPITAS : 920, Hillview Court, Suite 250, Milpitas, CA 95035 Ph: 408-230-9971 Email: [email protected]
www.mobiveil.com | [email protected]
11/7/2013 2013 Copyright Mobiveil Inc. 21