designing sequential logic circuits ilam university
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Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits
Ilam university
Sequential LogicSequential Logic
COMBINATIONALLOGIC
Registers
Outputs
Next state
CLK
Q D
Current State
Inputs
Naming ConventionsNaming Conventions
In our text: a latch is level sensitive a register is edge-triggered
There are many different naming conventions For instance, many books call edge-
triggered elements flip-flops This leads to confusion however
Latch versus RegisterLatch versus Register Latch
stores data when clock is high
D
Clk
Q D
Clk
Q
Register
stores data when clock rises
Clk Clk
D D
Q Q
LatchesLatches
In
clk
In
Out
Positive Latch
CLK
DG
Q
Out
Outstable
Outfollows In
In
clk
In
Out
Negative Latch
CLK
DG
Q
Out
Outstable
Outfollows In
Timing DefinitionsTiming Definitions
t
CLK
t
D
tc 2 q
tholdtsu
t
Q DATASTABLE
DATASTABLE
Register
CLK
D Q
Characterizing TimingCharacterizing Timing
Clk
D Q
tC 2 Q
Clk
D Q
tC 2 Q
tD 2 Q
Register Latch
Storage MechanismsStorage Mechanisms
Positive Feedback: Bi-StabilityPositive Feedback: Bi-StabilityVi1 Vo2
Vo2 =Vi1
Vo1 =Vi2
Vi1
A
C
B
Vo2
Vi1=Vo2
Vo1 Vi2
Vi2=Vo1
Meta-StabilityMeta-Stability
Gain should be larger than 1 in the transition region
A
C
d
B
Vi2
5V
o1
Vi1 5Vo2
A
C
d
B
Vi2
5V
o1
Vi1 5Vo2
Writing into a Static LatchWriting into a Static Latch
CLK
CLK
CLK
D
Q D
CLK
CLK
D
Converting into a MUXForcing the state(can implement as NMOS-only)
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
Mux-Based LatchesMux-Based LatchesNegative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
CLK
1
0D
Q 0
CLK
1D
Q
InClkQClkQ InClkQClkQ
Mux-Based LatchMux-Based Latch
CLK
CLK
CLK
D
Q
Mux-Based LatchMux-Based Latch
CLK
CLK
CLK
CLK
QM
QM
NMOS only Non-overlapping clocks
Master-Slave (Edge-Triggered) Master-Slave (Edge-Triggered) RegisterRegister
1
0D
CLK
QM
Master
0
1
CLK
Q
Slave
QM
Q
D
Two opposite latches trigger on edgeAlso called master-slave latch pair
Master-Slave RegisterMaster-Slave Register
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
Multiplexer-based latch pair
Clk-Q DelayClk-Q Delay
Setup TimeSetup Time
D
Q
QM
CLK
I2 2 T2
2 0.5
Volt
s
0.0
0.2 0.4time (nsec)
(a) Tsetup5 0.21 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
DQ
QM
CLK
I2 2 T2
2 0.5V
olt
s
0.0
0.2 0.4time (nsec)
(b) Tsetup5 0.20 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
Reduced Clock Load Reduced Clock Load Master-Slave RegisterMaster-Slave Register
D QT1 I1
CLK
CLK
T2
CLK
CLKI2
I3
I4
Latch-Based DesignLatch-Based Design
• N latch is transparentwhen = 0
• P latch is transparent when = 1
NLatch
Logic
Logic
PLatch
Maximum Clock FrequencyMaximum Clock Frequency
Avoiding Clock OverlapAvoiding Clock OverlapCLK
CLK
A
B
(a) Schematic diagram
(b) Overlapping clock pairs
X
D
Q
CLK
CLK
CLK
CLK
Overpowering the Feedback Loop ─Overpowering the Feedback Loop ─Cross-Coupled PairsCross-Coupled Pairs
Forbidden State
S
S
R
Q
QRS Q
Q00 Q
101 0
010 1
011 0RQ
NOR-based set-reset
Cross-Coupled NANDCross-Coupled NAND
S
QR
Q
M1
M2
M3
M4
Q
M5S
M6CLK
M7 R
M8 CLK
VDD
Q
Cross-coupled NANDsAdded clock
This is not used in datapaths any more,but is a basic building memory cell
Sizing IssuesSizing Issues
Output voltage dependence on transistor width
Transient response
4.03.53.0W/L5 and 6
(a)
2.52.00.0
0.5
1.0
1.5
2.0
Q (
Vo
lts)
time (ns)
(b)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20
1
2
W = 1 m
3
Vo
lts
Q S
W = 0.9 m
W = 0.8 m
W = 0.7 mW = 0.6 m
W = 0.5 m
Storage MechanismsStorage Mechanisms
D
CLK
CLK
Q
Dynamic (charge-based)
CLK
CLK
CLK
D
Q
Static
Making a Dynamic Latch Pseudo-StaticMaking a Dynamic Latch Pseudo-Static
D
CLK
CLK
D
More Precise Setup TimeMore Precise Setup Time
tD 2 C
t
t
t
tC 2 Q1.05tC 2 Q
tSu
tH
Clk
D
Q
Clk-Q Delay
TSetup-1
TClk-Q
Time
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
ClockDataTSetup-1
Clk-Q Delay
TSetup-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
ClockDataTSetup-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
Clk-Q Delay
TSetup-1
TClk-Q
Time
Timet=0
ClockDataTSetup-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Clk-Q Delay
TSetup-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
ClockDataTSetup-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
Timet=0
ClockDataTSetup-1
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
Clk-Q Delay
TSetup-1
TClk-Q
Time
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
DataClockTHold-1
0
Clk-Q Delay
THold-1
TClk-Q
Time
Clk-Q Delay
THold-1
TClk-Q
Time
Timet=0
DataClockTHold-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
0
Clk-Q Delay
THold-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
DataClockTHold-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
0
Clk-Q Delay
THold-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
Clock
THold-1
Data
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
0
Clk-Q Delay
THold-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
Clock
THold-1
Data
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
0