Design, Verification, and Test of Design, Verification, and Test of True Single-Phase Adiabatic MultiplierTrue Single-Phase Adiabatic Multiplier

Suhwan KimSuhwan KimIBM Research DivisionIBM Research Division

T. J. Watson Research Center, Yorktown HeightsT. J. Watson Research Center, Yorktown Heights

Conrad H. Ziesler and Marios C. PapaefthymiouConrad H. Ziesler and Marios C. PapaefthymiouElectrical Engineering and Computer ScienceElectrical Engineering and Computer Science

University of Michigan, Ann ArborUniversity of Michigan, Ann Arbor

Adiabatic Charging of an RC TreeAdiabatic Charging of an RC Tree

Charge and discharge load capacitance slowly to maintain small Charge and discharge load capacitance slowly to maintain small voltage drop across MOS switches and recycle energy stored in load voltage drop across MOS switches and recycle energy stored in load capacitance.capacitance.

Adiabatic Logic FamiliesAdiabatic Logic Families

Various adiabatic logic families,including 2N-2P, Pass-Transistor Various adiabatic logic families,including 2N-2P, Pass-Transistor Aiabdatic Logic (PAL), and Clocked CMOS Adiabatic Logic (CAL), Aiabdatic Logic (PAL), and Clocked CMOS Adiabatic Logic (CAL), have been proposed.have been proposed.

True Single-Phase Energy-Recovery Logic (TSEL) is the first-ever True Single-Phase Energy-Recovery Logic (TSEL) is the first-ever true single-phase adiabatic logic family. [Suhwan Kim and Marios.C. true single-phase adiabatic logic family. [Suhwan Kim and Marios.C. Papaefthymiou, Papaefthymiou, ISLPED’98ISLPED’98].].

Source-Coupled Adiabatic Logic (SCAL) is an enhancement of TSEL Source-Coupled Adiabatic Logic (SCAL) is an enhancement of TSEL with improved scalability and energy efficiency across a broad range with improved scalability and energy efficiency across a broad range of operating frequencies. [Suhwan Kim and Marios. C. of operating frequencies. [Suhwan Kim and Marios. C. Papaefthymiou, Papaefthymiou, ISLPED’99ISLPED’99].].

SCAL-D: Source-Coupled Adiabatic Logic with SCAL-D: Source-Coupled Adiabatic Logic with Diode-Connected TransistorsDiode-Connected Transistors

Basic characteristics of SCAL-D are the same as with SCAL/TSEL.Basic characteristics of SCAL-D are the same as with SCAL/TSEL.single-phase AC power-clock operationsingle-phase AC power-clock operationsimple AC power-clock generatorsimple AC power-clock generatorsimple to cascadesimple to cascade

Individually tunable current source attached to each gate.Individually tunable current source attached to each gate.broad range of operating frequencies with minimum-size transistorsbroad range of operating frequencies with minimum-size transistors

Diode-connected transistors used to improve performance. Diode-connected transistors used to improve performance.

PMOS Logic Structure in SCAL-DPMOS Logic Structure in SCAL-D

Each logic gate comprises a pair of cross-coupled transistors, diode-Each logic gate comprises a pair of cross-coupled transistors, diode-connected transistors, current control switches, a pull-up evaluation connected transistors, current control switches, a pull-up evaluation tree, and a tunable current source. tree, and a tunable current source.

Operation of PMOS Logic in SCAL-DOperation of PMOS Logic in SCAL-D

NMOS Logic Structure in SCAL-DNMOS Logic Structure in SCAL-D

Basic structure is the same as in PMOS SCAL-D, with NMOS Basic structure is the same as in PMOS SCAL-D, with NMOS devices replaced by PMOS devicesdevices replaced by PMOS devices

Cascading of SCAL-D LogicCascading of SCAL-D Logic

Energy consumption is minimized Energy consumption is minimized by individually setting the W/L by individually setting the W/L ratio of each current source and globally setting the biasing voltagesratio of each current source and globally setting the biasing voltages equal to the minimum possible value. This value depends on the equal to the minimum possible value. This value depends on the gate’s output load and speed requirement. gate’s output load and speed requirement.

Voltages of Output Nodes inVoltages of Output Nodes inCascaded SCAL-DCascaded SCAL-D

8-bit Multiplier and BIST Logic in SCAL-D 8-bit Multiplier and BIST Logic in SCAL-D

Schematic Diagram of Schematic Diagram of Full-Adder Multiplier Cell in SCAL-DFull-Adder Multiplier Cell in SCAL-D

Full-Custom Layout of Full-Custom Layout of Full-Adder Multiplier Cell in SCAL-DFull-Adder Multiplier Cell in SCAL-D

1-bit full adder buffer

buffer and

Full-Custom Layout of Full-Custom Layout of 8-bit Multiplier and BIST Logic in SCAL-D8-bit Multiplier and BIST Logic in SCAL-D

8-bit multiplier

BILBO 2

BILBO 1

self-testcontroller

Transistor Count and Area ofTransistor Count and Area of8-bit Multiplier and BIST Logic in SCAL-D 8-bit Multiplier and BIST Logic in SCAL-D

Transistor Count

11,854

Area

0.710mm^2

Built-in self-test logic 8-bit multiplier

Evaluation with Voltage ScalingEvaluation with Voltage Scaling

In HSPICE simulations, our SCAL-D 8-bit multiplier and BIST logic In HSPICE simulations, our SCAL-D 8-bit multiplier and BIST logic outperformed corresponding static CMOS designs that were outperformed corresponding static CMOS designs that were operating with supply voltages scaled for minimum energy operating with supply voltages scaled for minimum energy dissipation.dissipation.

Design Verification of Design Verification of 8-bit Multiplier and BIST Logic in SCAL-D8-bit Multiplier and BIST Logic in SCAL-D

The results of HSPICE simulation were compared directly against The results of HSPICE simulation were compared directly against the corresponding results of Verilog-HDL simulation using CAD tools the corresponding results of Verilog-HDL simulation using CAD tools we developed.we developed.

power-clock

BILBO control signals s1,s2

output sequence ixof BILBO 1

output sequence oxof BILBO 2

Floor-plan of Test-ChipFloor-plan of Test-Chip

Two identical multipliers with associated BIST logic, an internal Two identical multipliers with associated BIST logic, an internal power-clock generator, adiabatic-to-digital converters, and pads power-clock generator, adiabatic-to-digital converters, and pads were included.were included.

Die Photograph of Test-ChipDie Photograph of Test-Chip

Fully custom design0.5um n-well CMOS processDIP40 package4.83mm^2130 MHz operation with 3.0V

Experimental Setup Experimental Setup

digital digital oscilloscopeoscilloscope(TDS754D)(TDS754D)

signal generator(HP8647A)

test-board

DC power supply

digitalmulti-meters

Test-Board Test-Board

test-chip

switches for input signals

variable resistorsto control PMOS and NMOS

biasing voltages

connector forexternal power-clock

Functional Test in Self-Test Mode:Functional Test in Self-Test Mode:50MHz/3.0V50MHz/3.0V

power-clock

BILBO control signals s2

output sequence ixof BILBO 1

output sequence oxof BILBO 2

power-clock

BILBO control signals s2

output sequence ixof BILBO 1

output sequence oxof BILBO 2

Functional Test in Self-Test Mode:Functional Test in Self-Test Mode:130MHz/3.0V130MHz/3.0V

Energy Measurement ProceduresEnergy Measurement Procedures

chip power supply

Ndt

IV

IV

iv

VIIVI

ETN

0

)(

)(

)(

2/)(2/(

BNBN

BPBP

PCPC

ddPCVDDddVDD

cycle

Measured Energy Consumption ofMeasured Energy Consumption of8-bit Multiplier and BIST Logic in SCAL-D8-bit Multiplier and BIST Logic in SCAL-D

Energy consumption in the 8-bit multiplier and BIST logic, Energy consumption in the 8-bit multiplier and BIST logic, implemented entirely using SCAL-D, for various PMOS and NMOS implemented entirely using SCAL-D, for various PMOS and NMOS biasing voltages at the operating frequency range of 40-130 MHz.biasing voltages at the operating frequency range of 40-130 MHz.

Relative Difference of Energy Consumption Relative Difference of Energy Consumption Between TDS754D and HSPICEBetween TDS754D and HSPICE

Measured energy consumption of SCAL-D circuits correlates well Measured energy consumption of SCAL-D circuits correlates well with HSPICE simulation results for the same operating frequencies, with HSPICE simulation results for the same operating frequencies, amplitude of AC power-clock, DC supply voltage, and PMOS and amplitude of AC power-clock, DC supply voltage, and PMOS and NMOS biasing voltages. NMOS biasing voltages.

Measured Waveforms of Test-Chip Measured Waveforms of Test-Chip Operated in BIST Mode - 130MHz/3.0VOperated in BIST Mode - 130MHz/3.0V

power-clock

BILBO control signals s2

output sequence ixof BILBO 1

output sequence oxof BILBO 2

SummarySummary

True single-phase source-coupled adiabatic logic familyTrue single-phase source-coupled adiabatic logic family

Lower energy dissipation than static CMOS across broad range of Lower energy dissipation than static CMOS across broad range of operating frequencies.operating frequencies.

To demonstrate practicality of our single-phase adiabatic logic, we To demonstrate practicality of our single-phase adiabatic logic, we designed an 8-bit adiabatic multiplier in 0.5um standard CMOS designed an 8-bit adiabatic multiplier in 0.5um standard CMOS process.process.

The 8-bit adiabatic multiplier and BIST logic was verified, fabricated, The 8-bit adiabatic multiplier and BIST logic was verified, fabricated, tested, and measured up to 130 MHz.tested, and measured up to 130 MHz.