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DESIGN GUIDE
Carrier Board for SOM-6X80 Module
1.00-08222018-183700
Copyright
Copyright ©2018 VIA Technologies Incorporated. All rights reserved.
No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies, Incorporated.
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Disclaimer
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided in this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no responsibility for the use or misuse of the information (including use or connection of extra device/equipment/add-on card) in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.
VIA Technologies, Inc. reserves the right the make changes to the products described in this manual at any time without prior notice.
Carrier Board Design Guide for SOM-6X80 Module
Revision History
Revision Date Description1.00 08/22/2018 Initial release
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Carrier Board Design Guide for SOM-6X80 Module
Table of Contents
1. Introduction ....................................................................................................................... 11.1 Document Overview ............................................................................................................................. 11.2 Acronyms Used ..................................................................................................................................... 21.3 SchematicConventions ........................................................................................................................ 3
2. GeneralCarrierBoardRecommendations ........................................................................ 42.1 PCB Stackup .......................................................................................................................................... 4
2.1.1 4-Layer PCB Stackup Example ........................................................................................................ 52.1.2 4-Layer PCB Impedance Control .................................................................................................... 5
2.2 GeneralLayoutandRoutingGuidelines ............................................................................................... 62.2.1 RoutingStylesandTopology .......................................................................................................... 62.2.2 GeneralTraceAttributeRecommendation .................................................................................... 72.2.3 GeneralClockRoutingConsiderations ........................................................................................... 8
3. SOM-6X80ModuleandSOMDDR3SODIMMSlotSpecificationOverview ....................... 93.1 SOM-6X80 Module Placement ............................................................................................................ 93.2 SOM-6X80ModuleMechanicalCharacteristics ................................................................................... 93.3 SOM-6X80 Module and Carrier Board Dimensions ............................................................................ 103.4 SOM DDR3 SODIMM Slot ................................................................................................................... 11
3.4.1 SOM DDR3 SODIMM Slot Dimensions ........................................................................................ 113.4.2 SOM DDR3 SODIMM Slot Footprint ............................................................................................. 12
3.5 SOMDDR3SODIMMSlotPinAssignments ........................................................................................ 13
4. LayoutandRoutingRecommendation............................................................................. 164.1 HDMI Interface ................................................................................................................................... 16
4.1.1 HDMISignalDefinition ................................................................................................................. 164.1.2 HDMILayoutandRoutingRecommendations ............................................................................. 174.1.3 HDMIReferenceSchematics ........................................................................................................ 19
4.2 Ethernet Interface .............................................................................................................................. 204.2.1 EthernetSignalDefinition ............................................................................................................ 204.2.2 EthernetLayoutandRoutingRecommendations ........................................................................ 214.2.3 EthernetReferenceSchematics ................................................................................................... 22
4.3 USB Interface ...................................................................................................................................... 234.3.1 USBSignalDefinition ................................................................................................................... 234.3.2 USBLayoutandRoutingRecommendations ................................................................................ 244.3.3 USBReferenceSchematics ........................................................................................................... 26
4.4 COM and UART Interface .................................................................................................................... 274.4.1 COMandUARTSignalDefinition ................................................................................................. 274.4.2 COMandUARTLayoutandRoutingRecommendations ............................................................. 284.4.3 COMandUARTReferenceSchematics ........................................................................................ 29
4.5 LCD Interface ...................................................................................................................................... 304.5.1 LCDSignalDefinition .................................................................................................................... 304.5.2 LCDLayoutandRoutingRecommendations ................................................................................ 314.5.3 LCDReferenceSchematics ........................................................................................................... 32
4.6 Touch Panel Interface ......................................................................................................................... 334.6.1 TouchPanelSignalDefinition ....................................................................................................... 334.6.2 TouchPanelLayoutandRoutingRecommendations ................................................................... 344.6.3 TouchPanelReferenceSchematics .............................................................................................. 35
4.7 GPIO Interface .................................................................................................................................... 364.7.1 GPIOSignalDefinition .................................................................................................................. 364.7.2 GPIOLayoutandRoutingRecommendation ................................................................................ 36
4.8 I²C Interface ........................................................................................................................................ 374.8.1 I²CSignalDefinition ..................................................................................................................... 374.8.2 I²CLayoutandRoutingRecommendation ................................................................................... 37
4.9 SPI Interface ....................................................................................................................................... 38
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4.9.1 SPISignalDefinition ..................................................................................................................... 384.9.2 SPILayoutandRoutingRecommendation ................................................................................... 38
4.10 Audio Interface ................................................................................................................................... 394.10.1 AudioSignalDefinition ................................................................................................................ 394.10.2 AudioLayoutandRoutingRecommendations ............................................................................. 394.10.3 AudioInterfaceReferenceSchematics ........................................................................................ 40
4.11 SD Interface ........................................................................................................................................ 424.11.1 SDSignalDefinition ...................................................................................................................... 424.11.2 SDLayoutandRoutingRecommendations .................................................................................. 424.11.3 SDInterfaceReferenceSchematics .............................................................................................. 43
Appendix A.SOMDB1CarrierBoardReferenceSchematics ................................................... 44
Carrier Board Design Guide for SOM-6X80 Module
ListofFiguresFigure1: Schematicconventions......................................................................................................................... 3Figure2: MicrostripPCBstackupexample .......................................................................................................... 4Figure3: StriplinePCBstackupexample ............................................................................................................. 4Figure4: 4-LayerPCBboardstackupdetail ......................................................................................................... 5Figure5: Point-to-pointandmulti-dropexamples ............................................................................................. 6Figure6: Daisy-chainexample ............................................................................................................................. 6Figure7: Alternatemulti-dropexample .............................................................................................................. 6Figure8: Signaltracewidthandspacingexample .............................................................................................. 7Figure9: Differentialsignaltracewidthandspacingexample ............................................................................ 7Figure10: Suggestedclocktracespacing .............................................................................................................. 8Figure11: Clocktracelayoutinrelationtothegroundplane ............................................................................... 8Figure12: Seriesterminationformultipleclockloads .......................................................................................... 8Figure13: SOM-6X80moduleplacementexampleonthecarrierboard ............................................................. 9Figure14: CarrierboardwithSOM-6X80module(sideview) .............................................................................. 9Figure15: CarrierboardandSOM-6X80moduleheightdistribution(sideview) ................................................. 9Figure16: DimensionsoftheSOM-6X80module ............................................................................................... 10Figure17: Dimensionsofthereferencecarrierboard ........................................................................................ 10Figure18: DimensionsoftheSOMDDR3SODIMMslot(topview) .................................................................... 11Figure19: DimensionsoftheSOMDDR3SODIMMslot(sideview) ................................................................... 11Figure20: PCBfootprintoftheSOMDDR3SODIMMslot .................................................................................. 12Figure21: PCBfootprintoftheSOMDDR3SODIMMslotwithSOM-6X80module ........................................... 12Figure22: SOMDDR3SODIMMslotschematics ................................................................................................. 15Figure23: HDMIroutingtopology ...................................................................................................................... 16Figure24: HDMIdifferentialtracewidthandspacingexample .......................................................................... 17Figure25: HDMIsingle-endedtracewidthandspacingexample ....................................................................... 17Figure26: HDMIreferencecircuitry .................................................................................................................... 19Figure27: Ethernetroutingtopology .................................................................................................................. 20Figure28: Ethernetsingle-endedtracewidthandspacingexample .................................................................. 21Figure29: Ethernetdifferentialtracewidthandspacingexample ..................................................................... 21Figure30: Ethernetreferencecircuitry ............................................................................................................... 22Figure31: USBroutingtopology ......................................................................................................................... 23Figure32: USBdifferentialsignalroutingexample ............................................................................................. 24Figure33: USBdifferentialtracewidthandspacingexample ............................................................................. 24Figure34: USBhostreferencecircuitry ............................................................................................................... 26Figure35: USBclientreferencecircuitry ............................................................................................................. 26Figure36: COMandUARTroutingtopology ....................................................................................................... 28Figure37: COMandUARTreferencecircuitry .................................................................................................... 29Figure38: LCDroutingtopology.......................................................................................................................... 31Figure39: LCDreferencecircuitry ....................................................................................................................... 32Figure40: Touchpanelroutingtopology ............................................................................................................ 34Figure41: Touchpanelreferencecircuitry .......................................................................................................... 35Figure42: Line-in1&2referencecircuitry ......................................................................................................... 40Figure43: Headphonereferencecircuitry .......................................................................................................... 40Figure44: Monospeakeroutreferencecircuitry ................................................................................................ 40Figure45: Rightchannelspeakerreferencecircuitry .......................................................................................... 41Figure46: Leftchannelspeakerreferencecircuitry ............................................................................................ 41Figure47: Onboardmicrophonereferencecircuitry........................................................................................... 41Figure48: SDroutingtopology ........................................................................................................................... 42Figure49: SDreferencecircuitry ......................................................................................................................... 43
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List of TablesTable1: Acronymsused ..................................................................................................................................... 2Table2: 4-LayerPCBimpedancecontrol .......................................................................................................... 5Table3: Recommendedtracewidthandspacing .............................................................................................. 7Table4: SOMDDR3SODIMMslotsample ....................................................................................................... 11Table5: SOMDDR3SODIMMslotpinouts ...................................................................................................... 14Table6: HDMIsignaldefinition ........................................................................................................................ 16Table7: HDMItraceproperties ....................................................................................................................... 17Table8: HDMIlayoutguidelines ...................................................................................................................... 18Table9: HDMIroutingtopologyandsignaltype ............................................................................................. 18Table10: Ethernetsignaldefinition ................................................................................................................... 20Table11: Ethernettraceproperties ................................................................................................................... 22Table12: Ethernetlayoutguidelines ................................................................................................................. 22Table13: Ethernetreferenceplane,signaltypeandroutingtopology ............................................................. 22Table14: USBsignaldefinition .......................................................................................................................... 23Table15: USBtraceproperties .......................................................................................................................... 25Table16: USBterminationoption,signaltypeandroutingtopology ................................................................ 25Table17: USBlayoutguidelines ......................................................................................................................... 25Table18: COMandUARTsignaldefinition ........................................................................................................ 27Table19: COMandUARTtraceproperties ........................................................................................................ 28Table20: COMandUARTtopology,signaltypeandlayoutguidelines .............................................................. 29Table21: LCDsignaldefinition ........................................................................................................................... 30Table22: LCDtraceproperties........................................................................................................................... 31Table23: LCDsignaltype,topologyandreferenceplane .................................................................................. 31Table24: LCDlayoutguidelines ......................................................................................................................... 32Table25: Touchpanelsignaldefinition ............................................................................................................. 33Table26: Touchpaneltraceproperties ............................................................................................................. 34Table27: Touchpanelsignaltype,routingtopologyandreferenceplane ........................................................ 34Table28: Touchpanellayoutguidelines ............................................................................................................ 34Table29: GPIOsignaldefinition ......................................................................................................................... 36Table30: GPIOtraceproperties ......................................................................................................................... 36Table31: GPIOsignaltype,topologyandlayoutguidelines .............................................................................. 36Table32: I²Csignaldefinition ............................................................................................................................ 37Table33: I²Ctraceproperties ............................................................................................................................ 37Table34: I²Csignaltype,topologyandlayoutguidelines .................................................................................. 37Table35: SPIsignaldefinition ............................................................................................................................ 38Table36: SPItraceproperties ............................................................................................................................ 38Table37: SPIsignaltype,topologyandlayoutguidelines ................................................................................. 38Table38: Audiosignaldefinition ....................................................................................................................... 39Table39: Audiotraceproperties ....................................................................................................................... 39Table40: Audiosignaltype,topologyandlayoutguidelines ............................................................................. 40Table41: SDsignaldefinition ............................................................................................................................. 42Table42: SDtraceproperties ............................................................................................................................ 43Table43: SDsignaltype,topologyandlayoutguidelines .................................................................................. 43
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1. IntroductionThisdocumentprovidesdesignguidelinesandrulerecommendationsforthedevelopersofacarrierboardthatsupportsthefeaturesoftheVIASOM-6X80module.Thisdocumentincludesthelayoutandroutingguidelinesforgeneralboarddesignsandmajorunderlyinginterfaces(e.g.HDMI,Ethernet,USB).Inaddition,thedocumentincludestheplacementandmechanicalinformationontheSOMDDR3SODIMMslotwhichisusedtoprovidehigh-speedinterfacesbetweenthecarrierboardandthemodule.
Pleasenotethatthisdocumentisconsideredtobeareferenceguideonly.Thisdocumentisnotintendedtobeaspecification.Allinformationandexampleslistedbelowareconsideredtobeaccurateasofthepublicationdate.However,developersmustbeawarethatthisdocumentisonlyareferenceguide.
1.1 Document OverviewAbriefdescriptionofeachchapterisgivenbelow.
Chapter 1: IntroductionThischapterbrieflyintroducesthestructureofthedesignguidedocument.
Chapter 2: General Carrier Board RecommendationsThegeneraldesignschemesandrecommendedlayoutrulesareshowninthischapter.
Chapter 3: SOM-6X80 Module and SOM DDR3 SODIMM Slot Specification OverviewDetailedinformationabouttheSOM-6X80moduleandSOMDDR3SODIMMslotplacementanddimensionsare described in this chapter.
Chapter 4: Layout and Routing RecommendationsDetailedlayoutandroutingguidelinesforeachmajorinterfacearedescribedinthischapter.
Appendix A: Carrier Board Reference SchematicsReferenceschematicsoftheSOMDB1evaluationcarrierboard.
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1.2 Acronyms Used
Table1:Acronyms used
Term DescriptionASIC Application-specificIntegratedCircuitDDR Double Data RateEMI ElectromagneticInterferenceESD Electrostatic-discharge
GPIO General Purpose Input/OutputHDMI High-DefinitionMultimediaInterface
I²C Inter-ICIC IntegratedCircuit
LCD Liquid-Crystal DisplayLVDS Low-VoltageDifferentialSignalingP2P Point-to-PointPCB Printed Circuit BoardRGB Red,GreenandBlue
RJ-45 RegisteredJack45RS-232 Recommend Standard number 232
SD SecureDigitalSODIMM Small Outline Dual In-line Memory Module
SMT SurfaceMountTechnology
SOM System-On-ModuleSPI Serial Peripheral Interface
UART UniversalAsynchronousReceiver-TransmitterUSB Universal Serial Bus
USB OTG USB On-The-Go
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1.3 SchematicConventionsThereferenceschematicsdepictedinthisdocumentshowthedirectionalflowofthesignals.Directionalflowisindicated by the pointed ends of the arrow shapes.
Figure1:Schematicconventions
Bidireconal signal flow
IC/Connector
Input signal flow
Output signal flow
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2. General Carrier Board Recommendations ThissectioncontainsgeneralguidelinesforthePCBstackupandthelayoutoftraces.Thegeneralguidelinesforroutingstyle,topology,andtraceattributerecommendationsarealsodiscussed.
2.1 PCB StackupThePCBstackupconsistsofsignallayersandreferencelayers(powerandground).Thesignallayersarereferredtoasthecomponentlayer(top),innerlayerandsolderlayer(bottom).
ThecarrierboarddesignerscanchoosebetweentwobasiccategoriesofPCBstackupdesign:microstripandstripline.Themicrostripdesignshavetheoutersignallayersexposed.Thestriplinedesignshavetheoutermostsignallayersshieldedbyreferencelayers.
Thefollowingfiguresshowanexampleofmicrostripandstriplinedesigns.
.
Figure2:Microstrip PCB stackup example
Figure3:Stripline PCB stackup example
Thechoiceofmicrostriporstriplinedesigndependsontheapplicationforwhichthecarrierboardisbeingdesigned.IfthecarrierboardisbeingdesignedforlocationswheresensitivitytoEMIisanissue,astriplinedesignisrecommendedforreducingEMIandnoisecoupling.ForapplicationswherethetoleranceforEMIlevelsisgreater,amicrostripdesignisrecommendedtoreducecosts.DuetotheinherentnatureofstriplinePCBstacks,broad-sidecouplingispossible.
Microstrip stackup design
Signal layers
Reference layers
Component layer
Ground layer
Inner layer
Power layer
Ground layer
Solder layer
Stripline stackup design
Signal layers
Reference layers
Component layer
Ground layer
Inner layer
Power layer
Ground layer
Solder layer
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2.1.1 4-Layer PCB Stackup ExampleThefollowingfigureshowstherecommended4-layerPCBstackupdesignforthecarrierboardoftheSOM-6X80 module.
Figure4:4-Layer PCB board stackup detail
2.1.2 4-Layer PCB Impedance Control
Table2: 4-Layer PCB impedance control
± 10%40Ω
Single-end50Ω
Single-end55Ω
Single-end85Ω
Differential90Ω
Differential90Ω
Differential
Layer 1 12mil 8mil 7mil7.8:9:7.8
mil7.6:8:7.6
mil7:7.5:7
mil
Layer 4 12mil 8mil 7mil7.8:9:7.8
mil7.6:8:7.6
mil7:7.5:7
mil
TOP = 1.0oz (1.46mil)
GROUND = 1.0oz (1.18mil)
POWER =1.0oz (1.18mil)
BOTTOM = 1.0 oz (1.46mil)
PP (Er) = 4.76 mil
Core (Er) = 44.88mil
PP (Er) = 4.76 mil
Soldermask = 0.79mil
Pla ng = 0.8mil
Soldermask = 0.79mil
Pla ng = 0.8mil
LAYER 1
LAYER 2
LAYER 3
LAYER 4
61.68mil
Copper foil + Plang
Copper foil
Copper foil
Copper foil + Plang
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2.2 GeneralLayoutandRoutingGuidelinesThissectionprovidesgenerallayoutrulesandroutingguidelinesfordesigningcarrierboardsfortheSOM-6X80module.
2.2.1 RoutingStylesandTopologyTopologyisthephysicalconnectivityofanetoragroupofnets.Therearetwotypesoftopologiesforacarrierboardlayout:point-to-point(P2P)andmulti-drop.AnexampleofthesetopologiesisshowninFigure5.
Figure5:Point-to-pointandmulti-dropexamples
High-speedbussignalsaresensitivetotransmissionlinestubs,whichcanresultinringingontherisingedgecausedbythehighimpedanceoftheoutputbufferinthehighstate.Inordertomaintainbettersignalquality,transmissionstubsshouldbekeptasshortaspossible(lessthan1.5”).Therefore,daisychainstyleroutingisstronglyrecommendedforthesesignals.Figure6belowshowsanexampleofdaisychainrouting.
Figure6:Daisy-chain example
Ifdaisychainroutingisnotallowedinsomecircumstances,differentroutingsmaybeconsidered.AnalternativetopologyisshowninFigure7.Inthiscase,thebranchpointissomewherebetweenbothends.Itmaybenearthesourceorneartheloads,butbeingclosetotheloadsideisbest.Theseparatedtracesshouldbeequalinlength.
Figure7:Alternatemulti-dropexample
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2.2.2 GeneralTraceAttributeRecommendationA5miltracewidthand10milspacingaregenerallyadvisedformostsignaltracesonacarrierboardlayout.Toreduce trace inductance the minimum power trace width is recommended to be 30mil.
Asaquickreference,theoverallrecommendedtracewidthandspacingfordifferenttracetypesarelistedinTable3,andtherecommendedtracewidthandspacingforeachsignalgroupisshowninChapter4.
Table3:Recommendedtracewidthandspacing
Generalrulesforminimizingcrosstalkinhigh-speedbusdesignsarelistedbelow:
• Maximize the distance between traces. Maintain 10mil minimum spaces between traces wherever possible.
•Maximizethedistance(30milminimum)betweentwoadjacentroutingareasofdifferentsignalgroups wherever possible.
•Avoidparallelismbetweentracesonadjacentlayers.
•Providestablereferenceplanesforallhigh-speedsignals.
•Neverroutehigh-speedsignalsoversplitsintheirperspectivereferenceplanes.
•Selectaboardstack-upthatminimizescouplingbetweenadjacenttraces.
Figure8:Signaltracewidthandspacingexample
Figure9:Differentialsignaltracewidthandspacingexample
Notes:1.W:Tracewidth2.S:Thespacingtoothertraces3.S1:Differentialpairspacing
Trace Type Trace Width (mil) Spacing (mil)RegularSignal 5 or wider 10 or widerInterfaceorBusReferenceVoltageSignal 20 or wider 20 or widerPower 30 or wider 20 or wider
S1S S
Reference Plane
W W
Signal Signal
S
Reference Plane
WS
Signal
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2.2.3 GeneralClockRoutingConsiderationsTheclockroutingguidelinesarelistedbelow:
• The recommended clock trace width is 5mil.
•Theminimumspacebetweenoneclocktraceandadjacentclocktracesis20mil.Theminimumspace fromonesegmentofaclocktracetoothersegmentsofthesameclocktraceisatleasttwotimesof theclockwidth.Thatis,morespaceisneededfromoneclocktracetoothersoritsowntracetoavoid signalcoupling(seeFigure10).
•Theclocktracesshouldbeparalleltotheirreferencegroundplanes.Thatis,aclocktraceshouldberight beneathorontopofitsreferencegroundplane(seeFigure11).
•Theseriesterminations(dampingresistors)areneededforallclocksignals(typically0Ωto47Ω).When twoloadsaredrivenbyoneclocksignal,theseriesterminationlayoutisshowninFigure12.When multipleloads(morethantwo)areapplied,aclockbuffersolutionispreferred.
•Isolatingclocksynthesizerpowerandgroundplanesthroughferritebeadsornarrowchannels(typically 20milto50milwide)ispreferred.
• No clock traces on the internal layer if a six-layer board is used.
Figure10:Suggestedclocktracespacing
Figure11:Clocktracelayoutinrelationtothegroundplane
Figure12:Seriesterminationformultipleclockloads
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3. SOM-6X80 Module and SOM DDR3 SODIMM Slot Specification Overview3.1 SOM-6X80 Module Placement ThefollowingfigureshowsthedepictionofthetopviewofthecarrierboardPCB(SOMDB1)withtheappropriate amount of space reserved for the SOM-6X80 module.
Figure13:SOM-6X80 module placement example on the carrier board
3.2 SOM-6X80ModuleMechanicalCharacteristics
Figure14:CarrierboardwithSOM-6X80module(sideview)
Figure15:CarrierboardandSOM-6X80moduleheightdistribution(sideview)
Carrier board
67.6mm
44.3mm
48mm
O 2mm
Carrier board PCB
SOM DDR3 SODIMM slotVIA SOM-6X80 module
Standoff spacer
Screw
6.5mm 1.8mm
68mm
1.3mm
2.5mm
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3.3 SOM-6X80 Module and Carrier Board DimensionsThefollowingfiguresshowthemechanicaldimensionsoftheSOM-6X80moduleandthereferencecarrierboard(SOMDB1).
Figure16:Dimensions of the SOM-6X80 module
Figure17:Dimensions of the reference carrier board
SOMDB1VTS8666C
152.4mm
160mm
26mm
100mm
77mm 42mm41mm
3.8mm
O 4mm 3.8mm
92.4mm
67.6mm
44.3mm
63mm
O 2mm
20mm
21mm39mm
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3.4 SOM DDR3 SODIMM SlotTheSOMDDR3SODIMMslotcanhandlehigh-speedsignalsandcomprises204pinstoconnecttheSOM-6X80module.Table4showsthespecificationsampleoftheSOMDDR3SODIMMslot.
Table4:SOM DDR3 SODIMM slot sample
3.4.1 SOM DDR3 SODIMM Slot Dimensions
Figure18:DimensionsoftheSOMDDR3SODIMMslot(topview)
Figure19:DimensionsoftheSOMDDR3SODIMMslot(sideview)
Part Number Description Height Vendor
40-40024-02 DDR3 SODIMM 5.2H 1.5V STD PLASTIC LATCH ASSEMBLY 5.2mm Deren
41.95mm±0.15
3.70mm3.70mm
71.1mm
64.7mm
21mm39mm3mm
1.35mm0.6mm0.6mm
0.15mm
21mm39mm3mm
1.35mm
41.35mm 23.35mm23.95mm±0.15
67.90mm±0.15
0.45mm
23.0
5mm
±0.2
0
25.8
5mm
±0.1
5
3mm
5.20mm
0.80mm
5mm
12mm
17.15mm9.80mm
0.60mm
5mm
1.06mm±0.04
0.25mm0.05mm +0.1
-0.05204 PIN CONTRACT
1.16mm REF.0.28mm +0.1
-0.05
SOM-6X80 module
Slot
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3.4.2 SOM DDR3 SODIMM Slot Footprint
Figure20:PCB footprint of the SOM DDR3 SODIMM slot
Figure21:PCB footprint of the SOM DDR3 SODIMM slot with SOM-6X80 module
Pin # 204
39mm
3mm
21mm
Pin # 2
0.60mm (Pitch)
12mm
4.1mm
4.1mm
Ø1.10mm±0.05 (Hole)
Pin # 1
39mm
Pin # 203 3mm
21mm
0.35mm±0.03
Ø1.60mm±0.05 (Hole)
2mm±0.03
4.60mm±0.10 (2X)
3.50mm±0.10 (2X)
Carrier board PCB
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3.5 SOMDDR3SODIMMSlotPinAssignmentsThe SOM DDR3 SODIMM slot consists of 204 pins. The pinouts of the SOM DDR3 SODIMM slot are shown below.
Pin Signal Pin Signal1 USBATTA0 2 GND3 USBID0 4 nUSBHB+5 USBSW0 6 nUSBHB-7 GND 8 GND9 SPI0MISO 10 nUSBHA+
11 SPI0MOSI 12 nUSBHA-13 SPI0CLK 14 GND15 SPI0SS0- 16 nUSBHD0+17 GND 18 nUSBHD0-19 SD0CLK 20 GND21 SD0DATA1 22 UARTB_CTS23 SD0WP 24 UARTB_RTS25 SD0DATA0 26 UARTB_RX27 SD0CMD 28 UARTB_TX29 SD0DATA2 30 UARTA_CTS31 SD0DATA3 32 UARTA_RTS33 SD0PWRSW 34 UARTA_RX35 SD0CD 36 UARTA_TX37 M0_LINK 38 UARTC_RTS39 M0_SPEED 40 UARTC_RX41 PWMOUT0 42 UARTC_TX43 PWMOUT1 44 UARTC_CTS45 GND 46 UARTD_RTS47 NET_RX- 48 UARTD_CTS49 NET_RX+ 50 UARTD_TX51 GND 52 UARTD_RX53 NET_TX- 54 VDHSYNC55 NET_TX+ 56 VDVSYNC57 GND 58 VDDEN59 nHDMIHPD 60 VDCLK61 nHDMICEC 62 VDOUT063 nHDMIDDCSDA 64 VDOUT865 nHDMIDDCSCL 66 VDOUT167 GND 68 VDOUT1069 NC 70 VDOUT371 NC 72 VDOUT273 GND 74 VDOUT575 nHDMICLK+ 76 VDOUT477 nHDMICLK- 78 VDOUT6
Pin Signal Pin Signal79 GND 80 VDOUT1381 nHDMID0+ 82 VDOUT983 nHDMID0- 84 VDOUT785 GND 86 VDOUT1587 nHDMID1+ 88 VDOUT1189 nHDMID1- 90 VDOUT1291 GND 92 VDOUT1993 nHDMID2+ 94 VDOUT1495 nHDMID2- 96 VDOUT1897 GND 98 VDOUT1799 VDIN0 100 VDOUT20
101 VDIN1 102 VDOUT21103 VDIN2 104 VDOUT16105 VDIN4 106 VDOUT23107 VDIN3 108 VDOUT22109 VCLK 110 UART1RXD111 GND 112 UART1TXD113 VDIN6 114 NC115 C24MOUT 116 NC117 VDIN5 118 UART0RXD119 VDIN7 120 UART0TXD121 VVSYNC 122 SD2CMD123 VHSYNC 124 SD2CLK125 GPIO12 126 SD2DATA0127 GPIO13 128 SD2DATA3129 GND 130 SD2DATA2131 SPK_OUT_R- 132 SD2DATA1133 SPK_OUT_R+ 134 SD2PWRSW135 GND 136 SD2WP137 SPK_OUT_L- 138 I2C0SDA139 SPK_OUT_L+ 140 I2C0SCL141 GND 142 I2C1SCL143 HPOUTR 144 I2C1SDA145 OUT3 146 I2C2SDA147 HPOUTL 148 I2C2SCL149 MICBIAS 150 SUS_GPIO0151 GND 152 PWRGD153 LINPUT3 154 WAKEUP0155 LINPUT2 156 SPI1MOSI
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Table5:SOM DDR3 SODIMM slot pinouts
Pin Signal Pin Signal157 LINPUT1 158 GND159 GND 160 SPI1CLK161 RINPUT1 162 SPI1SS0-163 RINPUT2 164 SPI1MISO165 GND 166 GPIO1167 WAKEUP3 168 GPIO0169 PWRENVCC 170 GPIO2171 WAKEUP2 172 GPIO6173 CIRIN 174 GPIO3175 PWRENMEM 176 GPIO4177 PWRENVDD 178 GPIO5179 SUS_GPIO1 180 GPIO9181 PWRBTN- 182 GPIO7183 RSMRST- 184 VSUS33185 PWMOUT3 186 VSUS33187 PWMOUT2 188 VCC33189 PWREN_MAIN 190 VCC33191 VCC-BAT 192 VCC33193 NC 194 NC195 VIN 196 GND197 VIN 198 GND199 VIN 200 GND201 VIN 202 GND203 VIN 204 GND
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Figure22:SOMDDR3SODIMMslotschematics
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4. Layout and Routing RecommendationTheinformationpresentedinthischapterincludesthesignaldefinition,topology,layoutandroutingguidelinesforeachbusinterface,andreferenceschematicsexample.Theinformationprovidedisintendedfordesigningcarrier boards that are compliant with the SOM-6X80 module.
4.1 HDMI InterfaceTheSOM-6X80modulefeaturesoneHDMIinterface.TheHDMIinterfaceusesfourcontrolsignals,onedifferentialclock,andthreedifferentialdatapairsignalsthatcarryvideoandaudiosignals.
4.1.1 HDMISignalDefinitionThefollowingtableprovidesthedefinitionoftheHDMIsignalsthatareimplementedintheSOMDDR3SODIMM slot.
Table6:HDMIsignaldefinition
Figure23:HDMIroutingtopology
Note:TheEMIfiltersandESDcomponentsmustbeplacedneartheHDMIport.
Signal Name Pin # I/O DescriptionnHDMID0+ 81
O HDMIdifferentialpairlineslane0nHDMID0- 83nHDMID1+ 87
O HDMIdifferentialpairlineslane1nHDMID1- 89
nHDMID2+ 93O HDMIdifferentialpairlineslane2
nHDMID2- 95nHDMICLK+ 75
O HDMIdifferentialpairclocklinesnHDMICLK- 77nHDMIDDCSCL 65 IO HDMI DDC SCLnHDMIDDCSDA 63 IO HDMI DDC SDAnHDMICEC 61 O HDMI consumer electronics connectornHDMIHPD 59 O HDMIhotplugdetect
L1L1
L1L1
L1
L1
L2
L2
SOM DDR3SODIMM Slot
HDMI port
EMI filter1 2
4 3
ESD
1 2
4 3
ESD
1 2
4 3
ESD
1 2
4 3
ESD
SOM-6X80
Edge
fing
er
L2
L2
L2
L2
L2
L2
L2
L2
nHDMID0+
nHDMID0-
nHDMID2+
nHDMIDDCSCL
nHDMIDDCSDA
nHDMICLK-
nHDMICLK+
nHDMID2-
nHDMID1-
nHDMID1+
ESD
ESD
L2
L2nHDMIHPD
nHDMICEC
N-ChannelDigital FET
L1
L1Route Differenally
L1
L1Route Differenally
L1
L1Route Differenally
L1
L1Route Differenally
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4.1.2 HDMILayoutandRoutingRecommendations•Tracelengthsshouldbekepttoaminimum.
•Eachtraceofdifferentialpairsshouldnothavemorethantwoviaholes.
•Eachdifferentialpairssignalshouldroutetoparalleltoeachotherwiththesametracelength.
•Differentialpairshouldbeallreferencedtoground.
•Routethedifferentialpairsonasinglelayeradjacenttoagroundplane.
•Thespacingbetweenthedifferentialpairsignalandothersignalsshouldbeatleastthreetimesthetrace width.
Figure24:HDMIdifferentialtracewidthandspacingexample
Figure25:HDMIsingle-endedtracewidthandspacingexample
Table7:HDMItraceproperties
HDMI SignalDifferenal Pair
S1S S
Reference Plane
W W
S
Reference Plane
WS
HDMI SignalSingle-ended
Signal Group Signal Name Trace Impedance
Trace & Spacing (mil)(S : W : S1 : W : S)
Pair to Pair Trace Mismatch
Spacing to Other Signal
Data
nHDMID0+
100Ω±15%(Differential)
15:5:7:5:15<5mil
(Differential)15mil
nHDMID0-nHDMID1+nHDMID1-nHDMID2+nHDMID2-
ClocknHDMICLK+ 100Ω±15%
(Differential)15:5:7:5:15 <5mil
(Differential) 15milnHDMICLK-
Control
nHDMIDDCSCL
50Ω±15%5:10(W:S)
6mil 10milnHDMIDDCSDAnHDMICECnHDMIHPD
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Table8:HDMIlayoutguidelines
Table9:HDMIroutingtopologyandsignaltype
Signal Group Signal Name Routing LayerAccumulated Trace Length (L1+ L2 = LT)
Length Difference (mil)
To Clock In Group
Data
nHDMID0+
Top/Bottom LT < 3" <500 <1000
nHDMID0-nHDMID1+nHDMID1-nHDMID2+nHDMID2-
ClocknHDMICLK+
Top/Bottom LT < 3" <500 <1000nHDMICLK-
Control
nHDMIDDCSCL
Top/Bottom LT < 3" <500 <1000nHDMIDDCSDAnHDMICECnHDMIHPD
Signal Group Signal Name Reference Plane Routing Topology Signal Type
Data
nHDMID0+
Ground Point-to-Point DifferentialPairs
nHDMID0-nHDMID1+nHDMID1-nHDMID2+nHDMID2-
ClocknHDMICLK+
Ground Point-to-Point DifferentialPairsnHDMICLK-
Control
nHDMIDDCSCL
Ground Point-to-Point Single-endednHDMIDDCSDAnHDMICECnHDMIHPD
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19
4.1.3 HDMIReferenceSchematics
Figure26:HDMI reference circuitry
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20
4.2 Ethernet InterfaceTheSOM-6X80modulefeaturesoneEthernet(10/100Mbps)interface.TheEthernetinterfaceconsistsoftwodifferentialdatasignalsandtwocontrolsignalsforactivitylinkandspeedindicators.
4.2.1 EthernetSignalDefinitionThefollowingtableprovidesthedefinitionoftheEthernetsignalsthatareimplementedintheSOMDDR3SODIMM slot.
Table10: Ethernetsignaldefinition
Figure27:Ethernetroutingtopology
Note:ThemagneticmodulehastobeplacedascloseaspossibletotheRJ-45port.Thedistancemustbelessthan1".
Signal Name Pin # I/O DescriptionNET_TX+ 55
O EthernetdifferentialpairlinesTransmitNET_TX- 53NET_RX+ 49
O EthernetdifferentialpairlinesReceiveNET_RX- 47
M0_SPEED 39 O Ethernet controller 0 100Mbps speed indicatorM0_LINK 37 O Ethernet controller 0 100Mbps link indicator
SOM DDR3SODIMM Slot
RJ-45 port SOM-6X80
Edge
fing
er
L1
L1
L1
L1
LT
LT
L2
L2
L2
L2
NET_TX+
NET_TX-
M0_SPEED
M0_LINK
NET_RX-
NET_RX+
Magnec module (Transformer)
Route Differenally
Route Differenally
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4.2.2 EthernetLayoutandRoutingRecommendations•Routedifferentialpairsclosetogetherandawayfromothersignals.
•Routeanyothertraceparalleltooneofthedifferentialtrace.
•Keeptracelengthwithineachdifferentialpairequal.
•Keepproperimpedancebetweentwotraceswithinadifferentialpair.
•Eachtraceofdifferentialpairsshouldnothavemorethantwoviaholes.
•Thespacingbetweenthedifferentialpairsignalandothersignalsshouldbeatleastthreetimesthetrace width.
•Eachdifferentialpairofsignalsisrequiredtobeparalleltoeachotherwiththesametracelength (Tolerance±50mil)onthecomponent(top)layerandtobeparalleltoarespectivegroundplane. Thelengthdifferencebetweentheshortestandlongestpairsshouldbelessthan200mil.
•TheaccumulatedtracelengthofthedifferentialsignalspairbetweentheSOMDDR3SODIMMslotand magneticmoduleshouldbelessthan1".
•TheaccumulatedtracelengthofthedifferentialsignalspairbetweenthemagneticmoduleandRJ-45 connectorshouldbelessthan1".Isolategroundplaneandconnecttochassis.
•Keepeachdifferentialpaironthesameplane.
•Topreventanynoisefrominjectingintothedifferentialpairs,besuretokeepdigitalsignalsorother signalsawayfromthedifferentialsignals.
•TheexternalmagneticmoduleshouldbeplacedclosetotheRJ-45connectortolimitEMIemissions.
Figure28:Ethernetsingle-endedtracewidthandspacingexample
Figure29:Ethernetdifferentialtracewidthandspacingexample
.
S
Reference Plane
WS
Ethernet Signal Single-ended
Ethernet SignalDifferenal Pair
S1S S
Reference Plane
W W
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Table11: Ethernettraceproperties
Table12: Ethernetlayoutguidelines
Table13: Ethernetreferenceplane,signaltypeandroutingtopology
4.2.3 EthernetReferenceSchematics
Figure30:Ethernet reference circuitry
Signal Group Signal Name Trace Impedance
Trace & Spacing (mil)(S : W : S1 : W : S)
Pair to Pair Trace Mismatch
Spacing to Other Signal
Data
NET_TX+
100Ω±15%(Differential)
10:10:5:10:10 50mil 10milNET_TX-NET_RX+NET_RX-
ControlM0_SPEED
55Ω±15% 5:10 - 10milM0_LINK
Signal Group Signal Name Routing LayerAccumulated Trace Length(L1+ L2 = LT)
Length Difference (mil)
To Clock
Data
NET_TX+
Top/Bottom LT < 3" <1500NET_TX-NET_RX+NET_RX-
ControlM0_SPEED
Top/Bottom LT < 3" <1500M0_LINK
Signal Group Signal Name Reference Plane Signal Type Routing Topology
Data
NET_TX+
Ground/Power DifferentialPairs Point-to-PointNET_TX-NET_RX+NET_RX-
ControlM0_SPEED
Ground/Power Single-ended Point-to-PointM0_LINK
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4.3 USB InterfaceThe SOM-6X80 module features three USB 2.0 interfaces. Two of the three USB interfaces can only be used as ahost.Theotherinterfacecanbeconfiguredtobeusedaseitherthehostorclient.TheUSBinterfacesignalsusethreebi-directionaldifferentialdatapairs.
4.3.1 USBSignalDefinitionThefollowingtableprovidesthedefinitionoftheUSBsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table14: USBsignaldefinition
Figure31:USBroutingtopology
Signal Name Pin # I/O DescriptionnUSBHD0+ 16
IOOTGUniversalSerialBusport0,data+
nUSBHD0- 18 OTGUniversalSerialBusport0,data-nUSBHA+ 10
IOUniversalSerialBusport1,data+
nUSBHA- 12 UniversalSerialBusport1,data-
nUSBHB+ 4IO
UniversalSerialBusport2,data+nUSBHB- 6 UniversalSerialBusport2,data-USBATTA0 1 I UniversalSerialBusdeviceattachdetectUSBID0 3 I Port ID pinUSBSW0 5 I Universal Serial Bus power control pin
L2
L2
L2
L2
L2
L2
L1L1
L1L1
L1L1
L1L1
L1L1
L1L1
SOM DDR3SODIMM Slot
USB port 1
EMI filter1 2
4 3
ESD
1 2
4 3
ESD
1 2
4 3
ESD
SOM-6X80
Edge
fing
er
nUSBHA+
nUSBHA-
nUSBHD0+
USBID0
USBSW0
USBATTA0
nUSBHD0-
nUSBHB-
nUSBHB+USB port 2
USB port 3 (Micro USB)
USB Overcurrent Protector IC
R
R
VSUS
R
VCC
R
R
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4.3.2 USBLayoutandRoutingRecommendations•Thedifferentialpairsignalsshouldbeallreferencedtoground.
•Eachtraceofdifferentialpairsshouldnothavemorethantwoviaholes.
•Differentialpairrouteinparallelandinequallength.
•TheamountofviasandcornersusedfortheUSBsignallayoutshouldbeminimized;thisistopreventtheoccurrenceofreflectionandimpedancechanges.
•EachpairofUSBdatalinesisrequiredtobeparalleltoeachotherwiththesametracelength,andnot parallelwithothersignalstominimizecrosstalk.
•Separatethesignaltracesintosimilargroupsandroutesimilarsignaltracestogether.Inaddition,itisrecommendedtohavedifferentialpairsroutedtogetheronthecarrierboard.
•Controltracesignalsimpedanceshouldmaintain55Ω±10%.
•FortheUSBtraces,donotroutethemunderoscillators,crystals,clocksynthesizers,magneticdevicesorIC’swhichcouldbeusingduplicateclocks.
TheroutingexamplefortwopairsofUSBdatabusesisshowninFigure32.
Figure32:USBdifferentialsignalroutingexample
Figure33:USBdifferentialtracewidthandspacingexample
SOM DDR3SODIMM Slot
nUSBHA+
nUSBHA-
nUSBHA-
nUSBHA+
Recommended
USB port
USB port
Not recommended
S1W W
USB Signal Differenal Pair
S S
Reference Plane
S1W W
S
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Table15: USBtraceproperties
Table16: USBterminationoption,signaltypeandroutingtopology
Table17: USBlayoutguidelines
Signal Group Signal Name Trace Impedance
Trace & Spacing (mil)(S : W : S1 : W : S)
Pair to Pair Trace Mismatch
Spacing to Other Signal
Data
nUSBHA+
90Ω±15% 20:7:7.5:7:20 100mil 20mil
nUSBHA-nUSBHB+nUSBHB-nUSBHD0+nUSBHD0-
ControlUSBATTA0
55Ω±10% 5:10 - 10milUSBID0USBSW0
Signal Group Signal Name Termination Option Signal Type Topology
Data
Port 1nUSBHA+
90Ω DifferentialDataPairs Point-to-Point
nUSBHA-
Port 2nUSBHB+nUSBHB-
Port 3nUSBHD0+nUSBHD0-
ControlUSBATTA0
60Ω - Point-to-PointUSBID0USBSW0
Signal Group Signal Name Routing LayerLength Difference
(In Pair)
Accumulated Trace Length(L1+ L2 = LT)
Data
Port 1nUSBHA+
Top/Bottom <100mil LT < 12"
nUSBHA-
Port 2nUSBHB+nUSBHB-
Port 3nUSBHD0+nUSBHD0-
ControlUSBATTA0
Top/Bottom - LT < 12"USBID0USBSW0
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4.3.3 USBReferenceSchematics
Figure34:USB host reference circuitry
TheUSBportmodecanbecontrolledbythesignalUSBID0.Inthereferencecircuitryexamplebelow,theUSBID0signalisreferencedtogroundthatmakestheUSBportmodeasclientUSB(orUSBOTGport).
Figure35:USB client reference circuitry
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4.4 COM and UART InterfaceTheSOM-6X80modulefeaturesCOMandUARTinterfacesthatenabletheinterfacingoffourCOMortwoUARTonthecarrierboard.ThefourCOMinterfacesareusedforRS-232serialcommunicationsandthetwoUARTcanbeusedforTX/RX,RTS,CTSanddebuggingTX/RX.
4.4.1 COMandUARTSignalDefinitionThefollowingtableprovidesthedefinitionoftheCOMandUARTsignalsthatareimplementedintheSOMDDR3 SODIMM slot.
Table18: COMandUARTsignaldefinition
Signal Name Pin # I/O DescriptionUARTA_TX 36 O UART Port-A transmit dataUARTA_RX 34 I UART Port-A receive dataUARTA_RTS 32 O UART Port-A request to sendUARTA_CTS 30 I UART Port-A clear to send
UARTB_TX 28 O UART Port-B transmit dataUARTB_RX 26 I UART Port-B receive dataUARTB_RTS 24 O UART Port-B request to sendUARTB_CTS 22 I UART Port-B clear to sendUARTC_TX 42 O UART Port-C transmit dataUARTC_RX 40 I UART Port-C receive dataUARTC_RTS 38 O UART Port-C request to sendUARTC_CTS 44 I UART Port-C clear to sendUARTD_TX 50 O UART Port-D transmit dataUARTD_RX 52 I UART Port-D receive dataUARTD_RTS 46 O UART Port-D request to sendUARTD_CTS 48 I UART Port-D clear to sendUART1TXD 112 O UART Port-1 transmit dataUART1RXD 110 I UART Port-1 receive dataUART0TXD 120 O UART Port-0 transmit dataUART0RXD 118 I UART Port-0 receive data
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Figure36:COMandUARTroutingtopology
4.4.2 COMandUARTLayoutandRoutingRecommendations•Thetransmitandreceivedatatracesignalsshouldberoutedinparallelandinequallength.
•TheamountofviasandcornersusedfortheCOMandUARTsignallayoutshouldbeminimized;thisisto preventtheoccurrenceofreflectionandimpedancechanges.
•Controltracesignalsimpedanceshouldmaintain55Ω±10%.
Table19: COMandUARTtraceproperties
L4L3L2L1
L4L3L2L1
L4L3L2L1
L4L3L2L1
ESD
L2
L2COM port 1
L4
L4
L3
L3
L1
L1
L4L3L2L1
L2
L2COM port 2
L4
L4
L3
L3
L1
L1
ESD UARTpin header 1
ESD
L2
L2COM port 3
L4
L4
L3
L3
L1
L1
L2
L2COM port 4
L4
L4
L3
L3
L1
L1
ESD UARTpin header 2
SOM DDR3SODIMM Slot
SOM-6X80
Edge
fing
er
UARTA_TX
UARTA_RTS
UARTA_RX
UARTA_CTS
UARTB_TX
UARTB_RTS
UARTB_RX
UARTB_CTS
UARTD_TX
UARTD_RTS
UARTD_RX
UARTD_CTS
UARTC_TX
UARTC_RTS
UARTC_RX
UARTC_CTS
L4L3L2L1
L4L3L2L1
L4L3L2L1
Tranceiver IC
Tranceiver IC
Tranceiver IC
Tranceiver IC
Signal Group Signal NameTrace (mil)
(Width:Spacing)Trace Impedance Spacing in Other Group
Data
UART[D:A]_TX
5:5 55Ω±10% 5milUART[D:A]_RXUART[1:0]TXDUART[1:0]RXD
ControlUART[D:A]_CTS
5:5 55Ω±10% 5milUART[D:A]_RTS
Carrier Board Design Guide for SOM-6X80 Module
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Table20: COMandUARTtopology,signaltypeandlayoutguidelines
4.4.3 COMandUARTReferenceSchematics
Figure37:COM and UART reference circuitry
Signal Group Signal Name Signal Type Topology Reference Plane
Accumulated Trace Length
(L1 + L2 + L3 + L4 = LT)
Data
UART[D:A]_TX
Single-ended Point-to-Point Ground/Power <10"UART[D:A]_RXUART[1:0]TXDUART[1:0]RXD
ControlUART[D:A]_CTS
Single-ended Point-to-Point Ground/Power <10"UART[D:A]_RTS
Carrier Board Design Guide for SOM-6X80 Module
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4.5 LCD InterfaceTheSOM-6X80modulefeaturesone(RGB)LCDinterface.TheLCDinterfaceisaparallelbussignalprovidedforinterfacingtheLCDconnectorforLVDSLCDdisplayasthemaindisplayinterface.TheLCDinterfaceisasingle-channel that supports 18-bit and 24-bit interfaces.
4.5.1 LCDSignalDefinitionThefollowingtableprovidesthedefinitionoftheLCDsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table21: LCDsignaldefinition
Signal Name Pin # I/O DescriptionVDOUT0 62 O
BlueLCDdatasignal
VDOUT1 66 O
VDOUT2 72 OVDOUT3 70 O
VDOUT4 76 OVDOUT5 74 OVDOUT6 78 OVDOUT7 84 OVDOUT8 64 O
GreenLCDdatasignal
VDOUT9 82 OVDOUT10 68 OVDOUT11 88 OVDOUT12 90 OVDOUT13 80 OVDOUT14 94 OVDOUT15 86 OVDOUT16 104 O
RedLCDdatasignal
VDOUT17 98 OVDOUT18 96 OVDOUT19 92 OVDOUT20 100 OVDOUT21 102 OVDOUT22 108 OVDOUT23 106 OVDHSYNC 54 O LCD Line Horizontal SyncVDVSYNC 56 O LCDFrameVerticalSyncVDDEN 58 O LCD Data EnableVDCLK 60 O LCD Clock
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Figure38:LCDroutingtopology
4.5.2 LCDLayoutandRoutingRecommendations•RGBdatasignaltracesshouldbedesignedtobeasshortaspossible.
•InordertomaximizethenoiserejectioncharacteristicsoftheRGBvideooutputs,itisthen recommendedtoroutetheRGBvideooutputsonthetoplayeroverasolidgroundplane.
•TheroutingfortheRGBsignalsshouldbeassimilaraspossible(i.e.,sameroutinglayer,samenumber ofvias,sameroutinglengthandsamebends).
•RoutetheRGBdatatracesignalsandtwosyncsignals(VDHSYNCandVDVSYNC)asasingle-endedsignal withatraceimpedanceof55Ω.
Table22: LCDtraceproperties
Table23: LCDsignaltype,topologyandreferenceplane
LCD connector
RRS
R
SOM DDR3SODIMM Slot
SOM-6X80
Edge
fing
er
VDOUT23:0]
VDDEN
VDHSYNC
VDSYNC
VDCLK
C
LCD panel
LT
LT
LT
LT
LT
Signal Group Signal Name Trace Impedance
Trace (mil)(Width : Spacing)
Trace Mismatch Spacing to Other Signal
DataVDOUT[7:0]
55Ω±10% 5:10 1000mil 10milVDOUT[15:8]VDOUT[23:16]
ControlVDHSYNC
55Ω±10% 5:10 1000mil 10milVDVSYNC
Clock VDCLK 55Ω±10% 5:15 - -
Signal Group Signal Name Signal Type Topology Reference Plane
DataVDOUT[7:0]
Single-ended Point-to-Point Ground/PowerVDOUT[15:8]VDOUT[23:16]
ControlVDHSYNC
Single-ended Point-to-Point Ground/PowerVDVSYNC
Clock VDCLK Single-ended Point-to-Point Ground/Power
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Table24: LCDlayoutguidelines
4.5.3 LCDReferenceSchematics
Figure39:LCD reference circuitry
Signal Group Signal Name Routing LayerLength Difference (mil) Accumulated
Trace Length (LT)To Clock In Group
DataVDOUT[7:0]
Top/Bottom <500 <1000Route to Minimum
(or<6")VDOUT[15:8]VDOUT[23:16]
ControlVDHSYNC
Top/Bottom <500 <1000Route to Minimum
(or<6")VDVSYNC
Clock VDCLK Top/Bottom -- --- --
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4.6 Touch Panel InterfaceTheSOM-6X80modulefeaturesatouchpanelinterfaceforcapacitivetouchscreens.Itallowstheintegrationofthetouchscreensolutiononthecarrierboard.ThetouchpanelinterfaceisaninterfaceconnectionbetweentheSOMDDR3SODIMMslot,capacitivetouchsensorcontroller,andtouchpanelconnector.Thetouchpanelinterfacesupports4-wireand5-wirecapacitivetouchscreens.
4.6.1 TouchPanelSignalDefinitionThefollowingtableprovidesthedefinitionofthetouchpanelsignals.
Table25: Touchpanelsignaldefinition
From SOM DDR3 SODIMM Slot to Capacitive Touch Sensor ControllerSignal Name Pin # I/O Description
GPIO3 174 O TPresetsignalGPIO4 176 O TPinterruptsignal
I2C2SDA 146 O TP I²C DataI2C2SCL 148 O TP I²C Clock
From Capacitive Touch Sensor Controller to Touch Panel Connector
Signal Name Pin # I/O Description
DRIVE00 22 O CapacitivetouchICdriveline-0
DRIVE01 23 O CapacitivetouchICdriveline-1
DRIVE02 24 O CapacitivetouchICdriveline-2
DRIVE03 25 O CapacitivetouchICdriveline-3
DRIVE04 26 O CapacitivetouchICdriveline-4
DRIVE05 27 O CapacitivetouchICdriveline-5
DRIVE06 28 O CapacitivetouchICdriveline-6
DRIVE07 29 O CapacitivetouchICdriveline-7
DRIVE08 9 O CapacitivetouchICdriveline-8
DRIVE09 8 O CapacitivetouchICdriveline-9
DRIVE10 7 O CapacitivetouchICdriveline-10
DRIVE11 6 O CapacitivetouchICdriveline-11
DRIVE12 5 O CapacitivetouchICdriveline-12
DRIVE13 4 O CapacitivetouchICdriveline-13
DRIVE14 3 O CapacitivetouchICdriveline-14
DRIVE15 2 O CapacitivetouchICdriveline-15
SENSE00 31 I CapacitivetouchICsenseline-0
SENSE01 32 I CapacitivetouchICsenseline-1
SENSE02 33 I CapacitivetouchICsenseline-2
SENSE03 34 I CapacitivetouchICsenseline-3
SENSE04 35 I CapacitivetouchICsenseline-4
SENSE05 36 I CapacitivetouchICsenseline-5
SENSE06 37 I CapacitivetouchICsenseline-6
SENSE07 38 I CapacitivetouchICsenseline-7
SENSE08 39 I CapacitivetouchICsenseline-8
SENSE09 40 I CapacitivetouchICsenseline-9
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Figure40:Touchpanelroutingtopology
4.6.2 TouchPanelLayoutandRoutingRecommendations•Keeptracelengthsasshortaspossible.
• It is recommended to route the traces on the top layer.
•Theamountofviasandcornersusedforthetouchpanelsignallayoutshouldbeminimized.
Table26: Touchpaneltraceproperties
Table27: Touchpanelsignaltype,routingtopologyandreferenceplane
Table28: Touchpanellayoutguidelines
L2
Touch Panel Connector
RRS
SOM DDR3SODIMM Slot
SOM-6X80Ed
ge fi
nger
GPIO4
GPIO5
I2C3SCL
I2C3SDA
CapaciveTouch screen Capacive
Touch Sensor Controller
TP_RESET
TP_INT
TP_SCL
TP_SDA
DRIVE[15:00]
SENSE[09:00]
L2
L1
L1
L1
L1
Interface Signal Name Trace Impedance
Trace (mil)(Width : Spacing)
Trace Mismatch
Spacing to Other Signal
SOM DDR3 SODIMM slot to Touch Screen Controller
GPIO3
55Ω±10% 5:5 20mil 5milGPIO4I2C2SCLI2C2SDA
Touch screen controllerto Touch panel connector
DRIVE[23:00]55Ω±10% 5:5 20mil 5mil
SENSE[09:00]
Interface Signal Name Signal Type Topology Reference Plane
SOM DDR3 SODIMM slot to Touch screen controller
GPIO3
Single-ended Point-to-Point Ground/PowerGPIO4I2C2SCLI2C2SDA
Touch screen controller to Touch panel connector
DRIVE[23:00]Single-ended Point-to-Point Ground/Power
SENSE[09:00]
Interface Signal Name Routing Layer
Length Difference (mil)
Accumulated Trace Length (L1 + L2 = LT)
SOM DDR3 SODIMM slot to Touch Screen Controller
GPIO3
Top/Bottom - 2"GPIO4I2C2SCLI2C2SDA
Touch screen controllerto Touch panel connector
DRIVE[23:00]Top/Bottom 200mil 2"
SENSE[09:00]
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4.6.3 TouchPanelReferenceSchematics
Figure41:Touch panel reference circuitry
Carrier Board Design Guide for SOM-6X80 Module
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4.7 GPIO InterfaceTheSOM-6X80modulefeaturesaGeneralPurposeInputandOutput(GPIO)interface.
4.7.1 GPIOSignalDefinitionThefollowingtableprovidesthedefinitionoftheGPIOsignalsthatareimplementedintheSOMDDR3SODIMM slot.
Table29: GPIOsignaldefinition
4.7.2 GPIOLayoutandRoutingRecommendation
Table30: GPIOtraceproperties
Table31: GPIOsignaltype,topologyandlayoutguidelines
Signal Name Pin # I/O DescriptionGPIO0 168 IO
General Purpose GPIO
GPIO1 166 IOGPIO2 170 IOGPIO3 174 IOGPIO4 176 IOGPIO5 178 IOGPIO6 172 IOGPIO7 182 IOGPIO9 180 IOSUS_GPIO0 150 IO
General Purpose GPIO for Suspend Power DomainSUS_GPIO1 179 IO
Signal Group Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other Signal
Data
GPIO[7:0]55Ω 5:5 5mil
GPIO9SUS_GPIO0
55Ω 5:5 5milSUS_GPIO1
Signal Group Signal Name Signal Type Topology Reference Plane Accumulated Trace Length
Data
GPIO[7:0]Single-ended Point-to-Point Ground/Power 12"
GPIO9SUS_GPIO0
Single-ended Point-to-Point Ground/Power 12"SUS_GPIO1
Carrier Board Design Guide for SOM-6X80 Module
37
4.8 I²C InterfaceThe SOM-6X80 module features an I²C interface that can support up to three I²C devices.
4.8.1 I²CSignalDefinitionThefollowingtableprovidesthedefinitionoftheI²CsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table32: I²Csignaldefinition
4.8.2 I²CLayoutandRoutingRecommendation
Table33: I²Ctraceproperties
Table34: I²Csignaltype,topologyandlayoutguidelines
Signal Name Pin # I/O DescriptionI2C0SDA 138 IO I²C1 serial dataI2C0SCL 140 IO I²C1 serial clockI2C1SDA 144 IO I²C2 serial data
I2C1SCL 142 IO I²C2 serial clockI2C2SDA 146 IO I²C3 serial dataI2C2SCL 148 IO I²C3 serial clock
Signal Group Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other SignalData I2C[2:0]SDA 55Ω 5:5 5milClock I2C[2:0]SCL 55Ω 5:5 5mil
Signal Group Signal Name Signal Type Topology Reference Plane Accumulated Trace Length
Data I2C[2:0]SDA Single-ended Daisy chain Ground/Power <12"Clock I2C[2:0]SCL Single-ended Daisy chain Ground/Power <12"
Carrier Board Design Guide for SOM-6X80 Module
38
4.9 SPI InterfaceThe SOM-6X80 module features two SPI interfaces. Each SPI interface can support one master and one slave.
4.9.1 SPISignalDefinitionThefollowingtableprovidesthedefinitionoftheSPIsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table35: SPIsignaldefinition
4.9.2 SPILayoutandRoutingRecommendation
Table36: SPItraceproperties
Table37: SPIsignaltype,topologyandlayoutguidelines
Signal Name Pin # I/O DescriptionSPI0MISO 9 I MasterInput0,SlaveOutput0SPI0MOSI 11 O MasterOutput0,SlaveInput0SPI0CLK 13 O Serial Clock 0
SPI0SS0- 15 O Slave Select 0SPI1MOSI 156 O MasterOutput1,SlaveInput1SPI1MISO 164 I MasterInput1,SlaveOutput1SPI1CLK 160 O Serial Clock 1SPI1SS0- 162 O Slave Select 1
Signal Group Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other Signal
DataSPI[1:0]MISO
55Ω 5:5 5milSPI[1:0]MOSISPI[1:0]SS0-
Clock SPI[1:0]CLK 55Ω 5:10 5mil
Signal Group Signal Name Signal Type Topology Reference Plane Accumulated Trace Length
DataSPI[1:0]MISO
Single-ended Daisy chain Ground/Power <10"SPI[1:0]MOSISPI[1:0]SS0-
Clock SPI[1:0]CLK Single-ended Rs=22Ω Ground/Power <10"
Carrier Board Design Guide for SOM-6X80 Module
39
4.10 Audio InterfaceTheSOM-6X80modulefeaturesanaudiointerfaceforaudioconnectorssuchastwoLine-in,headphone,monospeakerout,rightandleftchannelspeakers,andmicrophone.
4.10.1 AudioSignalDefinitionThefollowingtableprovidesthedefinitionoftheaudiosignalsthatareimplementedintheSOMDDR3SODIMM slot.
Table38: Audiosignaldefinition
4.10.2 AudioLayoutandRoutingRecommendations•Routetheanaloganddigitaltracesignalsasfaraspossiblefromeachothertopreventnoise.
•Routetheclocktraceawayfromanyanaloginputandvoltagereferencepins.
•Isolatethecodecorputawayfromanymajorcurrentpathorgroundbounce.
•Fillwithcoppertheregionsbetweentheanalogtracesandattachedittotheanalogground.
•Fillwithcoppertheregionsbetweenthedigitaltracesandattachedittothedigitalground.
•Keeptracelengthsasshortaspossible.
Table39: Audiotraceproperties
Signal Name Pin # I/O DescriptionHPOUTR 143 O HeadphonerightchanneloutputHPOUTL 147 O HeadphoneleftchanneloutputOUT3 145 O Audio mono output
LINPUT1 157 I Leftchannelsingle-endedMicinput/LeftchannelnegativedifferentialMicinput
LINPUT2 155 I Leftchannellineinput/LeftchannelpositivedifferentialMicinput
LINPUT3 153 I Leftchannellineinput/LeftchannelpositivedifferentialMicinput/Jack detect input pin
RINPUT1 161 I Rightchannelsingle-endedMicinput/RightchannelnegativedifferentialMicinput
RINPUT2 163 I Rightchannellineinput/RightchannelpositivedifferentialMic input
SPK_OUT_R+ 133 O RightspeakerpositiveoutputSPK_OUT_R- 131 O RightspeakernegativeoutputSPK_OUT_L+ 139 O LeftspeakerpositiveoutputSPK_OUT_L- 137 O Leftspeakernegativeoutput
Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other SignalHPOUTR
55Ω±10% 8:5 5milHPOUTLOUT3 55Ω±10% 8:5 5milLINPUT[3:1]
55Ω±10% 8:5 5milRINPUT[2:1]SPK_OUT_R[+/-]
55Ω±10% 8:5 5milSPK_OUT_L[+/-]
Carrier Board Design Guide for SOM-6X80 Module
40
Table40: Audiosignaltype,topologyandlayoutguidelines
4.10.3 AudioInterfaceReferenceSchematics
Figure42:Line-in1&2referencecircuitry
Figure43:Headphone reference circuitry
Figure44:Mono speaker out reference circuitry
Signal Name Signal Type Topology Reference Plane Accumulated Trace Length
HPOUTRSingle-ended Point-to-Point Ground <10"
HPOUTLOUT3 Single-ended Point-to-Point Ground <10"LINPUT[3:1]
Single-ended Point-to-Point Ground <10"RINPUT[2:1]SPK_OUT_R[+/-]
Single-ended Point-to-Point Ground <10"SPK_OUT_L[+/-]
Carrier Board Design Guide for SOM-6X80 Module
41
Figure45:Rightchannelspeakerreferencecircuitry
Figure46:Leftchannelspeakerreferencecircuitry
Figure47:Onboard microphone reference circuitry
Carrier Board Design Guide for SOM-6X80 Module
42
4.11 SD InterfaceTheSOM-6X80modulefeaturesanSDinterfaceforSDstorage.
4.11.1 SDSignalDefinitionThefollowingtableprovidesthedefinitionoftheSDsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table41: SDsignaldefinition
Figure48:SDroutingtopology
4.11.2 SDLayoutandRoutingRecommendations•SignaltracesshouldbeaboveasolidandcontinuousgroundplanealongthepathfromSOMDDR3 SODIMM slot to SD slot.
•SD0CMDtracesignalmusthavepull-upresistorof4.7KΩ.
•SD0WPtracesignalmusthavepull-downresistorof1KΩtotheground.
•TheESDprotectionoftracesignalSD0PWRSWmustbeplacedneartheSDslot.
Signal Name Pin # I/O DescriptionSD0DATA0 25 IO Datasignal0,usedforSDinterfaceSD0DATA1 21 IO Datasignal1,usedforSDinterfaceSD0DATA2 29 IO Datasignal2,usedforSDinterfaceSD0DATA3 31 IO Datasignal3,usedforSDinterfaceSD0CMD 27 IO Commandsignal,addexternalpull-upresistorSD0CLK 19 O SD0 bus clockSD0CD 35 I SD0 CommandSD0PWRSW 33 O SD0 Power switchSD0WP 23 I SD0 write protect
L2L1
L2L1
L2L1
L1 L2
L1 L2
ESD
R
VCC33_SD0
R
SD slot
ESD SOM DDR3SODIMM Slot
SD0DATA[3:0]
SD0CMD
SD0CD
SD0PWRSW
SD0WP
SD0CLK SOM-6X80
Edge
fing
er
Carrier Board Design Guide for SOM-6X80 Module
43
Table42: SDtraceproperties
Table43: SDsignaltype,topologyandlayoutguidelines
4.11.3 SDInterfaceReferenceSchematics
Figure49:SD reference circuitry
Signal Group Signal Name Signal Type Topology Reference PlaneAccumulated Trace Length(L1 + L2 = LT)
Data SD0DATA[3:0] Single-ended Point-to-Point Ground/Power <8"
Control
SD0CMD
Single-ended Point-to-Point Ground/Power <8"SD0CDSD0WPSD0PWRSW
Clock SD0CLK Single-ended Point-to-Point Ground/Power <8"
Signal Group Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other SignalData SD0DATA[3:0] 55Ω±15% 5:5 5mil
Control
SD0CMD
55Ω±15% 5:5 5milSD0CDSD0WPSD0PWRSW
Clock SD0CLK 55Ω±15% 5:15 15mil
Carrier Board Design Guide for SOM-6X80 Module
44
Appendix A. SOMDB1 Carrier Board Reference SchematicsTheSOMDB1istheevaluationcarrierboardforSOM-6X80module.TheschematicsoftheSOMDB1carrierboardcanbeusedasanexampleofhowtodesignacarrierboardthatprovidesoptimalperformancewhenusedwiththeSOM-6X80module.Thereferencedesignsareonlyforreferencingandnottobecopied.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DVO
Block Diagram
WM8850 Processor512MB DDR38GB eMMC512KB SPI FlashVT1603A CodecGPIO
SPK
I2C1
7" LCD
1024*600
Cap-type
TouchPanel
SOM BOARD
USBH2USB HostConnector
USBH1USB HostConnector
Speaker Connector
GPIO Header
4pin
USBHD0 USB H/D
Optional
Title
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WonderMedia Technologies, Inc.
SOMDB1 A
Block Diagram
Custom
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SOMDB1 A
Block Diagram
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SOMDB1 A
Block Diagram
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MP2303ADNDCDC 5V
DCIN24V,300mA
SOM BOARD
WM8850 Processor512MB DDR38GB eMMC512KB SPI FlashVT1603A Codec
VIN(5V)
EUP2570OIR1
VGH(18V)
VGL(-6V)
VLED(9.3V)SY7200AABC
VCOM(3.9V)
VCC33
LCD+TP Module
voltage can be adjusted
SY6280AAC USB Host
DCDC
DCDC
Power Switch
VBUS(5V)
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WonderMedia Technologies, Inc.
SOMDB1 A
Cover Page
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WonderMedia Technologies, Inc.
SOMDB1 A
Cover Page
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Date: Sheet o f
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SOMDB1 A
Cover Page
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2 26Wednesday, August 08, 2018
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
WM8850 SOM IO Test Board VTS8666C
Block Diagram
Cover Page
TITLE
GPIO/I2C List Table
LCD PWR
PAGE
01
02
03
04
05
06
07
08
09
10
11
12
13
14
16
15
DDR3 SODIMM GF
USB I/F
RS-232 Output Conn
HDMI
Ethernet
Micro SD
SDIO WiFi
Debug Port & IR
SPI & I2C
GPIO_PWM
SPK & MIC
17
18
19
20
21
22
23
LCD I/F
CAP Touch - GSL1680
GM7150BC_Video_Decoder
DC-IN & WDT
NA
CCIR656 Camera
NA
NA
Source Load
LDO Switch
Illustration:
Version History 24
EMP8736VCC_WDG
APM4835KC-TRL5VIN
5VIN_EN
HT68F0025VIN_RTC
Power Tree:
MP2303ADN5VIN_RTC
DC CONN12V, 2A
USB Host x 2
PWRENVCC
SY6280AAC
USB Host x 1SY6280AAC
PWRENVCC
HDMI CONN
PWRENVCC
GN23055V_HDMI
Micro SD
VCC_WiFI
EMP8736SDIO WiFi
Debug CONN
PWRENVCC
GN2305VCC5_SPK
NS4158
GPIO3
GN2305LCD_VCC
LCD BIAS VoltageLCD backlight
VCAMD_PMU
EMP8736GM7150
33mA
RTC Battery
SPI CONN
GPIO CONN
GSL1680
VCC33
DDR3 SODIMM GF
300mA
80mA
1A
0.5A
1.5A
0.5A
VCC33_UARTSP3232
SY8086AAC200mA
PWRENVCC
DC to DC
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SOMDB1 A
Cover Page
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SOMDB1 A
Cover Page
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Cover Page
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Block Diagram
Earphone out
MIC in
Line in
WM8850 SOM
VINDC to DCFR9888
Button
USBH2
USBH1
DebugPort
Audio
USBH0
5V/1.5A
USB Host
Speaker out
RGB
HDMI
I2C
7" 1024*600GSL1680CAP Mul-Touch
USB Host
USB Host/ DeviceUSB CONN
SDIO1WiFiAP6330
TRANSFORMER
RJ45
PHY
HDMI CONN
COM2COM1 COM3
COM4
RS232 RECEIVER
RS232 RECEIVER
COM3/4COM1/2
VDIN
Video DecoderGM7150
CVBSCamera CONN
IR Receive
IR
UART0
SDIO0
Micro SD
KEY
USB CONN
USB CONN
ADAPTER12V/2A
SPI
I2C
PWM
GPIO
Reserved Header
Reserved Header
Reserved Header
Reserved Header
GPIOWatchDogHT68F002
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SOMDB1 A
Block Diagram
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SOMDB1 A
Block Diagram
Custom4 26Wednesday, August 08, 2018
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SOMDB1 A
Block Diagram
Custom4 26Wednesday, August 08, 2018
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C3
(Suspend)
PIN Shared
PIN Shared
GPIO# I/O Function
[GPIO/EXTINT ASSIGNMEMT]
GPIO0
GPIO1
GPIO7
GPIO8
GPIO9
GPIO/I2C List Table
USBOC3#
PIN Shared
N/A
[WAKEUP(INT) ASSIGNMEMT]
WAKEUP0
WAKEUP1
WAKEUP2
WAKEUP3
WAKEUP# I/O Function
SD0PWRSW
NAME I/O Function
[SD Card Power Control]
[SUSPEND GPIO ASSIGNMEMT]
SUSGPIO0
SUSGPIO1
SUSGPIO2
SUSGPIO# I/O Function
SUSGPIO3
SD1PWRSW
SD2PWRSW
SD3PWRSW
I2C Bus ASSIGNMEMT
I2C# Function Device Address Module Max.Freq(KHz)
I2C0
I2C1
I2C2
USBSW0
Note: Non-DEDICATED GPIO LIST(Refer WM8850 Datasheet for detail)
I
O
O
O
I
I
O
O
Control LCD Power
TP Reset
TP Interrupt
WiFi Host Wake BT
WiFi REG ON
Mute NS4118 Speaker
GM7150BC
Camera
TP-GSL1680
Low battery Alert(reserved)
CPU_ACTIVE
GPIO3
GPIO4
GPIO5
GPIO6
Camera PDNO
GPIO13
GPIO12 System normal boot
WiFi Wake Host
BT RST N
GM7150 PDN
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SOMDB1 A
GPIO/I2C List Table
Custom5 26Wednesday, August 08, 2018
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SOMDB1 A
GPIO/I2C List Table
Custom5 26Wednesday, August 08, 2018
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SOMDB1 A
GPIO/I2C List Table
Custom5 26Wednesday, August 08, 2018
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR3 SODIMM Golden finger
5V DC Input 1A
UART0 and 1 from WM8880
I2C Signal need external pull high
VVSYNC
VCLK
PWMOUT2
RSMRST-PWMOUT3
SUS_GPIO1
PWRBTN-
PWRENMEMPWRENVDD
WAKEUP3
LINPUT2LINPUT1
RINPUT1
LINPUT3
CIRIN
PWRENVCCWAKEUP2
HPOUTLOUT3
RINPUT2
SPK_OUT_L-SPK_OUT_L+
PWREN_MAIN
SD2DATA1
SD2DATA0
SD2DATA2
SD2CMDSD2CLK
SD2DATA3
SD2WPSD2PWRSW
I2C1SCL
SPI1SS0-SPI1MISO
SPI1CLK
SPI1MOSI
I2C2SDAI2C2SCL
I2C1SDA
PWRGDWAKEUP0
SUS_GPIO0
GPIO0GPIO1
GPIO5GPIO4GPIO3GPIO6GPIO2
GPIO7GPIO9
VDIN7
C24MOUTVDIN5
VHSYNC
SPK_OUT_R-SPK_OUT_R+
HPOUTR
VDOUT22
I2C0SDAI2C0SCL
SD2PWRSW
SD2WP
UARTD_TXUARTD_RX
UARTD_RTSUARTD_CTS
UARTC_TX
UARTC_RTS
UARTB_TXUARTB_RXUARTB_RTSUARTB_CTS
UARTA_TXUARTA_RXUARTA_RTSUARTA_CTS
SD0WP
SD0PWRSWSD0DATA3SD0DATA2
SD0DATA1
SD0DATA0SD0CMD
SD0CLKnUSBHD0-nUSBHD0+
nUSBHB-nUSBHB+
nUSBHA-nUSBHA+
nHDMIHPD
nHDMIDDCSDAnHDMIDDCSCL
nHDMICEC
NET_TX-NET_TX+
NET_RX-NET_RX+
M0_LINKM0_SPEED
USBATTA0
USBSW0USBID0
SD0CD
PWMOUT1PWMOUT0
UARTC_CTS
UARTC_RX
5VIN
VCC33
VSUS33
MICBIAS
VCC-BAT
VCC33
VSUS33
5VIN
VCC-BAT
VVSYNC20,21
VDIN420,21
VCLK20,21
PWMOUT315PWMOUT215
PWRBTN-15,22RSMRST-15,22
PWRENVDD15SUS_GPIO115,22
RINPUT116
WAKEUP315
PWRENMEM15
LINPUT116
LINPUT316LINPUT216
WAKEUP215CIRIN13
PWRENVCC7,8,09,12,15,16,20
RINPUT216
VDIN020,21VDIN120,21VDIN220,21
HPOUTL16OUT316
SPK_OUT_L-16SPK_OUT_L+16
PWREN_MAIN15
UART0TXD 13
SD2DATA1 12
UART0RXD 13
SD2DATA0 12
SD2DATA2 12
SD2CMD 12SD2CLK 12
UART1TXD 12UART1RXD 12
SD2DATA3 12
I2C1SCL 14,21
VDOUT23 18
GPIO5 15,21GPIO9 12,15GPIO7 15,16
GPIO4 15,19GPIO3 15,19
GPIO1 12,15GPIO0 12,15,22GPIO2 12,15GPIO6 15,17
SPI1SS0- 14SPI1MISO 14
SPI1CLK 14
SPI1MOSI 14
I2C1SDA 14,21I2C2SDA 14,19I2C2SCL 14,19
WAKEUP0 12,15
SUS_GPIO0 15,22PWRGD 15
VDIN520,21VDIN720,21
C24MOUT21
VHSYNC20,21
GPIO1220,22GPIO1320
SPK_OUT_R+16SPK_OUT_R-16
HPOUTR16
VDOUT9 18
VDOUT11 18
VDOUT7 18
VDOUT6 18
VDOUT5 18VDOUT4 18
VDOUT22 18
VDOUT20 18VDOUT21 18
VDOUT19 18
VDOUT15 18
VDOUT17 18VDOUT18 18
VDOUT16 18
VDOUT12 18
VDOUT14 18
VDOUT13 18
VDIN320,21
VDIN620,21
I2C0SDA 14,20I2C0SCL 14,20
nHDMID1-09
nHDMID0+09
nHDMICLK-09nHDMICLK+09
nHDMID2+09nHDMID2-09
nHDMID1+09
nHDMID0-09
UARTD_RX 8
UARTD_RTS 8UARTD_CTS 8
UARTC_TX 8
UARTC_RTS 8
UARTB_TX 8UARTB_RX 8UARTB_RTS 8UARTB_CTS 8
UARTA_TX 8UARTA_RX 8UARTA_RTS 8UARTA_CTS 8
SPI0MISO14
SPI0CLK14
SD0WP11
SD0PWRSW11SD0DATA311SD0DATA211
SD0DATA111
SD0DATA011SD0CMD11
SD0CLK11
nUSBHD0+ 7nUSBHD0- 7
nUSBHB+ 7nUSBHB- 7
nUSBHA- 7nUSBHA+ 7
nHDMIHPD09
nHDMIDDCSDA09nHDMIDDCSCL09
nHDMICEC09
NET_TX-10NET_TX+10
NET_RX-10NET_RX+10
M0_LINK10M0_SPEED10
USBSW07USBID07USBATTA07
SD0CD11
PWMOUT112,15PWMOUT015,17
VDVSYNC 18VDHSYNC 18
VDDEN 18VDCLK 18VDOUT0 18
UARTD_TX 8
UARTC_RX 8
UARTC_CTS 8
SPI0MOSI14
SPI0SS0-14
VDOUT10 18VDOUT1 18VDOUT8 18
VDOUT3 18VDOUT2 18
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SOMDB1 A
DDR3 SODIMM Golden Finger
Custom6 26Wednesday, August 08, 2018
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SOMDB1 A
DDR3 SODIMM Golden Finger
Custom6 26Wednesday, August 08, 2018
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DDR3 SODIMM Golden Finger
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V17
TestPoint_1mm
1
V15
TestPoint_1mm
1U67
071CAAAZ68B
1
C1840.1uF
PCB THICKNESS 1.0mm
J1
GF-DDR3_SODIMM_204P
A098
ODT1120
BA0109 BA1
108
CS0#114
CS1#121
CKE073
CKE174
CK0101
CK0#103 CK1
102
CK1#104
SDA200
SCL202
ODT0116
VREFDQ1
BA279 A15
78
A1480
A197 A2
96A3
95
A492
A591 A6
90
A786
A889
A985
A10/AP107
A1184
A12/BC#83
A13119
D05
D17
D215
D317
D44
D56
D616
D718
D821
D923
D1033
D1135
D1222
D1324
D1434
D1536
D1639
D1741
D1851
D1953
D2040
D2142
D2250
D2352
D2457
D2559
D2667
D2769
D2856
D2958
D3068
D3170
D32129
D33131
D34141
D35143
D36130
D37132
D38140
D39142
D40147
D41149
D42157
D43159
D44146
D45148
D46158
D47160
D48163
D49165
D50175
D51177
D52164
D53166
D54174
D55176
D56181
D57183
D58191
D59193
D60180
D61182
D62192
D63194
EVENT#198
NC2122
RESET#30
VREFCA126
TEST125
GND2
GND3
GND8
GND9
GND13
GND14
GND19
GND20
GND25
GND26
GND31
GND32
GND37
GND38
GND43
VDD175
VDD276
VDD381
VDD482
VDD587
VDD688
VDD793
VDD894
VDD999
VDD10100
VDD11105
VDD12106
VDD13111
VDD14112
VDD15117
VDD16118
VDD17123
VDD18124
SA0197
SA1201 VDDSPD199
NC177
DQM011
DQM128
DQM246
DQM363
DQM4136
DQM5153
DQM6170
DQM7187
GND44
GND48
GND49
GND54
GND55
GND60
GND61
GND65
GND66
GND71
GND72
DQS012DQS0#10
DQS129 DQS1#27
DQS247 DQS2#45
DQS364DQS3#62
DQS4137 DQS4#135
DQS5154DQS5#152
DQS6171 DQS6#169
DQS7188DQS7#186
GND127
GND128
GND133
GND134
GND138
GND139
GND144
GND145
GND150
GND151
GND155
GND156
GND161
GND162
GND167
GND168
GND172
GND173
GND178
GND179
GND184
GND185
GND189
GND190
GND195
GND196
WE#113
CAS#115
RAS#110
VTT203
VTT204
C1810.1uF
TP1
TestPoint_1mm
1
C18010uF
C322uF
V16
TestPoint_1mm
1
C1851uF
U68
071CAAAZ68B
1
TP2
TestPoint_1mm
1
C222uF
C110uF
C40.1uF
C18310uF
GND1
TestPoint_1mm
1
C18222uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB
Rset
Ilim(A)=6800/Rset(ohm)6800/6800=1A
Co-lay
Current Limit: 1.0A
Ilim(A)=6800/Rset(ohm)6800/10000=0.68A
Rset
1
0
Device
USB PORT 0 Configuration Table
HOST
USBID0
USBHA+nUSBHA+
nUSBHA- USBHA-
nUSBHB-
nUSBHB+
USBHB-
VBUS01
USBHB+
USB_VBUS
USBH0- USBHD0-USBH0+ USBHD0+
nUSBHD0+
nUSBHD0-
USBID0
USB_VBUS
USBID0
USB_VBUS
VBUS01
USBHA+
VBUS01USBHB-USBHB+
USBHA-
VCC33
VSUS33
5VIN
5VIN
nUSBHA+6
nUSBHA-6
nUSBHB+6
nUSBHB-6
nUSBHD0+6
nUSBHD0-6
USBATTA0 6 USBID06
USBSW06
PWRENVCC6,8,09,12,15,16,20
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
USB I/F
Custom7 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
USB I/F
Custom7 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
USB I/F
Custom7 26Wednesday, August 08, 2018
J270555-0003
123
M1
M2
4
C1110uF
J722TBH-0510-1208L
VBUS1
D-2
D+3
ID4
GND5
GN
DG
1G
ND
G2
GN
DG
3G
ND
G4
C810uF
ESD2CS0801S
12
C1310uF
+ CE1100uF
12
ESD3CS0801S
12
ESD6
CS0801M
12
L1ACM2012E-900-2P-T001 4
32
ESD8CS0801S
12
V18
TestPoint_1mm
1
L3ACM2012E-900-2P-T00
1 4
32
R8 1K
C141000pF
ESD7CS0801S
12
ESD5CS0801S
12
R710K_1%
R310K
ESD4CS0801S
12
R5 10K
+ CE2100uF
12
ESD9
CS0801M
12
U2
SY6280AAC
OUT1
GND2
SET3
EN4
IN5
R920K
C101000pF
C510uF
R40/X
L2ACM2012E-900-2P-T001 4
32
J470555-0003
123
M1
M2
4
C610uF
C1210uF
R2 1KR16.8K_1%
C710uF
U1SY6280AAC
OUT1
GND2
SET3
EN4
IN5
V19
TestPoint_1mm1
R60
C910uF
ESD1
CS0801M
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UART
1A or Higher
Vout=0.6*(1+R1/R2)0.6*(1+453K/100K)=3.3V
R1
R2
3.3V
COMA_RX
COMA_RTS
COMA_CTS
COMA_TXUARTA_TX
COM_A_TXCOM_A_RX
COM_A_RTSCOM_A_CTS
UARTA_RTS
UARTA_RXUARTA_CTS
COMA_RXCOMA_TXCOMA_CTSCOMA_RTS
COMB_TX
COMB_CTS
COMB_RTS
COMB_RX
COM_B_RXCOM_B_TXCOM_B_CTSCOM_B_RTS
UARTB_TXUARTB_RTS
UARTB_CTSUARTB_RX
COMB_RXCOMB_TXCOMB_CTSCOMB_RTS
COMC_CTS
COMC_TX
COMC_RX
COMC_RTS
COM_C_TXCOM_C_RX
COM_C_RTSCOM_C_CTS
COMD_CTS
COMD_TX
COMD_RX
COMD_RTS
COM_D_TXCOM_D_RX
COM_D_RTSCOM_D_CTS
COMD_RX
COMD_CTSCOMD_TX
COMD_RTS
UARTC_CTSUARTC_RX
UARTC_TXUARTC_RTS
COMC_TX
COMC_RTSCOMC_CTS
COMC_RX
UARTD_TX
UARTD_RXUARTD_CTS
UARTD_RTS
UARTA_TXUARTA_RTS
UARTA_CTSUARTA_RX
UARTB_RTSUARTB_TX
UARTB_RXUARTB_CTS
UARTC_CTS
UARTC_TX
UARTC_RXUARTC_RTS
UARTD_RX
UARTD_TXUARTD_RTS
UARTD_CTS
COM_A_CTSCOM_A_RTS
COM_A_RXCOM_A_TX
COM_B_RXCOM_B_TX
COM_A_RTSCOM_A_CTS
COM_A_TXCOM_A_RX
COM_B_RX
COM_B_RTSCOM_B_CTS
COM_B_TX
COM_C_RXCOM_C_TXCOM_C_CTSCOM_C_RTS
COM_D_RTS
COM_D_RXCOM_D_TXCOM_D_CTS
COM_C_TXCOM_C_RX
COM_D_RXCOM_D_TX
COM_B_CTSCOM_B_RTS
COM_C_RTSCOM_C_CTS
COM_D_RTSCOM_D_CTS
VCC33_UART5VIN
VCC33_UART
VCC33_UART
VCC33_UART
VCC33_UART
VCC33_UARTVCC33_UART
VCC33_UARTVCC33_UART
UARTA_TX6UARTA_RTS6
UARTA_RX6UARTA_CTS6
UARTB_RTS6UARTB_TX6
UARTB_CTS6UARTB_RX6
UARTC_TX6
UARTC_CTS6UARTC_RX6
UARTC_RTS6
UARTD_CTS6
UARTD_TX6
UARTD_RX6
UARTD_RTS6
PWRENVCC6,7,09,12,15,16,20
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1A
RS-232 Output Conn
Custom8 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1A
RS-232 Output Conn
Custom8 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1A
RS-232 Output Conn
Custom8 26Wednesday, August 08, 2018
R335 1K
C27 0.1uF
R13 33
R20 33
ES
D1
0C
S0
80
1M
12
ES
D2
1C
S0
80
1M
12
C28 0.1uF
J8HEADER 2X6
13 45 67 89 10
11 12
2
ES
D2
0C
S0
80
1M
12
J59
85205-0500N
12
G1
G2
345
R17 33
R10 33
C18610uF
R24 33
C250.1uF
U5SP3232EBEY-L
C1+1
V+2
C1-3
C2+4
C2-5
V-6
DOUT27
RIN28
ROUT29
DIN210 DIN111
ROUT112
RIN113
DOUT114
GN
D1
5V
CC
16
C19020pF
C18710uF
ES
D1
1C
S0
80
1M
12
C310.1uF
R14 33
U3SP3232EBEY-L
C1+1
V+2
C1-3
C2+4
C2-5
V-6
DOUT27
RIN28
ROUT29
DIN210 DIN111
ROUT112
RIN113
DOUT114
GN
D1
5V
CC
16
SY8086AAC
U27
EN1GND2LX3
VIN4
VFB5
R21 33
C300.1uF
ES
D2
2C
S0
80
1M
12
U6SP3232EBEY-L
C1+1
V+2
C1-3
C2+4
C2-5
V-6
DOUT27
RIN28
ROUT29
DIN210 DIN111
ROUT112
RIN113
DOUT114
GN
D1
5V
CC
16
ES
D1
2C
S0
80
1M
12
ES
D1
4C
S0
80
1M
12
C18810uFC18 0.1uF
R18 33
ES
D1
3C
S0
80
1M
12
R11 33
C200.1uF
R25 33
ES
D2
3C
S0
80
1M
12C34
0.1uF
J55
85205-0500N
12
G1
G2
345C21 0.1uF
J9HEADER 2X6
13 45 67 89 10
11 12
2
C160.1uF
R332100K
C190.1uF
V20
TestPoint_1mm
1
ES
D1
5C
S0
80
1M
12
C23 0.1uF
R15 33
R22 33
C260.1uF
ES
D2
5C
S0
80
1M
12
R334453K_1%
J58
85205-0500N
12
G1
G2
345
ES
D1
7C
S0
80
1M
12
C290.1uF R19 33
ES
D1
8C
S0
80
1M
12
R12 33
L12 ZAD-3015MES-3R3M
C32 0.1uF
C220.1uF
ES
D2
4C
S0
80
1M
12
ES
D1
6C
S0
80
1M
12
C150.1uF
C33 0.1uF
R16 33
R23 33
J57
85205-0500N
12
G1
G2
345
ES
D1
9C
S0
80
1M
12
U4SP3232EBEY-L
C1+1
V+2
C1-3
C2+4
C2-5
V-6
DOUT27
RIN28
ROUT29
DIN210 DIN111
ROUT112
RIN113
DOUT114
GN
D1
5V
CC
16
C17 0.1uF
C1891000pF
C240.1uF
R333100K_1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI
In Pair Pair to Pair
nHDMID[2:0]+/-
Do not change.
ESD Component can not be costdown!
nHDMICLK+/-
Notice: ESD components place near HDMI connector.
HDMI Port
HDMICLK+/-
For HDMI Logo:
HDMID[2:0]+/-< 5 < 100
LT < 3"
(5:7:5)
Do not change.
For HDMI Logo: SPN7002 change to FDV301N
Signal Name
For HDMI Logo:
Closed to HDMI connector
Length Mismatch (mils)Total Length
(Width : Spacing)
HDMID1-HDMID1+
HDMID2-HDMID2+
HDMICLK-HDMICLK+
HDMID0-HDMID0+
HDMI_CECIN
HDMI_CECIN
nHDMIDDCSDAnHDMIDDCSCL
nHDMI_CECIN
nHDMIHPD
nHDMID1+nHDMID2-
HDMID1-
nHDMID2+
nHDMICLK+
nHDMID0+nHDMID0-
nHDMICLK-
nHDMID1-
HDMICLK+
nHDMID2+
HDMID0+
nHDMIDDCSCL
HDMID1+
HDMI_CECIN
HDMIDDCSCL
nHDMIDDCSDA
nHDMID0-
nHDMID0+
HDMIDDCSDAHDMIDDCSCL
HDMID2+
HDMIDDCSDA
HDMIHPD
HDMIDDCSDAHDMIDDCSCL
HDMID0-
HDMID2-
HDMID1-
HDMICLK-
HDMIHPDnHDMIHPD
HDMID2-
HDMICLK-
nHDMID1+
nHDMID1-
nHDMID2-
nHDMICLK+
nHDMICLK-
HDMID0-
HDMID1+
HDMID2+
HDMICLK+
HDMID0+
VCC33VCC33
VCC33VCC33
5V_HDMI
VCC33
5V_HDMI
VCC33
5V_HDMI
5VIN
VCC33
nHDMICLK- 6
nHDMID0+ 6nHDMID1- 6nHDMID1+ 6nHDMID2- 6nHDMID2+ 6
nHDMICLK+ 6
nHDMICEC 6,09
nHDMID0- 6
nHDMIHPD 6,09
nHDMIDDCSCL 6,09nHDMIDDCSDA 6,09
nHDMIDDCSDA6,09
nHDMIDDCSCL6,09
nHDMIHPD6,09
nHDMICEC6,09
PWRENVCC6,7,8,12,15,16,20
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
HDMI
Custom09 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
HDMI
Custom09 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
HDMI
Custom09 26Wednesday, August 08, 2018
R31 100
R3520K
ESD28CS0801M
12
D2
RB521S-H
AK
V21
TestPoint_1mm
1
R3847K
Q4L2N7002LT1G
G
DS
C371uF
L5ACM2012E-900-2P-T001 4
32
R34 100
C390.1uF
Q2
LMBT3904LT1G
1
23
R332K
L7ACM2012E-900-2P-T001 4
32
ESD29CS0801M
12
Q1SM2307PSAC-TRG
G
D S
R371M
R36 100
D1
RB551V-30/X
A K
J10
HD119F-3A05204123456789
10111213141516171819
G1
G2
G4
G3
R292K
ESD27CS0801M
12
D5
RB521S-H
AK
R28 1K
Q3L2N7002LT1G
G
DS
D3 CS0806S
2
G1
45
1
67
910
C351uF
R27
1K
R322K
L4ACM2012E-900-2P-T001 4
32
L6ACM2012E-900-2P-T001 4
32
ESD30CS0801M
12
D4 CS0806S
2
G1
45
1
67
910
R302K
C361uF
C380.1uF
R26100K
ESD26CS0801M
12
Q5L2N7002LT1G
G
DS
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Ethernet
Active
Speed
For SOM-6X80 R582 Need to Mount (20180221)
M0_LINK
NET_TX+
NET_TX-
RX+NET_RX+
NET_RX-
TX-
TX+
RX-
CMT5
TX-TX+
M0_SPEED
RX+
RX-
VCC33
VCC33
NET_TX-6
M0_LINK 6M0_SPEED 6
NET_RX-6
NET_RX+6
NET_TX+6
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Ethernet
Custom10 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Ethernet
Custom10 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Ethernet
Custom10 26Wednesday, August 08, 2018
R582
0/X
R39 75_1%
R43 560
Y G
J11MRJN-11T54RS
M1G1
M2
G2
12345678
910
11
12
R44 560
D7BTUC05VD323B/X
12
R4075
C401000pF
D6BTUC05VD323B/X
12 R41
75
R42 75_1%
T1 TS8121ALF
TX+16
TX-14
CT315
RX+11
RX-9
CT410
TD+1
CT12
TD-3
RD+6
CT27
RD-8
C410.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Micro SD
low RDS
Please near SD Card
SD0DATA2
SD0DATA1SD0DATA0
SD0DATA3SD0CMD
SD0CD
SD0CLK
SD0CMD
VCC33_SD0
VCC33
VCC33_SD0
SD0WP6
SD0PWRSW6
SD0CMD6SD0DATA36SD0DATA26
SD0CLK6
SD0DATA16SD0DATA06
SD0CD6
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Micro SD
Custom11 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Micro SD
Custom11 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Micro SD
Custom11 26Wednesday, August 08, 2018
R45 33
ESD47CS0801S
12
C440.1uF
ESD48CS0801S
12
Q6SM2307PSAC-TRG
G
DS
ESD49CS0801S
12
C420.1uF
MR01A-01211J12
CARD DETECT9
DAT21
CD/DAT32
CMD3
VDD4
CLK5
VSS6
DAT07
DAT18
G1G1
G2G2
G3G3
G4G4
ESD50CS0801S
12
ESD51CS0801S
12
ESD46CS0801S
12
C431uF
ESD52CS0801S
12
R47 1K
V22
TestPoint_1mm
1
R46 4.7K
ESD31CS0801M
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Wi-Fi
External 32K input
2.2uF : DCR 0.06 OHM IDC 1.60A
AP6181/AP6330 : 0ohmESP8089: 200ohm
Place close, route short.
- default
C153AP6181/AP6330 : 10pFESP8089: 5.6pF
26MHZ : +/-10 PPM 10PF ESR <40 OHM
Co-lay Design
ESP8089(COB): 2.4GHz WiFiAP6181 : 2.4GHz WiFiAP6330 : 3-in-1 combo 2.4GHz/5GHz WiFi+BT+FM
Ampak 12*12 Module
AP6181/AP6330 : OSC2 26MHzC35/C36 3.9pFR232 100ESP8089:OSC2 40MHzC35/C36 15pFR232 0
VOUT =[ (R1 + R2)/ R2 ]× 1.207[(73.2K+42.2K)/42.2K]*1.207=3.3V
SD_CLK
SD_D0SD_D1
32K768HZ
XTAL26M_I
XTAL26M_O
BT_WAKE_HOST
WAKE_HOST
SD_D2
SD_D3
SD_CMD
WL_REG_ON
SD_CLK
SD_D0
SD_D1
XTAL26M_O
XTAL26M_I
WL_WAKE_HOST
BT_WAKE_HOSTHOST_WAKE_BT
32K768HZ
WIFI_BT_ANT
WL_REG_ON
TXD
RXD
RTS
CTS
CTS
RTS
WL_WAKE_HOST
RXD
SD_D3SD_D2
SD_CMD
TXD
HOST_WAKE_BTWAKE_HOST
VCC_WIFI
VCC_WIFI
VCC_WIFI
VCC_WIFI
VCC_WIFI
5VIN VCC_WIFI
VCC33
WAKEUP06,15
PWMOUT1 6,15
UART1RXD6
SD2CLK6
SD2DATA36SD2DATA26
SD2DATA16SD2DATA06
SD2CMD6
GPIO26,15
GPIO9 6,15
GPIO16,15
GPIO06,15,22
PWRENVCC 6,7,8,09,15,16,20
UART1TXD6
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
SDIO WiFi
Custom12 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
SDIO WiFi
Custom12 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
SDIO WiFi
Custom12 26Wednesday, August 08, 2018
R53 0/X
R52100K/X
C494.7uF
R573 0/X
R51 100
D10 RB521S-HAK
C5410pF/X
R68 0
R62 0
R50100K
R65 0
D8 RB521S-HAK
R71 0
R69 0
TP78
TestPoint_1mm
1
R48 73.2K_1%
R55 4.7K
U7
SGM2019-ADJYN5G/T
VIN1
GND2
EN3
FB4
VOUT5
C5710pF
C604.7uF
R63 0
R60 0R59 0/X
OSC1
26MHz
GND4
11
33
GND2
R66 0
C6110pF
C511uF
R4942.2K_1%
R70 0
C47 12pF
C521uF
N_VDDSWPIO____45N_VDDSWP_OUT__46N_VDDSWP_IN___47
AP6181/AP6330U8
XT
AL_O
UT
11
BT
_V
IO/N
_H
OS
T_W
AK
E8
BT
_H
OS
T_W
AK
E7
VB
AT
9P
CM
_O
UT
25
SDIO_DATA_CLK17
SDIO_DATA_214
SDIO_DATA_018
SDIO_DATA_CMD16
SDIO_DATA_315
WL_HOST_WAKE13
SDIO_DATA_119
UART_RTS_N41
GP
S_R
F32
VDDIO22
LP
O24
VIN
_LD
O23
VIN_LDO_OUT21
GND36
BT_RST_N34
N_I2C_SDA35
N_I2C_SCL37
N_REG_PU38
TX239
TX140
XT
AL_IN
10
WL_B
T_A
NT
2
TC
XO
_IN
30
GN
D3
GN
D1
PC
M_S
YN
C28
PC
M_C
LK
26
PC
M_IN
27
N_W
AK
E5
BT
_W
AK
E6
WL_REG_ON12
VD
D_T
CX
O29
GN
D31
GN
D33
UART_TXD42
GND20
UART_RXD43
UART_CTS_N44
FX
_R
X4
C451uF
C5510pF/X
R5720K
C48 12pFV23
TestPoint_1mm
1
L8
ZAD-3015MES-4R7N
C620.1uF
OSC2
32.768KHz
E/D1
GND2
OUT3
VDD4
C584.7uF
R64 0
C461uFR572 0
D9 RB521S-HA K
J13SMA8400M-0000
1
2345
R54 0
R67 0
R61 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Debug Port and IR
Use the same direction connect wire
Co-lay With IR1.
CIRIN
UART0TXDUART0RXD
CIRIN CIRIN
VCC33
VCC33
VSUS33VSUS33
VSUS33
CIRIN 6
UART0TXD 6UART0RXD 6
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Debug Port and IR
A13 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Debug Port and IR
A13 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Debug Port and IR
A13 26Wednesday, August 08, 2018
R7210K/X
IR1FM-9038LM-5DN
VOUT1 GND2 VCC3
J16HEADER_1X3
21
3
J1585204-0400L
12
G1
G2
34 C63
0.1uF
J142211S-04G-BK-F2
1
34
2
C641uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPI0MOSISPI0MISOSPI0SS0-
SPI0CLK SPI1CLKSPI1MOSISPI1MISOSPI1SS0-
I2C0SDAI2C0SCL
I2C1SDAI2C1SCL
I2C2SCLI2C2SDA
I2C0SCL I2C0SDAI2C1SCL I2C1SDAI2C2SCL I2C2SDA
VCC33 VCC33
VCC33
VCC33
VCC33
VCC33 VCC33
I2C0SCL6,20 I2C0SDA 6,20I2C1SCL6,21 I2C1SDA 6,21I2C2SCL6,19 I2C2SDA 6,19
SPI0CLK6SPI0MOSI6SPI0MISO6SPI0SS0-6
SPI1CLK 6SPI1MOSI 6
SPI1MISO 6SPI1SS0- 6
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
SPI & I2C
A14 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
SPI & I2C
A14 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
SPI & I2C
A14 26Wednesday, August 08, 2018
R772.2K
J17HEADER 2X6
13 45 67 89 10
11 12
2
R742.2K
R762.2K
R782.2K
R732.2K
J18HEADER_2X5
13 4
2
5 67 8
109
R752.2K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
WAKEUP2WAKEUP0
WAKEUP3
PWMOUT0PWMOUT1PWMOUT2PWMOUT3
GPIO4GPIO5
GPIO9
GPIO6GPIO7
SUS_GPIO1SUS_GPIO0
GPIO1GPIO0
GPIO3GPIO2
PWMOUT2 PWMOUT3
WAKEUP0 WAKEUP2 WAKEUP3
PWREN_MAIN
PWRENMEMPWRENVCC
PWRENVDD RSMRST-PWRGD
PWRBTN-
VCC33VCC33 VCC33
VCC33 VCC33
VCC33 VCC33 VCC33
VCC33
WAKEUP0 6,12
WAKEUP3 6WAKEUP2 6
PWMOUT16,12PWMOUT06,17
PWMOUT26PWMOUT36
GPIO4 6,19GPIO5 6,21GPIO6 6,17GPIO7 6,16GPIO9 6,12
SUS_GPIO06,22SUS_GPIO16,22
GPIO06,12,22
GPIO26,12GPIO36,19
GPIO16,12
PWREN_MAIN6PWRENVDD6PWRENMEM6PWRENVCC6,7,8,09,12,16,20
PWRGD 6RSMRST- 6,22PWRBTN- 6,22
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
GPIO & PWM
Custom15 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
GPIO & PWM
Custom15 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
GPIO & PWM
Custom15 26Wednesday, August 08, 2018
J21HEADER 2X6
13 45 67 89 10
11 12
2
R912.2K
LED4KPH-1608QBC-D
12
R892.2K
R812.2K
J19HEADER_2X5
13 4
2
5 67 8
109
LED5KPH-1608QBC-D
12
R902.2K
LED6KPH-1608QBC-D
12
LED2KPH-1608QBC-D
12
J20HEADER 2X6
13 45 67 89 10
11 12
2
R822.2K
LED3KPH-1608QBC-D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NCN Mode
Close to Amplif i er
Mute Speaker
Shortconnect i on, andshielding withGND
Onboard MIC
HPOUTR
HPOUTLLINPUT3
SPK3_P
SPK3_N
SPK3_PSPK3_N
SPKL_N
RIN1
LIN1 LINPUT1
RINPUT1
LIN2
RIN2
LINPUT2
RINPUT2
MIC1
LINPUT1
SPK3_PSPK3_N
SPKR_P
SPKR_N
SPKL_P
HPOUTLLINPUT3HPOUTR
OUT3
MIC1
VCC33
VCC5_SPK
VCC5_SPK
MICBIAS
5VIN VCC5_SPK
HPOUTR6
HPOUTL6LINPUT36
OUT36
SPK_OUT_L+6SPK_OUT_L-6
LINPUT1 6
RINPUT1 6
LINPUT2 6
RINPUT2 6
PWRENVCC6,7,8,09,12,15,20
GPIO76,15
SPK_OUT_R+6SPK_OUT_R-6
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
SPK & MIC
Custom16 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
SPK & MIC
Custom16 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
SPK & MIC
Custom16 26Wednesday, August 08, 2018
J30HEADER_1X3
21
3
C914.7uF
J29 PJ-S3127-S124
2
3
54
1
FB2BLM15AX102SN1D
R104100K
C781000pF/X
R99 36K
J282211S-02G-F2
21
C8010uF
R97 0
FB3BLM15AX102SN1D
C661000pF/X
J252211S-02G-F2
21
J232211S-02G-F2
21
FB9BLM15AX102SN1D
J4285204-0200L
12
G1
G2
ESD33
CS0801M
12
J2685204-0200L
12
G1
G2
FB5BLM15AX102SN1D
R105 1K
R101 0
FB7BLM15AX102SN1D
R1140
R1121K
ESD32
CS0801M
12
Q7LMBT3904LT1G
1
23
Q8SM2307PSAC-TRG
G
DS
J2285204-0200L
12
G1
G2
R10343K
R98 0
C821uF
R108100K
R11620K/X
C701000pF/X
C651000pF/X
R10082K
C830.1uF
+CE3 100uF1 2
ESD43CS0801M
12
J31HEADER_1X3
21
3
ESD41CS0801M
12
C89 4.7uF
FB10BLM15AX102SN1D
C771uF
R11010K
ESD44CS0801M
12
C840.1uF
R102 0
ESD42CS0801M
12
R113 1K
FB8BLM15AX102SN1D
R1170
FB6BLM15AX102SN1D
C93100pF
C791000pF
R106 0/X
C85220pF
FB4BLM15AX102SN1D
C68 0.022uF
J242211S-02G-F2
21
Q9
LMBT3904LT1G
1
23
MIC1PMO-6022PN-48KDQ
1
2 C90100pF
C751000pF
R115 2.2K
C741000pF
C92100pF
C721000pF/X
R11110K
R109 0/X
C86220pF
C88100pF
+CE4 100uF1 2
J2785204-0200L1
2
G1
G2
C731000pF/X
ESD34
CS0801M
12
C711000pF
U10
NS4158
CTRL1
Bypass2
NC3
INN4
VDD6
VO-5
VO+8
GND7
C691000pF
FB1BLM15AX102SN1D
C671000pF
R107 0C8110uF
C760.1uF
J32HEADER_1X3
21
3
C87100pF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LCD POWER
9.6V
3.897V
Co-lay with U12
uP6003AMT6
0.2V
96.8mA
96.8mA6.20.3V
Replacement:
U12
4.3
MT7184
EUP2586
R87/R88
4.3
SY7200A
6.2XR5161
94.5mA2.20.104V
93mA
93mA
0.2V
0.3V
1.2V
1.25V
U13
Replacement:
MT7140
100K_1%
1.2V 105K_1%STI3540
R198
105K_1%
EUP2570
LED Backlight Driver
R2
R1
Vout=1.25*(1+R1/R2)1.25*(1+100/15)=9.58V
Vfb = 0.2V
9.3V/120mA3P6S
R93 = 240 ohms for LPT Panel
CAP0402
CAP0402
CAP0402
CAP0402
CAP0402
CAP0402
RES0402
RES0402
RES0603 RES0603
RES0402
BL_LX
BL_FB BL_EN
BL_FB
BL_LX
BL_EN
AVDD
VGH
AVDD
VGL
VCOM
AVDDLCD_VCC
LCD_VCC
VCC33
5VIN
LCD_VCC
LCM_LEDA 18
LCM_LEDK 18
GPIO66,15
PWMOUT06,15
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
LCD PWR
Custom17 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
LCD PWR
Custom17 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
LCD PWR
Custom17 26Wednesday, August 08, 2018
J33HEADER_1X2_2.54MM/X2
1
R129820_1%
R126 0RES0402
C1091uF
R1363.3
R1271K
R12120KRES0402
C1010.1uF
R13415K_1%RES0402
C1061uF/16V/X5R
C971uF/16V/X5R
R13315K_1%/XRES0402
R125 1.2K
C1130.1uF
V4
TestPoint_1mm
1
R1373.3
C108 0.01uF/XCAP0402
Q10SM2307PSAC-TRG
GDS
C10210uF/16V/X5RCAP0805
D16SSM5818SGP
A K V5TestPoint_1mm
1
C952.2uFCAP0603
D13
LBAT54SLT1G
2
3
1
R119100K
R130 1K/X
U17
SY7200AABC
LX1
GND2
FB3
EN4 OVP
5IN6
C1031uF/16V/X5R
C1072.2uFCAP0603
V6TestPoint_1mm
1
C11210uF
R123100K_1%RES0402
R132 1KR131100K
V24
TestPoint_1mm
1
C11010uF/16V/X5RCAP0805
C10410uF
R138100K
D15SSM5818SGP
A K
U15
EUP2570OIR1
SW1
GND2
FB3
EN4
IN5
R128 10K
C1110.1uF
C98 1uF/16V/X5R
D11
LBAT54SLT1G
2
3
1
R118 1K
R120 100_1%
R12210K
V3
TestPoint_1mm
1
U16
EUP2586OIR1/X
SW1
GND2
FB3
EN4
IN5
L9ZAD-3015MES-4R7N
C962.2uFCAP0603
C94 1uF/16V/X5R
D14
MMVZ5235BGP
AK
V1
TestPoint_1mm
1
D12
MMSZ5248B-TP
AK
C10510uF
C1001uF/16V/X5R
Q11
LMBT3904LT1G
1
23
V2
TestPoint_1mm
1
R12410K/XRES0402
L10ZAD-3015MES-4R7N
C99 2.2uFCAP0603
R135 0RES0402
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TOP Contact Place TOP Layer
Top Contact
MODEDITH
RESET
UPDNSHLR
MODELCD_ENLCD_VSYNCLCD_HSYNCLCD_B7LCD_B6LCD_B5LCD_B4LCD_B3LCD_B2LCD_B1
LCD_G7LCD_G6LCD_G5LCD_G4LCD_G3LCD_G2
LCD_R7LCD_R6LCD_R5LCD_R4LCD_R3LCD_R2
LCD_PCLK
SHLRUPDN
RESET
DITH
LCM_LEDA
LCM_LEDK
VCOM
VCOM
LCD_R4
LCD_R7LCD_R6LCD_R5
LCD_R2LCD_R3
LCD_B7
LCD_B5LCD_B4
LCD_B6
LCD_EN
LCD_HSYNCLCD_VSYNC
LCD_PCLK
LCD_B0
LCD_G1LCD_G0
LCD_R1LCD_R0
LCD_B2LCD_B3
LCD_B1LCD_B0
LCD_G3LCD_G2
LCD_G7LCD_G6
LCD_G4LCD_G5
LCD_G1LCD_G0
LCD_R1LCD_R0
VCOM
VCOM
AVDD VGL
VGH
VCC33
VCC33
VCC33
LCM_LEDA17
LCM_LEDK17
VDHSYNC6VDVSYNC6
VDOUT16VDOUT06
VDDEN6
VDOUT76VDOUT66VDOUT56
VDOUT236
VDOUT46
VDOUT216
VDOUT196VDOUT186
VDOUT226
VDOUT206
VDCLK6
VDOUT26VDOUT36
VDOUT106
VDOUT156
VDOUT116
VDOUT146
VDOUT126VDOUT136
VDOUT96VDOUT86
VDOUT176VDOUT166
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
LCD I/F
Custom18 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
LCD I/F
Custom18 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
LCD I/F
Custom18 26Wednesday, August 08, 2018
TP29 TestPoint_1mm1
TP4 TestPoint_1mm1
TP21 TestPoint_1mm1
TP16 TestPoint_1mm1
R14810K
TP31 TestPoint_1mm1
J3450541-05001-002
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
GNDG1
GNDG2
TP10 TestPoint_1mm1
TP28 TestPoint_1mm1
TP22 TestPoint_1mm1
R139 0
RN4 1001 23 45 67 8
R141 100
RN2 1001 23 45 67 8
TP23 TestPoint_1mm1
R14610K
TP17 TestPoint_1mm1
C114100pF
TP5 TestPoint_1mm1
C1180.1uF/25V
TP24 TestPoint_1mm1
TP11 TestPoint_1mm1
R15010K/X
R142 100
RN5 1001 23 45 67 8
C1170.1uF/25V
R15110K/X
TP25 TestPoint_1mm1
C1160.1uF/25V
R152 10K
TP18 TestPoint_1mm1
TP6 TestPoint_1mm1
TP26 TestPoint_1mm1
TP12 TestPoint_1mm1
R140 100
TP19 TestPoint_1mm1
C1151uF
TP7 TestPoint_1mm1
TP13 TestPoint_1mm1
TP30 TestPoint_1mm1
C121 1uF
TP20 TestPoint_1mm1
TP8 TestPoint_1mm1
TP14 TestPoint_1mm1
R14510K
C1201uF
RN1 1001 23 45 67 8
R14910K/X
TP15 TestPoint_1mm1
R143 0
TP9 TestPoint_1mm1
TP3 TestPoint_1mm1
RN6 1001 23 45 67 8
R14410K/X
TP27 TestPoint_1mm1
RN3 1001 23 45 67 8
R14710K
C11920pF/X
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAP closed to Connector Pins.
Touch Panel
P1 GNDP2-P11 Y9-Y0P12,P13 GNDP14-P29 X0-X15P30 GND
TOP
1.8V IO
301
Max 9mA
Top Contact
FOR CAP TOUCH PANEL
GSL1680Q40
TP_RESET
TP_SDATP_SCL
SENSE01SENSE00TP_INT
SENSE06SENSE05SENSE04SENSE03SENSE02
SENSE09SENSE08SENSE07
TP_INTTP_RESET
TP_SCLTP_SDA
DRIVE15
DRIVE13DRIVE14
DRIVE09DRIVE10DRIVE11DRIVE12
DRIVE05DRIVE06DRIVE07DRIVE08
DRIVE01DRIVE02DRIVE03DRIVE04
SENSE01SENSE00
DRIVE00
SENSE05SENSE04SENSE03SENSE02
SENSE09SENSE08SENSE07SENSE06
DRIVE02DRIVE03
DRIVE14
DRIVE00DRIVE01
DRIVE10DRIVE11DRIVE12DRIVE13
DRIVE09
DRIVE06DRIVE07DRIVE08
DRIVE04DRIVE05
DRIVE15
I2C2SCLI2C2SDA
TP_RESET
TP_SDA
TP_SCL
TP_INT
TP_30V
TP_18V
TP_30V
TP_30VVCC33
TP_30V
I2C2SCL 6,14I2C2SDA 6,14
GPIO4 6,15GPIO3 6,15
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
CAP Touch - GSL1680
Custom19 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
CAP Touch - GSL1680
Custom19 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
CAP Touch - GSL1680
Custom19 26Wednesday, August 08, 2018
C1240.1uF
TP55 TestPoint_1mm1
R158 0/X
TP58 TestPoint_1mm1
TP43 TestPoint_1mm1
TP42 TestPoint_1mm1
TP49 TestPoint_1mm1
TP50 TestPoint_1mm1
TP36 TestPoint_1mm1
TP52 TestPoint_1mm1
TP48 TestPoint_1mm1
R574100K/X
TP37 TestPoint_1mm1
R153 0
TP32 TestPoint_1mm1
TP51 TestPoint_1mm1
FB11BLM15AX102SN1D
C1234.7uF
C1224.7uF
R154 0
TP39 TestPoint_1mm1
V7
TestPoint_1mm
1
R84 33
R155 22
TP38 TestPoint_1mm1
R86 33
TP44 TestPoint_1mm1
V8
TestPoint_1mm
1
C1284.7uF
C1251uF
R156 22
J60FPC05006-04200
11
22
33
44
G1
G1
G2
G2
55
66
J359631S-50Y913
34567
2
9101112131415161718192021222324252627282930
8
1G1
G2
C1270.1uF
TP45 TestPoint_1mm1
U18
AVDD1
AVDD21
GND30
VDDIO16
GND10
GND18
SDA12
SCL13
GPIO014
GPIO115
IRQ17
VTNC20
SHUTDOWN19
1V8_OUT11
Y940Y839Y738Y637Y536
X123
Y031
X152X143X134X125X116X107X98X89
Y233
Y435
X022
X224
X325
X426
X527
X628
X729
Y132
GN
DG
1
Y334
TP33 TestPoint_1mm1
TP47 TestPoint_1mm1
C1261uF
R15910K
C1291uF
TP46 TestPoint_1mm1
TP53 TestPoint_1mm1
TP57 TestPoint_1mm1
TP54 TestPoint_1mm1
TP34 TestPoint_1mm1
R157 0
TP40 TestPoint_1mm1
TP35 TestPoint_1mm1
TP56 TestPoint_1mm1
C5610.1uF
TP41 TestPoint_1mm1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
R2R1
VOUT =[ (R1 + R2)/ R2 ]× 1.207[(49.9K+100K)/100K]*1.207=1.81V
CVBS_IN
GM7150_RSTB
GM7150_XTAL2
GM7150_XTAL1
CMDAT7CMDAT6
CMDAT8CMDAT9
CMDAT3
CMDAT2
CMDAT4CMDAT5
VCLK
VHSYNC
VVSYNC
GM7150_RSTB
CVBS_IN
CMVREF
CMHREF
CMCLK
GM7150_SDA
GM7150_SCL
GM7150_XTAL2
GM7150_XTAL1
VDIN0VDIN1VDIN2VDIN3
VDIN4VDIN5VDIN6VDIN7
I2C0SCL
I2C0SDA
DVDD_GM7150 AVDD_GM7150VCAMD_PMU
IODVDD_GM7150
AVDD_GM7150
AVDD_GM7150 DVDD_GM7150
IODVDD_GM7150
IODVDD_GM7150
VCAMD_PMU
5VIN
VCC33 IODVDD_GM7150
VDIN0 6,21VDIN1 6,21
VDIN3 6,21VDIN2 6,21
VDIN4 6,21VDIN5 6,21VDIN6 6,21VDIN7 6,21
VVSYNC 6,21
VHSYNC 6,21
I2C0SCL 6,14
I2C0SDA 6,14
VCLK 6,21
GPIO126,22
GPIO13 6,20
PWRENVCC6,7,8,09,12,15,16
GPIO136,20
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
GM7150BC_Video_Decoder
Custom20 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
GM7150BC_Video_Decoder
Custom20 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
GM7150BC_Video_Decoder
Custom20 26Wednesday, August 08, 2018
C14820pF
R169 0
C5650.1uF
Q14
LMBT3904LT1G
1
23
C5631uF/16V/X5R
C1410.1uF
R567 33
R168 10K
C1351uF/16V/X5R
R184 33
R170 33/XC140
1uF/16V/X5R
C1321uF
R183 0/X
R162 0/X
R1801M
C146 0.1uF
Q15SM2307PSAC-TRG
G
DS
R175 33
R568 33
C14920pF
C15130pF/X
Color:YELLOW
U22
WT-04048Y(KY)
2
1
34
U21
GM7150BC
AIP1A1
AIP1B2
PLL_AGND3
PLL_AVDD4
XTAL15
XTAL26
AGND7
RESETB8
PC
LK
/SC
LK
9
IO_D
VD
D10
YO
UT
711
YO
UT
612
YO
UT
513
YO
UT
414
YO
UT
315
YO
UT
216
YOUT117
YOUT018
DGND19
SCL21
DVDD20
SDA22
INT
RE
Q27
RE
FM
30
CH
_A
GN
D31
CH
_A
VD
D32
FID/GLCO23
VSYNC/PALI24
HS
YN
C25
AV
ID26
PD
N28
RE
FP
29
AG
ND
_1
G1
FB12BLM15AX102SN1D
V25
TestPoint_1mm
1
C138
1uF/16V/X5R
R164 10K
V28
TestPoint_1mm
1
C5620.1uF
R569 33
C136 1uF/16V/X5R
C147 0.1uF
R564 33
R171 33/X
C5641uF/16V/X5R
R179 33
J452211S-02G-F2
21
R173 0/X
C1420.1uF
C1390.1uF
R178 33
R174 37.4_1%
R17637.4_1%
R570 33
X2
14.31818MHz
GND4
11
33
GND2
C1501uF/16V/X5R
R57910K
R1810
R565 33
R172 33
C1301uF
R165100K_1%
R18210K
U19
SGM2019-ADJYN5G/T
VIN1
GND2
EN3
FB4
VOUT5
R5801K
C134 1uF/16V/X5R
R160 49.9K_1%
R177 33/X
C1371uF/16V/X5R
R571 33
R581 1K
R566 33
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place near connector.
CCIR656 CameraI2C Address:
0x42VOUT =[ (R1 + R2)/ R2 ]× 1.207[(84.5K+64.9K)/64.9K]*1.207=2.778V
CAMERA1_RESET
CAMERA1_PWDN
VDIN7
VDIN6
VDIN5
VDIN3VDIN0VDIN4
VDIN2VDIN1
CAMERA1_RESET
CAMERA1_PWDN
CAMERA1_RESET
I2C1SDAI2C1SCLVVSYNCVHSYNC
C24MOUTVCLK
VDIN7VDIN6VDIN5VDIN4VDIN3VDIN2VDIN1VDIN0
DVDD_CAM
DVDD_CAM
VDIN7 VDIN6VDIN5 VDIN4
VDIN1VDIN3
VDIN0VDIN2
VCCVID
VCCVID
VCCVIDVCC33 VCCVID
AVCCVIDVCCVID
AVCCVID
VCAMD_PMUDVDD_CAM
GPIO56,15
C24MOUT6
VCLK6,20
I2C1SCL6,14
I2C1SDA6,14
VVSYNC6,20
VHSYNC6,20
VDIN76,20VDIN56,20VDIN36,20VDIN16,20
VDIN6 6,20VDIN4 6,20VDIN2 6,20VDIN0 6,20
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
CCIR656 Camera
Custom21 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
CCIR656 Camera
Custom21 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
CCIR656 Camera
Custom21 26Wednesday, August 08, 2018
R19310K
C3660.1uF
R575 0
TP62 TestPoint_1mm1
TP66 TestPoint_1mm1
R185 33
TP67 TestPoint_1mm1
D17RB520S-30/X
A K
TP68 TestPoint_1mm1
C3674.7uF
R186 33
TP69 TestPoint_1mm1
V27
TestPoint_1mm
1
R19064.9K_1%
J3650532-02401-001
34567
2
910111213141516171819202122
8
1G1
G2
2324
TP70 TestPoint_1mm1
TP65 TestPoint_1mm1
TP71 TestPoint_1mm1
R188 84.5K_1%
C1531uF
TP60 TestPoint_1mm1
TP63 TestPoint_1mm1
R234 0
TP72 TestPoint_1mm1
C3651uF
C3644.7uF
TP73 TestPoint_1mm1
TP64 TestPoint_1mm1
U23
SGM2019-ADJYN5G/T
VIN1
GND2
EN3
FB4
VOUT5
TP74 TestPoint_1mm1
C1910.1uF
TP75 TestPoint_1mm1
C1521uF
TP61 TestPoint_1mm1
R19410K
C1560.1uF
C1540.1uF
R192 22
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Active High
Watchdog
8ms Reserved for WOLwatchdog default enable when DC12V on
watchdog programming header
WDG_RESET_IN PA6
CPU_ACTIVE PA5
RECOVERY_MODE PA4
SUS_GPIO1PA2
Reset Key
SUS_GPIO0
Power Key
I
I
I
WDO PA1 O Cut Power
ILow Power alert
WatchDog External Connect
28V 3A 360kHz 0.8VFB
VIN Range:4.5V-23V
ESD near button.
>=5s
Low for disablewatchdog.
ESD near button.
Power
ESD near button.
Recovery/Reset
X5R X5R
VOUT =[ (R1 + R2)/ R2 ]× 1.207[(73.2K+42.2K)/42.2K]*1.207=3.3V
WD_PA4
ICP_DAT
WDI
ICP_CLK
WDO
WD_PA2WDG_RESET
ICP_CLK
ICP_VDDICP_DAT
WDG_EN
CPU_ACTIVE
WD_PA3
ICP_VDDICP_DATICP_CLK
PWRBTN-
GPIO12
WD_PA3
WD_PA2
WDO
WD_PA4ICP_DAT
WDI
WDO
WDG_EN
PWRBTN-
WD_PA4
RSMRST-
ICP_VDDVCC_WDG
ICP_VDD
ICP_VDD
VCC_WDG
5VIN_RTC
SYS_12VIN
5VIN_RTC
VCC-BAT
5VIN VCC33 ICP_VDD
5VIN_RTC
5VIN
VCC33
GPIO12 6,20
SUS_GPIO1 6,15
SUS_GPIO06,15
PWRBTN- 6,15
GPIO0 6,12,15
RSMRST- 6,15
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1A
DC-IN & WDT
Custom22 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1A
DC-IN & WDT
Custom22 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1A
DC-IN & WDT
Custom22 26Wednesday, August 08, 2018
ESD36CS0801M
12
5VIN
1
R552 100K
C16647uF
D44 RB521S-H/XAK
SW2
DTSM-62N-V-T/R
1
3 4
2
C1690.1uF/25V
FID4
FIDUCIAL
1
LED8KPH-1608QBC-D
12
ICP_DAT11
MH6
MTH6_3.5N
1234 5
678
9
C1620.1uF/25V
R557 100KESD40CS0801M
12
R21342.2K_1%
C164 56pF
FID5
FIDUCIAL
1
R556 100K
C5580.1uF
C1750.1uF
C1790.1uF
MH1
MTH6_3.5N
1234 5
678
9
U66
SGM2588IYN5G/TR
VOUT1
GND2/FAULT3
EN4
VIN5
C17610nF
R20710K_1%
C5591uF
ICP_GND11
FID1
FIDUCIAL
1
R2022.2K
R578 10K
U26HT68F002
VDD1
VSS10
PA7/RES/ICPCK/INT74
PA5/INT53
PA62
PA2/INT27
PA18
PA0/ICPDA9
PA45
PA3/INT36
R206
10k
R577 0/X
R205 51K_1%
ICP_VDD11
FID6
FIDUCIAL
1
V13
TestPoint_1mm
1
C16022uF
D19LBAT54CLT1G
1
23
ICP_CLK11
FID2
FIDUCIAL
1
MH3
MTH6_3.5N
1234 5
678
9
C1770.1uF
ESD45CS0801M
12
C16122uF
R529 100
FID3
FIDUCIAL
1
SW1PS-D16L-S191
321
654
C1711uF
R576 33
R2032.2K
R530 100/X
V11
TestPoint_1mm
1
D18B340A-13/X
A K
R216 0
R210 1K_1%U25
SGM2019-ADJYN5G/T
VIN1
GND2
EN3
FB4
VOUT5
C55610uF
R201 100K/X
V9
TestPoint_1mm
1
V14
TestPoint_1mm
1
MH5
MTH6_3.5N
1234 5
678
9
R545 100
C1721uF
R2080
J41210-91-04GB01
1
34
2
R200100K
MH2
MTH6_3.5N
1234 5
678
9
R474 100/X
C1670.1uF
J46
2317SJ-02
12
J5385205-0200N
12
G1
G2
R559 33
R204 53.6K_1%
R21510K
R550 100K
C5601000pF
R214100K
C16310nF/25V
C1681000pF
V10
TestPoint_1mm
1
ESD38CS0801M
12
R198 0
C55710uF
U24
MP2303ADN-Z
BS
1
IN2
SW3
FB5
COMP6
EN7
SS8
GND4
GNDG1
R551 100K
C1703300pF
C16547uF
R218 33
L11ZPWM-6030MT-100M
D46 RB521S-HAK
MH4
MTH6_3.5N
1234 5
678
9
a b c
SW3 MSS3N-Q-TR
1 32
G1 G2G3 G4
R553 100K
LED7KPH-1608QBC-D
12
ESD39CS0801M
12
C5481000pF
R199100K
R211 73.2K_1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
NA
A23 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
NA
A23 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
NA
A23 26Wednesday, August 08, 2018
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
NA
A24 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
NA
A24 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
NA
A24 26Wednesday, August 08, 2018
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
NA
A25 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
NA
A25 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
NA
A25 26Wednesday, August 08, 2018
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Version History
Responsibility DateVersion Modify Content
Initial released.VTS8662-V0 2016/11/08Echo Zhang
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Version History
Custom26 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Version History
Custom26 26Wednesday, August 08, 2018
Title
Size Document Number Rev
Date: Sheet o f
SOMDB1 A
Version History
Custom26 26Wednesday, August 08, 2018
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