Design Entry: Schematic Capture and

VHDL

ENG2410: Digital Design

Week #4

References

– Kenneth Sort, “VHDL For Engineers”, Prentice Hall, 2009.

– Peter Ashenden, “The designer’s guide to VHDL, 2nd edition”, Morgan Kaufmann publishers, 2002.

– Douglas Perry, “VHDL”, 3rd Edition, McGraw Hill.

– Sudhakar Yalamanchili, “Introductory VHDL: From Simulation to Synthesis”, Prentice Hall, 2001.

– Sudhakar Yalamnachili, “VHDL: A Starter’s Guide”, 2nd Edition, Prentice Hall, 2005.

Design Entry

� Schematic capture– What you already did in previous labs.

� Hardware Description Language (HDL)

– VHDL

– Verilog

� Electronic System Level (ESL) Higher level possible – C-like and Java-like

» ImpulseC, HandelC, Catapult C, Vivado HLS

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Schematic Design

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What is HDL?

Hardware Description Languages (HDLs) are languages used to

� document (model), � Communicate design,� simulate, and � synthesize digital circuits and systems.

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VHDL: Introduction

• VHDL is an acronym for “VHSIC Hardware DescriptionLanguage”.

• VHSIC is an acronym for “Very High Speed IntegratedCircuits” program. It was a US government sponsored program that was responsible for developing a standard HDL.

• VHDL supports modeling and simulation of digitalsystems at various levels of design abstraction.

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Basic Modeling Concepts

B

AEInternal

Functionality

circuit

ExternalInterface

InputsOutputs

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Basic Modeling Concepts

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Basic Modeling Concepts

External Interface modeled by “entity” VHDL construct.

entity ckt1 isport (X,Y,Z : in bit;

F : out bit);end entity ckt1;

VHDL “port” construct models data input/output.

Entity name Port name

Port

Port mode

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Basic Modeling Concepts

Internal Functionality modeled by “architecture” VHDL construct

architecture behav of ckt1 isbegin

F <= X or (not Y and Z);end architecture behav;

Architecture name Entity name

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Lexical Elements

• Comments:- A comment line in VHDL is represented by twosuccessive dashes “- -”.

- A comment extends from “- -” to the end of the line.

• Identifiers:

- Identifiers are names that can be given by the user.

- rules:>> must start with an alphabetic letter.>> can contain alphabetic letters, decimal

digits and underline character “_”.>> cannot end with “_”.>> cannot contain successive “_”.

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Legal vs. Illegal Identifiers

� Valid identifiers• A, X0, counter, Next_Value

� Invalid identifiers• last@value � contains illegal character• 5bit_coutner � starts with nonalphabetic • _A0 � starts with an underline• A0_ � ends with underline• clock__pulses � two successive underlines

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Libraries

• A library refers to a collection of declarations(type, entity, sub-program) and their implementations (architecture, sub-program body).

• The actual specification of a library varies from

one simulation package to another.• In VHDL we usually use the IEEE library and have

to declare that at the beginning of our VHDL program.

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Library: Example

• For standard logic (std_logic) the basic package is ieee.std_logic_1164.

• This package defines the values and basic logicoperators for type std_logic.

• The declarations can be made visible in our model

file by :

library IEEE;Use IEEE.STD_LOGIC_1164.ALL;

Library Package 14

std_logic type Demystified

Value Meaning

‘U’ Not Initialized

‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

‘L’Weak (Weakly driven) 0.Models a pull down.

‘H’Weak (Weakly driven) 1. Models a pull up.

‘-’ Don't Care

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• Signals are used to connect different parts of a design.

• They can be thought of as “wires” in conventional sense.

• Every signal has a type.

Complete Program

-- Library DeclarationLibrary IEEE;Use IEEE.std_logic_1164;

-- Entity DeclarationEntity ckt1 is

Port (X,Y,Z : in std_logic;F : out std_logic);

end ckt1;

-- Architecture Declarationarchitecture behav of ckt1 isbegin

F <= X or not Y and Z;end architecture behav;

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VHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral(algorithmic)

• Registers• State machines• Test benches

Sequential statements

Subset most suitable for synthesis

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This circuit could be modelled as following:

f <= z or w;z <= x and y;x <= not a;w <= a and b;y <= not b;

Example 2: Signals

Internal Signals

Complete Program

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-- Library DeclarationLibrary IEEE;Use IEEE.std_logic_1164;

-- Entity DeclarationEntity ckt2 is

Port (a, b : in std_logic;F : out std_logic);

end ckt2;

-- Architecture Declarationarchitecture dataflow of ckt2 is

signal x, y, z, w;

begin f <= z or w;z <= x and y;x <= not a;w <= a and b;y <= not b;

end architecture dataflow;

Internal Signals

Bit type

• Bit is also a predefined enumerated type

type bit is (‘0’, ‘1’);

• Operations

• Logical: =, /=, <, >, <=, >=

• Boolean: and, or, nand, nor, xor, xnor, not

• Shift: sll, srl, sla, sra, rol, ror

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Mapping the Design onto Digilent FPGA Board

-- Library DeclarationLibrary IEEE;Use IEEE.std_logic_1164;

-- Entity DeclarationEntity ckt1 isPort (X,Y,Z : in std_logic;

F : out std_logic);end ckt1;

-- Architecture Declarationarchitecture behav of ckt1 isbegin

F <= X or not Y and Z;end architecture behav;

Netlist

Synthesis

Map, Place and Route

Generate Bitstream

000111010100000000011111001010101010000010100101010101010001100101010110011000

Download

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