design considerations for low power time-mode sar adc

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONSInt. J. Circ. Theor. Appl. 2014; 42:707–730Published online 3 January 2013 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.1885

Design considerations for low power time-mode SAR ADC

Hua Fan*,†, Xue Han, Sekedi B. Kobenge, Qi Wei and Huazhong Yang

Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

SUMMARY

This paper describes circuit design considerations for realization of low power dissipation successiveapproximation register (SAR) analog-to-digital converter (ADC) with a time-mode comparator. A numberof design issues related to time-mode SAR ADC are discussed. Also, noise and offset models describingthe impact of the noise and offset on the timing error of time-domain comparator are presented. The resultsare verified by comparison to simulations. The design considerations mentioned in this paper are useful forthe initial design and the improvements of time-mode SAR ADC. Then, a number of practical designaspects are illustrated with discussion of an experimental 12-bit SAR ADC that incorporates a highly dynamicvoltage-to-time converter and a symmetrical input time-to-digital converter. Prototyped in a 0.18-mm six-metalone-polysilicon Complementary Metal-Oxide-Semiconductor (CMOS) process, the ADC, at 12 bit,500 kS/s, achieves a Nyquist signal-to-noise-and-distortion ratio of 53.24 dB (8.55 effective numberof bits) and a spurious-free dynamic range of 70.73 dB, while dissipating 27.17mW from a 1.3-V supply,giving a figure of merit of 145 fJ/conversion-step. Copyright © 2013 John Wiley & Sons, Ltd.

Received 29 May 2012; Revised 18 November 2012; Accepted 20 November 2012

KEY WORDS: analog-to-digital converter (ADC); time-domain comparator; successive approximationregister (SAR); wireless sensor networks (WSNs)

1. INTRODUCTION

Low voltage and low power analog-to-digital converters (ADCs) are key elements in energy-limitedapplications, such as wireless sensor networks (WSNs) and portable instruments. In submicron CMOS,as technologies scale down, the power, speed, and area of these digital circuits will improve. Thereexists a clear trend toward op-amp-less implementation of ADCs. This is for three reasons: first, therestrictions for advanced CMOS processes make high performance amplifier design challenging;second, the operational amplifiers are inherently inefficient by drawing a constant current; andthird, op-amp circuits usually cannot swing rail-to-rail. With a limited signal swing, the samplingcapacitance must be large enough to achieve a high signal-to-noise ratio, so the low supply voltageclearly makes the analog circuit design more difficult, but it is beneficial for designers of digitalcircuits. Therefore, mixed-signal design in scaled CMOS technologies is increasingly favoringthe adoption of digital architectures as implementations for analog components. To offset someof the ADC design challenges imposed by rapidly emerging deep submicron CMOS technologies, apotential candidate to replace conventional voltage signal processing is being investigated, referredto as time-mode signal processing. The time-mode signal processing methodology uses time toperform analog-to-digital conversion instead of voltage. Because most information begins in theform of a voltage, time-mode ADCs include circuits to convert voltage signals into time signals and

*Correspondence to: Hua Fan, Division of Circuits and Systems, Department of Electronic Engineering, TsinghuaUniversity, Beijing 100084, China.†E-mail: [email protected]; [email protected]

Copyright © 2013 John Wiley & Sons, Ltd.

708 F. HUA ET AL.

process time-mode signals, and finally, the processed time-mode signals are transformed into digitalrepresentations. Time difference variables are technology independent. In other words, they do notdepend on technology constrains such as power supply, so it is easily applicable to a low voltagecircuit. Moreover, the circuits involved in the time-mode ADC are comprised of highly digitalconstruction. Therefore, it offers all the benefits of the digital CMOS technology, and it is wellsuited for leveraging the raw transistor speed of new technologies, while being insensitive tocertain scaling implications, such as reduced intrinsic gain [1].

Previously, only a few studies have been carried out to efficiently model and analyze the time-modesuccessive approximation register (SAR) ADC [2], that is, low voltage headroom, noise of time-domaincomparator in SAR ADC. In this paper, a number of design issues related to time-mode SAR ADCare discussed. Also, noise and offset models describing the impact of the noise and offset on thetime-domain comparator are presented. The results are verified by comparison with simulations. Asan example of the application of these techniques, the design of an ultra-low power SAR ADCsuitable for WSN applications is described. A typical wireless sensor node consists of an RadioFrequency (RF) front end (for wireless communication), an ADC, an optional microprocessor toprocess the collected data, and a power supply block. In these systems, the size and lifetime of abattery-powered sensor node is determined to a large extent by the battery that usually cannot berecharged [3–5]. It has been observed that one of the largest sources of power dissipation in mostcases is RF front end and ADC. Therefore, a moderate resolution analog-to-digital converter withpower dissipation of a few microwatts and sample rate in excess of 100 kS/s is required. Clearly,taking power dissipation into consideration is of paramount importance, whereas linearity is ofsecondary importance for WSN applications. A well-known example of an architecture thatachieves very high efficiency is the charge-based SAR converter, see for example [6–17]. Suchconverters have been popular in recent years, primarily because a SAR ADC typically consists ofsample-and-hold stage, digital-to-analog converter (DAC), a voltage comparator, and a SAR. Thus,the simple architecture of charge-based SAR ADC and its lack of residue amplifiers render it moreamenable to WSN applications than other Nyquist ADC architectures. Because the only analogcomponent in SAR ADC is the voltage comparator, the only component that may be replaced by itstime-mode counterpart is the voltage comparator. Therefore, the digital time-domain comparatorhas eliminated the only analog part of SAR ADC, meaning that entire SAR operation is moved todigital domain, which enables the SAR ADC to make better use of scaling in CMOS technology.Moreover, the power consumption of SAR ADC will be low as mainly dynamic power is dissipated.

The proposed time-mode SAR ADC has a completely digital implementation, thus offering theadvantages of a very low power, compact, and high speed design. The ADC, implemented in astandard 0.18-mm CMOS, consumes only 27.17 mW at 500 kS/s from a 1.3-V power supply. Thelow power consumption is achieved by a novel time-domain comparator based on [18], which,instead of operating in the voltage domain, transforms the input and the reference voltages intopulses and compares their arrival times (or phase differences) [17]. This comparator obviates thepreamplifiers, which are the only circuit blocks that draw static current in the conventional SARADC [10]. Compared with [18], this work includes fabrication results of the chip and detailedanalysis of the new features of the proposed comparator in terms of noise, offset, and precision thathave not been mentioned in [18].

This paper is organized as follows: Section 2 briefly describes the circuit design of the ADC. Section 3focuses on design considerations for time-domain comparator. Section 4 shows the experimentalresults. Section 5 discusses the measurement results. Section 6 gives plan for future improvements.Finally, Section 7 summarizes the paper and draws a short conclusion.

2. CIRCUIT DESIGN

Figure 1 shows a simplified representation of a SAR ADC, whose main components are a sample/holdstage, a SAR logic stage, an N-bit DAC, and a comparator [3]. It converts an analog value into itsdigital counterpart via a binary search algorithm. Each conversion period consists of two phases: inthe first one, the input analog voltage is sampled and held, and in the second one, the digital output

Copyright © 2013 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2014; 42:707–730DOI: 10.1002/cta

VIN

VrefDAC

CLK OUT

S&H

SAR

Comp

Figure 1. Successive approximation converter architecture.

THEORETICAL MODELS OF TIME-MODE SAR ADC 709

bit is stored in the register and returned to the DAC for the next bit conversion. Unlike pipelinedconverters, SAR ADCs only determine one bit per clock cycle. Typically, the operation of an N-bitSAR ADC needs at least N + 1 clock cycles to complete one conversion. The high power efficiencythat has been achieved with SAR ADCs is mainly due to the lack of any feedback amplifiers withinthe architecture. Moreover, the proposed SAR ADC can receive rail-to-rail input signals, which canovercome the limitation of low supply voltage in deep submicron process.

2.1. Successive approximation register analog-to-digital converter architecture

Differential structures can realize better linear performance than single-ended architectures [19–21],but with the consideration of chip area, cost, and power consumption, the single-ended architectureis adopted here. The presented 12-bit single-ended SAR ADC architecture, as shown in Figure 2,uses a capacitive split array consisting of a 6-bit main capacitive DAC, 6-bit subcapacitive DAC,and a unity coupling capacitor [17]. GND and VDD are used as reference levels, so rail-to-railsignal swing is achieved. The conversion requires 14 clock periods of the main clock: the first onefor the input sampling, 12 periods for the bit cycling, and the last one for end of conversion anddata output. During the sampling phase, as shown in Figure 3(a), the voltage Vin is stored in theentire capacitor array. Because the MSB notifies whether the input is larger or smaller than half ofthe full scale, the algorithm conversion begins by switching only the MSB capacitor to VREFP(which is VDD) and the others to VREFN (which is GND), respectively, as shown in Figure 3(b).This implies that in the MSB capacitor conversion phase, Vx settles to

Vx ¼ �Vin þ VCMþ 20484095

VREF (1)

16C 32C

VDD

GNDVIN

Vx

16C32C CC

C SA

R

D0

D1

D11

VCM

12

VCM

MSB ArrayLSB Array

A

Figure 2. Successive approximation register analog-to-digital converter block diagram.


16C 32C

VDD

GNDVIN

Vx

16C32C CC

C SA

R

D0

D1

D11

VCM

12

VCM

MSB ArrayLSB Array

A

(a)

16C 32C

VDD

GNDVIN

Vx

16C32C CC

C SA

R

D0

D1

D11

VCM

12

VCM

MSB ArrayLSB Array

A

(b)

Figure 3. The split capacitor array during (a) sampling and (b) MSB bit cycling.

710 F. HUA ET AL.

where VREF is difference of VREFP and VREFN and the comparator output will be

D11 ¼0 Vin <

VREF2

1 Vin >VREF

2

8><>: (2)

If D11 is 0, the MSB capacitor is switched to GND. If D11 is 1, the MSB capacitor is continuouslyconnected to VDD. All of the remaining decisions follow the same switching fashion, proceeding tosmaller capacitors. Finally, the voltage generated by the DAC turns out to be equal to

Vx ¼ �Vin þ VCMþ 20484095

D11þ 10244095

D10þ⋯þ 14095

D0 (3)

so the full scale of this DAC structure is VDD instead of VDD � (2N� 1)/2N as in [5] and [17], whichavoids that the value of the scaling capacitance between the two arrays is one instead of beingfractional.

The split DAC leads to an architecture with 6-bit MSB array and 6-bit LSB array, being the totalcapacitance 6.4 pF, whereas the binary capacitor array of the conventional 12-bit SAR ADC uses212 unit capacitors, leading to the total capacitance 409.6 pF. Clearly, the split ADC architecture isa good solution for low power and small-area demands. The drawback of this architecture,however, is that the floating node A will strongly influence the accuracy and linearity of ADC [22].



2.2. A novel time-domain comparator

In data converters, especially in Nyquist rate architectures, power consumption is dominated by theanalog part of the system. It is therefore worthwhile to focus design efforts on optimizing the powerconsumption of analog building blocks [23]. In SAR ADC, the comparator is often the only activeelement and consumes a large portion of the SAR ADC power [10]. Implementing low voltage lowpower SAR ADC therefore means focusing design efforts on comparator. Dramatic reductions inthe power dissipation of conventional converter can be achieved by making modifications to thetraditional implementation.

Migrating from voltage domain to time domain can accommodate highly digital circuits, so time-basedanalog-to-digital conversion has recently gained considerable attentions as a viable approach insubmicron CMOS technology mainly because of its energy efficiency and low voltage applications[24]. Figure 4 shows the concept of time-based signal processing. It consists of a voltage-to-timeconverter (VTC) and a time-to-digital converter (TDC) [1]. The input analog voltage VIN andreference voltage VCM are first converted into delayed digital pulses Ф1 and Ф2, respectively;then, the phase differences between Ф1 and Ф2 are compared using a time comparator, which isusually an edge-triggered D-type flip-flop [17], forces one output to high and the other to low, andfinally provides the comparator output.

2.2.1. Voltage-to-time converter. Figure 5 shows the proposed VTC based on [17] and [24]. Thepurpose of the VTC is to generate a time difference from an input voltage difference. Its linearitylimits the overall resolution of the ADC. Unlike the preamplifier in the conventional voltagecomparator, the VTC dissipates no static power, and it uses highly digital architecture operating ata low supply voltage. When CLK is low, the input transistor of the comparator tracks the DACsettling. During this phase, transistors M9 and M10 charge the nominally equal capacitors C1 andC2 to VDD, and nodes A and B are discharged through M1 and M2 to cancel out any residual

TDC

1

2

VIN

VCM

VTC

OUT1

OUT2

Figure 4. Concept of time-based signal processing.

CLK

M1

Vin

VDD

C2

CLK

C1

M2RD

VCMM3 M4

M10M9

M7

CLKRD

CLKCLK

POFFNOFF POFFNOFFTIN TIPM5 M6

M8

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

A B

C D

E F

Figure 5. Voltage-to-time converter.


712 F. HUA ET AL.

charge of the previous comparisons, whereas the outputs of the two VTCs are pulled to groundvoltage. When CLK makes transition to high, transistors M7 and M8 turn on, and the capacitorsbegin to discharge at a constant rate through the current generator, consisting of M3 (M4) andRD. When the voltage across C1 (C2) crosses the threshold of M12 (M17), transistors M12 andM17 are completely turned on and together with the following inverters, produce the phasedifferences. Therefore, the VTC enables the capacitor-discharging rate to be a function of the inputvoltage difference and as will be shown in Section 3.2.2, the resistor RD enables the relationbetween input voltage and current to become linear. One drawback to this resistor RD, however, isthat the voltage drop across the resistors can vary significantly with process variations, such asresistor mismatch.

In [17], the time allowed for both charging and discharging of capacitors are equal, which areboth half of the clock period. However, the following TDC typically resolves in much less timethan half of the clock period. In this proposed VTC, the discharge currents of C1 and C2 can beterminated through the added switches M5 and M6 as soon as the comparison result is available toobtain further energy reductions.

2.2.2. Time-to-digital converter. A TDC is responsible for converting a time interval between twoclock edges into a digital code. For the time-do-digital detector, an edge-triggered D-type flip-flopcan be conventionally used [17] as it is the simplest and fastest circuit, but it suffers from a largedead zone, and normally, the loads at the data and clock inputs of D-type flip-flops (DFFs) areunsymmetrical. Figure 6 shows a new TDC, and its transient plot is shown in Figure 7. While theTDC is in its reset phase, TIP and TIN are low, whereas the outputs DOP and DON are unaffected.When CLK rises, if TIN makes transition to high first, MT2 and MT16 turn on, and strong positivefeedback is enabled after a short interval, which forces MT5 and MT8 on, whereas MT6 and MT7are turned off. This causes DOP to be high and DON to be low. This TDC is completelysymmetrical as the pulses see equal loads at the TDC input [24].

The TDC transfer characteristic with metastability window ΔT is shown in Figure 8. When inputtime difference is ΔTin positive and greater than ΔT/2, then the TDC output is high. When inputtime difference ΔTin is negative and less than �ΔT/2, the TDC output is low. Otherwise, the TDCsetup time is violated, and the output may be unpredictable. To ensure that the metastability isovercome, the VTC need to be designed with an adequate voltage-to-time gain. The simulationresults have shown that the TDC can resolve time difference as low as 10 ps.

TIP

TIP

MT3

MT1

MT5

MT11

MT9

MT13

MT7

MT14

MT10

TIN

MT12 MT4

MT2

MT6

MT8

TIN

VDD VDD

VDD

DOP DON

MT16MT15

MT17 MT18

A B

Figure 6. Time-to-digital converter.


TIN

TIP

A

B

DOP

DON

Figure 7. Timing diagram of time-to-digital converter.

OUT

TIN

TMW

1

Figure 8. Time-to-digital converter transfer characteristic.


By using the VTC and the TDC described earlier, the time-based comparator enables the 12-bitADC to operate on a supply voltage as low as 1.3 V while operating up to 1MS/s.

2.3. Control logic

The control logic is driven by the system clock, system reset, and one feedback signal representingend of conversion. It generates the necessary timing signals for the different components and dataoutput strobe. The control logic and SAR together use a total of 17 DFFs and several basic logicgates. Both the shift registers and the switch drive registers are implemented using full dynamiclogic to save power.

2.4. Voltage level shifter

The proposed time-mode SAR ADC can operate on voltage as low as 0.8 V, and using bootstrappedswitch can increase the linearity of the switches but will introduce considerable complexity. On theother hand, the typical level shifter is used for simplicity [25]. Figure 9 shows a MOS-only voltageshifter used to level shift the switch drive command from a low supply of VDDL= 0.8V toVDDH= 1.4V. Before sampling, SAE is low, the output SAEN is also low, and sampling isdisabled. When SAE makes transition from low to high, the voltage at node SAEN also increases toVDDH. This level shifter uses MOS devices only.

3. DESIGN CONSIDERATIONS

Because the proposed time-domain comparator relies on VTC operation, the effect of using it for highprecision circuits needs to be characterized in the following various aspects.


SAE

VDDH

SAEN

VDDL

Figure 9. Low to high voltage level shifter [25].

714 F. HUA ET AL.

3.1. Operation at lowered power supply voltage

3.1.1. Low voltage headroom in conventional voltage comparator. Low voltage circuit designsattract much attention by its excellent power efficiency in both digital and analog circuits.Lowering the supply voltage is the most effective way to reduce power consumption assuming thatthe signal power is proportional to VDD2. A well-known issue in designing ADCs in modernprocesses is the low voltage headroom. It is worthwhile examining the underlying equations thatcapture the low voltage headroom in time-mode SAR ADC. In medium and high precisionconverters, the latch is always preceded by one or more preamplifiers, and the minimum supplyvoltage is dominated by the sum of the threshold voltages of NMOS and PMOS. For example, inFigure 10, the operating supply voltage VDD must be sufficient to keep all transistors M1–M5 inthe saturation region, and the input voltage VINP or VINN is always the common voltage VDD/2,so the relation that follows should be satisfied:

VDD2

� Vgs;M1;2 > Vov;M5 (4)

Thus, the minimum operating supply voltage VDD is

VDD > 4Vov þ 2Vth (5)

This sets the minimum supply voltage for the voltage comparator.

M1 M2

M3 M4

M5

VINNVINP

VB2

VDD

VB1

Figure 10. Typical preamplifier in voltage comparator.



3.1.2. Low voltage headroom in time-domain comparator. For the typical VTC [1], the minimumsupply voltage is determined by the required on and off state of M5 and M1. As shown inFigure 11, initially, when the input clock signal CLK is low, the capacitor C1 is set to the supplyvoltage forcing the output signal OUT to reset. At this time, because for M5 to be on, the minimumsupply voltage VDD must satisfy VDD>Vth,M5. On the rising edge of the clock, the capacitorbegins to discharge through the NMOS transistors M4 and M1 at a rate that is governed by theinput voltage Vin, which is always around the common voltage VDD/2. The output inverter (M2and M3) acts as the comparator and senses when the capacitor voltage has surpassed the inverterthreshold voltage. At this time, the minimum supply voltage must satisfy

VDD2

> Vth;M1 (6)

so the minimum supply voltage VDD is around 2Vth,M1.In conclusion, the minimum supply voltage VDD in time-domain comparator can be very close to

2Vth, which is much smaller than the conventional voltage comparator.

3.2. Error sources

This VTC functions as a gain stage for preamplification and determines the minimum resolvable voltagedifference, so the precision of the proposed time-domain comparator relies on VTC sensitivity, andthe error sources that influence the VTC sensitivity needs to be analyzed in various aspects.

3.2.1. Timing error caused by discharging rate. First, the timing error tdiff caused by discharging rateis analyzed as follows. The discharge branch can be simply modeled as shown in Figure 12. Becausethe small input difference is of interest in the VTC, analysis is performed assuming the two inputsapproach to 0. IR represents the discharge current when gate bias voltage Vin is equal to VCM.When CLK goes high, the time is defined as 0. td is the delay for VC1 to reach the threshold

C1

M1

M3

M5

M4

ACLK

Vin

M2

VDD VDD

OUT

Figure 11. Typical voltage-to-time converter [1].

RD

M3

AC1

VC1

CLK

VDD

VDD-Vth

time0

Vin VC1

CLK

VDD

M17

M16

IR

td

Figure 12. Model of voltage-to-time converter.


716 F. HUA ET AL.

voltage of the M17, which is given by

td ¼ CVth;PMOS

IR¼ RDCVth;PMOS

VR(7)

The timing error caused by discharging rate can be calculated as

tdVin ¼RDCVth;PMOS

VCM� Vgs M4� RDCVth;PMOS

Vin � Vgs M3

¼ RDCVth;PMOS Vin � VCMð ÞVCM� Vgs M4� �

Vin � Vgs M3� �

� RDCVth;PMOSΔVin

VCM� Vgs M3;4� �2

(8)

where Vth,PMOS is the threshold voltage of M17 and C1 =C2 =C.Therefore,

ΔVin �td Vin VCM� Vgs M3;4

� �2RDCVth;PMOS

(9)

3.2.2. Timing error caused by offset voltage. It is important to note that offset is also an issue intime-domain comparators. A possible mismatch between the two discharge branches causes aninput-referred offset, which is similar to the case of the offset in the conventional voltagecomparator [26]; the offset of in the comparator of the SAR ADC limits the system’s performancebecause any input signal that is smaller than the input offset leads to unpredictable ADC output.

Here, the effective transconductance Gm is used to represent a direct relation between IR and Vin [27]

Gm ¼ @IR@Vin

¼ gm1þ gmRD

(10)

where gm is the small-signal transconductance of the NMOS. Equation (10) shows that the nonlinearrelationship between IR and Vin can be compensated to a large extent by the source negativefeedback resistor RD.

With an input-referred offset voltage, VOS, as shown in Figure 13, the discharging characteristic isdetermined by

td þ td Vos ¼CVth;PMOS

IR � GmVOS(11)

RD

M3

IR

AC1

VC1

VinVos

GmVos

Figure 13. Model of voltage-to-time converter with an input-referred offset.



By using (7), the timing error caused by an input-referred offset voltage is derived as

td Vos �CVth;PMOSGmVOS

I2R(12)

To verify this offset model, we will now compare the aforementioned calculation results withsimulation results. It can clearly be seen from Figure 14 that the relation of input-referred offset andtiming error tdVos is approximately linear and the simulation results fit the calculation results.

Usually, the offset voltage can be estimated by the Monte Carlo simulation. However, the foundrycannot provide the Monte Carlo model sometimes. To find the offset error, another more simple andintuitive simulation method is employed here. Reasonable W/L ratio variation can be artificially appliedto the input transistors; then, the offset measurement is carried out by shorting all capacitors at thecomparator input to the common level VCM for offset storage (Figure 15(a)); once the offset is known,the offset measurement DAC generates a voltage successively converging to the stored offset throughthe coupling capacitor CC (Figure 15(b)). The final input word of the DAC is the digital representationof the input-referred offset of the comparator [13]. Equation (13) indicates how DAC’s outputsconverge to the stored offset, where VOS is the offset voltage of the time-domain comparator and DOFF

is the final input word of the DAC. VREF is the difference of VREFP and VREFN, Ctotal representsthe total capacitance of the main DAC, COFF is the total capacitance of the offset measurement DAC,and CC is the coupling capacitor. N is the resolution of the offset measurement DAC. The maximumoffset voltage that the offset measurement DAC can accommodate is proportional to the size of thecoupling capacitor CC.

Vxp � Vxn ¼ VOS þCOFFCCCOFFþCC

VREF

Ctotal þ COFFCCCOFFþCC

1

21DOFF;MSB þ⋯þ 1

2NDOFF;LSB

� �(13)

Using the offset measurement DAC, we can estimate the input-referred offset of the comparatorquickly according to the mismatch between the discharge currents. Figure 16 reflects the relationsbetween input-referred offsets and the mismatch between the discharge currents. From Figure 16,we can know that only 1% mismatch of discharge current will lead to 1.1mV input-referred offset.Simulation results also demonstrate that mismatch between the discharge currents deteriorates thelinearity of SAR ADC. When only 1% mismatch is applied to the input transistors, spurious-freedynamic range (SFDR) drops by 5 dB with an effective number of bit (ENOB) loss of 0.8 bit withrespect to the case where no mismatch exists in the input transistors. The results of the analysis

0 2 4 6 8 100

100

200

300

400

500

Input-Referred Offset(mV)

Tim

ing

Err

or(p

s)

Calculation results

Simulation results

Figure 14. Comparison of timing error calculation and simulation results for voltage-to-time converter withan input-referred offset.


16C 32C

VDD

GNDVIN

Vx

16C32C CC

CVCM

VCM

MSB ArrayLSB Array

Cc

VCM

VOFFSET

OFFSET Measurement

DAC

MainDAC

16C 32C

VDD

GNDVIN

Vxp

16C32C CC

CVCM

VCM

MSB ArrayLSB Array

Cc

VCM

VOFFSET

OFFSET Measurement

DAC

Vxn

MainDAC

(a)

(b)

Figure 15. Comparator offset error measurement.

0 1 2 3

1

0.2

0.4

0.6

0.8

1.4

3

5

Δ Id/ Id(%)

Inpu

t-R

efer

red

Offs

et(m

V)

Figure 16. Input-referred offset versus discharge current mismatch.

718 F. HUA ET AL.

show that the offset can indeed limit the dynamic performance of a high accuracy ADC if one does notapply any special techniques to solve this problem. If necessary, comparator offset can be canceled byusing another auxiliary calibration capacitive DAC that injects a correcting charge into the chargebalance node during the normal operation of the SAR ADC. However, the auxiliary calibrationcapacitive DAC imposes severe die area and power dissipation penalties. The goal of this paper isto propose a SAR ADC that is suitable for WSN applications where the power saving and smallarea are paramount design objectives, whereas linearity is of secondary importance. Therefore, nooffset cancelation is performed to minimize power consumption and area.



3.2.3. Timing error caused by noise. The noise contribution of the VTC is a significant factor indetermining the accuracy of the SAR ADC. The potential advantages of time-mode designs dependon their noise properties. Therefore, it is important to establish noise analysis model that providesinsight into the different sources of noise in these circuits for design purposes.

Noise currents of M3, M5, M7, and RD can be modeled by parallel current source with a power of

i2nRON

�, i2n3�

, and �i2nR , respectively.The equivalent circuit of Figure 17 is shown in the Figure 18.The output noise voltage of VTC can the calculated as follows:

�Vn out ¼�Vn in1=jwC

RD þ ro þ 2RONð Þ þ 1=jwC

¼�Vn in1

1þ j2pfC RD þ ro þ 2RONð Þ(14)

so we can obtain the output-referred noise power of two branches as follows:

�V2n out ¼

2��V2n in

1þ 2pfC RD þ ro þ 2RONð Þ½ �2 (15)

Then, the output-referred noise power integrated over the full noise bandwidth (taking the integralon both sides) is given by

�V2n out; total ¼

Z 1

0

2��V2n in

1þ 2pfC RD þ ro þ 2RONð Þ½ �2 df (16)

RD

M3

A

C1in32

inR2

4KT gm

4KT/R

Vn_out2

2RON inRON2 2KT/RON

DD

Figure 17. Equivalent circuit with noise generator.

RD

C1Vn_in2

roVn_out

2

roin32 2 inR

2 RD2

inRON2 2

(2RON)

2RON

Figure 18. Simplified circuit with noise generator.


�

720 F. HUA ET AL.

UsingR

dxx2þ1 ¼ tan�1 Eq. (20) becomes

�V2n out; total ¼ 2��V2

n in

2pC RD þ ro þ 2RONð Þ tan�1 2pfC RD þ ro þ 2RONð Þ½ � 1

0 ¼ 2KT ggmr2o þ RD þ 2RON� �C RD þ ro þ 2RONð Þ

��(17)

where k is Boltzmann’s constant, T stands for absolute temperature, and g is the noise factor, typicallyequal to 2/3. The calculated output-referred noise of VTC is 128 mV.

Now, the output-referred noise voltage can be referred to the input, and therefore, we divide

V2n out; total by the gain squared (because we are dealing with powers). Therefore, dividing by

(Gain)2, we obtain

�V2n in; total ¼�V2

n out; total

Gain2 ¼ I2RR2D

V2th;PMOS

�V2n out; total

(18)

Periodic steady state (pss) and periodic noise (pnoise) simulations are performed to verify theeffectiveness of the noise model. As expected from the noise model, the simulated output-referrednoise of VTC is 135.17 mV.

Also, because the timing domain error is of interest, the voltage domain noise should be translatedinto timing fluctuation [28].

td noise ¼�Vnout;total

SlewRate

¼ C

IR�Vn out;total

(19)

By substituting (17) to (19), the output delay error caused by noise can be obtained:

td noise ¼ C

IR

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2KT ggmr2o þ RD þ 2RON

� �RD þ ro þ 2RONð Þ

s(20)

On the basis of the aforementioned noise model, transistors and capacitors in VTC were sized toguarantee the input-referred noise is small enough.

Finally, the total timing error of all error sources can be translated into error of input-referred voltagedifference we are familiar with. By using (9) and (18), the input-referred voltage error is derived as

Verr ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiΔVinð Þ2 þ VOSð Þ2 þ�V2

n in;total

� 2r

(21)

In a conclusion, the accuracy of the VTC is mainly determined by KT/C noise voltage across C1and C2, the minimum resolvable time difference tdiff, and offset voltage of the comparator [17].The accuracy of the VTC can be improved by changing the value of C and RD. The value of C1 orC2 is determined by three conditions: resistor-capacitor (RC) time constant, the KT/C noiserequirement, and the matching accuracy. Because the required capacitance for the targeted 12-bitresolution is 800 fF, which is enough to render the KT/C noise negligible, the dominant part of theaccuracy of VTC is the error voltage ΔVin caused by time difference tdiff and the offset voltage.Offset can be on the order of 1–10mV, which is larger than root mean square (RMS) noise in most



designs. This is because, by the time the noise is referred back to the input, the gain of VTC diminishesits magnitude.

The error sources described earlier are exploited to improve linearity of SAR ADC, such as the onereported in [24]. In [24], the ADC, at 12 bit, 100 kS/s, achieves a signal-to-noise-and-distortion ratio(SNDR) of 55.6 dB (8.9 ENOB) and an SFDR of 71.4 dB. However, the SFDR at 200 kS/s drops bymore than 10 dB. In this work, emphasis is posed on analytical solutions to provide a deeper insight inthe most influential error sources. By using the theoretical models in Section 3.2, the design parametersof time-domain comparator in [24] are readjusted to enable the ADC to work at a higher samplingrate. The main modifications of circuit lie in the following three aspects: (1) in [24], a capacitor with avalue of 800 fF in time-domain comparator was used without considerations for noise and capacitormismatch. In this work, however, the capacitor is set to be 1 pF for two reasons: first, according toparameters provided by semiconductor manufacturing foundry, matching requirements for 12-bitresolution demand the value of capacitor to be larger than 1 pF. Second, with larger capacitor, the noiseperformance of VTC can be improved. (2) The timing error caused by offset voltage was reduced byadjusting the discharge current according to the analytical results in Section 3.2.2. (3) In [24], thefloating node A in Figure 2 was not purged during sampling phase; in this work, however, the floatingnode A was connected to VCM during sampling to remove any residual charge. After theaforementioned revisions, the ADC maintains over 70 dB SFDR at 12 bit, 500 kS/s, almost 13-dBSFDR improvement compared with [24], which shows that the analysis of time-mode SAR ADC inthis paper is useful for the improvement of time-mode SAR ADC.

4. EXPERIMENTAL RESULTS

The designed ADC was fabricated in a 0.18-mm six-metal one-polysilicon CMOS process with Metal-Insulator-Metal (MIM) capacitors. Figure 19 shows the microphotograph of the test chip, in which theposition of main circuit blocks is highlighted. Capacitor DACs were implemented by a MIM structurewith the unit C of 100 fF. Moreover, the total capacitance of the DAC is 6.4 pF. The active circuitsmeasure 404mm� 477mm. All measurement results described in this section were obtained at roomtemperature.

The performance test of the prototype SAR ADC was conducted using a full-swing, sinusoidal inputwith amplitude of 1.3V. Figure 20 shows the SNDR and SFDR variations of this ADC with respect tothe input frequency. In the left figure, the SAR ADC was measured at 142.86 kS/s, with the inputfrequency increased to the Nyquist frequency, the SNDR and SFDR were maintained over 53.93 dB(8.67 ENOB) and 69.01 dB at 142.86 kS/s; In the right figure, the SAR ADC was measured at 500kS/s,

SA

RD

AC

COMP

404μm

477 μm

Figure 19. Chip photograph.


0 50 100 150 200 25050

55

60

65

70

75

Input Frequency(kHz)

dB

SNDR

SFDR

10 20 30 40 50 60 7050

55

60

65

70

75

Input Frequency(kHz)dB

SNDR

SFDR

(a) (b)

Figure 20. Measured signal-to-noise-and-distortion ratio and spurious-free dynamic range versus the inputfrequency at (a) fs = 142.86 kS/s and (b) fs = 500 kS/s.

722 F. HUA ET AL.

with the input frequencies increased to the Nyquist frequency, and the SNDR and SFDRwere maintainedover 53.2 dB (8.54 ENOB) and 69.89 dB at 500 kS/s.

A fast Fourier transform (FFT) of the ADC at 142.86 kS/s is shown in Figure 21(a) (Fin = 39.7 kS/s)and 21(b) (Fin = 69.3kS/s). In the left figure, with a 39.7-kHz input, the SNDR and SFDR are 53.93 dB(8.67 ENOB) and 70.96 dB, respectively. In the right figure, the SAR ADC was measured at Nyquistinput frequency. With a 69.3-kHz input, the ADC achieves a Nyquist SNDR of 54.55 dB (8.77 ENOB)and an SFDR of 70.85 dB when it samples at 142.86 kS/s.

In Figure 22, the SAR ADC was measured at 500 kS/s. With a 69.7-kHz input, the peak SNDR andSFDR are 54.05 dB (8.69 ENOB) and 70.83 dB, respectively. In the right figure, the SAR ADC was

0 2 4 6-120

-100

-80

-60

-40

-20

0

Input Frequency(Hz)

dB

[email protected]/sSNDR=54.55dBSFDR=70.85dBENOB=8.77

0 2 4 6

x 104

x 104

-120

-100

-80

-60

-40

-20

0

Input Frequency(Hz)

dB

[email protected]/sSNDR=53.93dBSFDR=70.96dBENOB=8.67

(a) (b)

Figure 21. Fast Fourier transform plot of the analog-to-digital converter at fs = 142.86kS/s with (a) 39.7-KHzinput and (b) 69.3-KHz input.

0 0.5 1 1.5 2 2.5

x 105

-120

-100

-80

-60

-40

-20

0

Input Frequency(Hz)

dB

Fin=249.2kHz@500KS/sSNDR=53.24dBSFDR=70.73dBENOB=8.55

0 0.5 1 1.5 2 2.5

x 105

-120

-100

-80

-60

-40

-20

0

Input Frequency(Hz)

dB


(b)(a)

Figure 22. Fast Fourier transform plot of the analog-to-digital converter at fs = 500kS/s with (a) 69.7-KHzinput and (b) 249.2-KHz input.



measured at Nyquist input frequency. With a 249.2-kHz input, the ADC achieves a Nyquist SNDR of53.24 dB (8.55 ENOB) and an SFDR of 70.73 dB when it samples at 500 kS/s.

In Figure 23, the SAR ADC was measured at 1MS/s. With a 19.7-kHz input, the peak SNDR andSFDR are 53.61 dB (8.61 ENOB) and 70.62 dB, respectively. The SFDR drops by 9.3 dB with anENOB loss of 0.24-bit at the Nyquist frequency (495.1 kHz) with respect to its low frequencyvalue; this distortion is due to the nonlinearity of the input switch resistance, and the loss of SNDRis likely due to noise from the substrate and references.

Figure 24 shows the differential nonlinearity (DNL) and integral nonlinearity (INL) with respect to theoutput code in 12-bit 500 kS/s mode. The maximum DNL is +0.76LSB/�0.87LSB, and the maximum

0 1 2 3 4 5

x 105

-120

-100

-80

-60

-40

-20

0

Input Frequency(Hz)dB

Fin=495.1kHz@1MS/sSNDR=52.12dBSFDR=61.33dBENOB=8.37

0 1 2 3 4 5

x 105

-120

-100

-80

-60

-40

-20

0

Input Frequency(Hz)

dB

Fin=19.7kHz@1MS/sSNDR=53.61dBSFDR=70.62dBENOB=8.61

(a) (b)

Figure 23. Fast Fourier transform plot of the analog-to-digital converter at fs = 1MS/s with (a) 19.7-KHzinput and (b) 495.1-KHz input.

0 50 100 150 200 250 300 350 400 450 500-1

-0.5

0

0.5

1

CODE

(a)

LSB

DNL

0 50 100 150 200 250 300 350 400 450 500-3

-2

-1

0

1

2

3

CODE

(b)

LSB

INL

Figure 24. Measured differential nonlinearity and integral nonlinearity in 12-bit mode at 500 kS/s.


724 F. HUA ET AL.

INL is +2.13LSB/�2.15LSB. Mismatch of certain capacitor in LSB capacitor array may result in theasymmetry of the DNL plots. Other than that, to satisfy the demand for metal density, many disorderlymetals were intentionally added to our chip by the foundry, leading to unpredictable parasitic effects ofthe capacitor array, which may be another cause of the asymmetry of the DNL plots.

To evaluate the efficiency of the ADC, a widely used figure of merit (FOM) for normalized powerversus frequency comparison of ADCs has been defined as a ratio of sampling frequency fs todissipated power and normalized by converter resolution, where ENOB is effective number of bits [29],

FOM ¼ Power

2ENOBfs(29)

The FOM of this work corresponds to 145 fJ/conversion-step at 500 kS/s. Table I summarizes theexperimental results of the prototype chip. Recently published and commercialized CMOS ADCsare compared with the proposed ADC in Table II. This work can be compared with state-of-the-artADCs in similar technologies. What should be mentioned is that the proposed ADC is for sensorinterface applications, where chip area and power tend to dominate all other considerations. InTable II, we can see that the chip area of this work is smallest with the same technology (0.18 mm).Moreover, the power of this work is smaller than all other works at the same sampling rate of500 kS/s. Wang et al. [13] adopted the most advanced technology among all the works in Table II,but the power of [13] is almost 30 times than ours. Other than that, the power of [19] is 1.5 timesthan ours, although the resolution of [19] is only 10 bit, which demonstrates that the low powertechniques employed in this design are valuable to minimize the power of time-mode SAR ADC.

Table I. Analog-to-digital converter performance summary.

Process 0.18mm

Area 404mm� 477 mmVoltage supply (V) 1.3Input range (V) 0 ~ 1.3Resolution 12 bitSampling rate 500 kS/sSNDR (dB) (at Nyquist) 53.24ENOB (at Nyquist) 8.55SFDR (dB) (at Nyquist) 70.73Power (mW) (at Nyquist) 27.17DNL (LSB) �0.87/+0.76INL (LSB) �2.15/+2.13FOM (fJ/step) 145

Table II. Comparison of performance on several analog-to-digital converters.

BIT Process(nm) MS/s Area(mm2) SFDR(dB) Power(mW) FOM(fJ/step) ENOB

[30] JSSC 2011 12 130 22.5 0.09 90.3 3020 51.3 11.35[31] JSSC 2011 12 65 50 0.16 78 3500 52 10.7[32] IJCTA 2011 12 250 0.05 2.56 - 1683 14670 11[13] ISSCC 2010 12 45 0.5 0.168 82 800 195 11[19] ASSCC2009 10 180 0.5 0.24 75 42 124 9.4[17] ISSCC 2008 12 180 0.1 0.24 71.8 3.8 56 9.4[33] JSSC 2007 12 180 0.1 0.63 71 25 165 10.55[34] ZADCS146 12 - 0.2 - 80 5980 14600 11ZMDI datasheetThis work 12 180 0.5 0.19 70.73 27.17 145 8.55



5. MEASUREMENT RESULT DISCUSSIONS

The emphasis in this work is to provide time-domain nonideal models that may be of guidance fordesigns of time-mode ADC. Undesirable performance has no impact on the correctness oftheoretical models in Section 3.2. Possible reasons for the nonideal performance include (1) power,(2) comparator offset, (3) capacitor mismatch, and (4) technology.

First of all, the limited performance of output digital pads leads to the unsatisfactory power. Fromsimulation results, the power supply of time-mode SAR ADC can be as low as 0.8V, but the digitalpads applied do not support such low output voltage. The simulation results show that the power is11.7 mW from a 0.8-V supply at 500 kS/s, giving a FOM of 62.43 fJ/conversion-step, so there is stillspacious room for further improvement. Beyond that, the conventional inefficient ‘trial-and-error’search procedure leads to unnecessary power loss.

Second, the input-referred offset deteriorates the overall precision of the ADC. In Section 3.2.2, thesimulation results have already shown that only 1% mismatch of the discharge current will lead to1.1mV input-referred offset. A significantly popular approach to offset cancelation involves multiplestages of inefficient preamplifiers. Instead of using preamplifier, offset calibration with digitalcontrol is implemented to suppress the offset voltage by inserting unbalance capacitance at thecomparator outputs [12] or adding an extra DAC for the calibration of input-referred offset [13].Offset cancelation techniques described earlier either degrade the speed of the comparator with outputloads or increase its design complexity and area by adding extra DAC. Offset cancelation techniquesthat are more suitable for low voltage and high resolution design are expected for future design.

Third, the capacitor mismatch also degrades the linearity of the SAR ADC. The static linearity ofADC is usually limited to around 10 bit in 0.18 mm because of technology limitations. Morecomplicated common centroid layout technique may be needed in the future.

Finally, it is worth mentioning that better performance of time-mode SAR ADC can be achieved byusing more advanced technology. The simulation results in Taiwan Semiconductor ManufacturingCompany, Limited (TSMC) 65 nm CMOS technology show that the ADC, at 12 bit, 1MS/s, achievesa Nyquist SNDR of 73.35 dB (11.89 ENOB) and an SFDR of 88.88 dB, while dissipating 25mW froma 0.8-V supply, giving a FOM of 6.6 fJ/conversion-step. Considering reasonable process deviation,SFDR drops by 7 dB with an ENOB loss of 1.4 bit when 1.6% mismatch exists between the dischargecurrents; accordingly, the FOM is 17.38 fJ/conversion-step. The dynamic performance at 1MS/s is shownin Figure 25. In conclusion, if more advanced technology is applied, the advantages of time-mode SARADC can be fully expanded.

6. FUTURE IMPROVEMENTS

As a continuation of the work presented in this paper, the priority of the future improvement is todesign a more efficient SAR ADC with higher ENOB.

0 100 200 300 400 500-120

-100

-80

-60

-40

-20

0

Input Frequency(KHz)

dB


Figure 25. Fast Fourier transform plot of the analog-to-digital converter at fs = 1MS/s with 491.7-KHz input.


726 F. HUA ET AL.

6.1. Power improvement

The conventional ‘trial-and-error’ search procedure uses charge inefficiently during a conversion, if thetrilevel-based switching scheme [9] is employed in this work, and the total capacitors to realize a 12-bitDAC will be halved compared with the conventional one by using ‘trial-and-error’ procedure, asshown in Figure 26. Accordingly, the operation of digital logic during SAR ADC normal conversionwill be much simpler than the conventional counterpart. Simulation results show that the power oftrilevel-based SAR ADC is 44% of the conventional SAR ADC, whereas the area reduction of DAC isabout twice.

On the other hand, asynchronous timing control circuits can achieve low power.In the synchronous 12-bit SAR ADCs, the clock frequency should be at least 13 times higher than

sampling frequency to generate adequate control signals; as a result, this high frequency clockgenerator consumes more power than that of asynchronous circuits. However, asynchronous logicrequires additional decision circuits and may cause meta-stability.

6.2. Offset improvement

Input-referred offset is the main bottleneck in the overall precision of the ADC. Offset cancelationtechniques will inevitably increase design complexity and area. Offset improvement techniques areproposed for future SAR ADC design. As mentioned in Section 3.2.2, the input-referred offset mainlycomes from the mismatch between the discharge currents; the following theoretical analysis ofinput-referred offset will demonstrate that the mismatch between RD is the main cause of input-referredoffset. The effective transconductance Gm of Eq. (10) is rewritten as follows:

Gm ¼ gm1þ gmRD

It can be simplified into

Gm � 1RD

(22)

From Eq. (22), we can see that the resistor RD plays a role to compensate the nonlinearity betweenIR and input voltage Vin. One drawback to this resistor RD, however, is that the voltage drop acrossthe resistors can vary significantly with process variations, such as resistor mismatch, leading to aninput-referred offset.

16C

VDD

GNDVIN

Vx

16C32C CC

C

VCM

VCM

MSB ArrayLSB ArrayVCM

32C

Tri-level based architecture removes the MSB capacitor in DAC

Figure 26. Trilevel-based 12-bit successive approximation register analog-to-digital converter.



Thus, the input voltage Vin and Vin�VOS in Figure 27 can be simplified into

Vin � IRRD (23)

Vin � VOS � IR � GmVOSð Þ RD þ ΔRð Þ (24)

By merging Eqs (23) and (24), we obtain the following simplified input-referred offset voltageexpression:

VOS � IRRDΔR þ 1� �

Gm(25)

We see from this result that the input-referred offset is mainly due to the mismatch between RD.We have found that the input-referred offset caused by mismatch between resistors will be canceled

by merging two discharging branches into one, as shown in Figure 28(b). Therefore, the newlyproposed VTC with improved offset will be used to improve the resolution of SAR ADC for thenext step.

6.3. Capacitor mismatch improvement

A conventional common centroid layout may be severely affected by the edge effect. To improve thematching of capacitors, first of all, each unit capacitor will be enclosed with local dummies, which

M1

IR

A

Vout

VinVin

RD IR

M2

RD ΔR

B

GmVos

Vos

Figure 27. Model of voltage-to-time converter with an input-referred offset.

CLK

M1

Vin

VDD

C2 C1

RD

VCMM3 M4

M10M9

M7

POFFNOFFM5 M6

M8

CLK

CLK

M1

Vin

VDD

C2 C1

RD

VCMM3 M4

M10M9

M7

POFFNOFFM5 M6

M8

CLKM1

RD

CLK

(a) (b)

Figure 28. (a) Schematic of proposed voltage-to-time converter and (b) voltage-to-time converter with im-proved offset.


728 F. HUA ET AL.

provides similar conditioning to all the capacitors because the interconnects are placed outside thisenclosure leading to reduced interferences from the interconnects. Moreover, the top and bottomplates of the local dummies are connected to VDD and ground, respectively, which provideseffective supply decoupling.

6.4. Speed improvement

Considering longer term plan for higher speed, voltage-controlled delay line (VCDL)-basedtime-domain comparator [35] can be applied to SAR ADC with higher speed. As shown inFigure 29, the multistage VCDLs generate a delay difference proportional to the input voltagedifference, and the sensitivity of the VTC increases as the number of delay stages increases. In ourdesign, the one-inverter delay stage was 200 ps. The comparator can resolve in 1 ns. The highlydigital operation of VCDL-based time-domain comparator dissipates no static power consumption.

7. CONCLUSIONS

This work proposes a 12-bit time-mode SAR ADC for sensor interface applications such asenvironmental monitoring and biomedical detection systems. Efficient models of the time-modeSAR ADC were used to improve its performance. A novel time-domain comparator has beenproposed in this work, which incorporates an improved VTC structure and a new symmetricalTDC. The proposed novel digital time-domain comparator with no static power consumption hasobviated the only analog part of SAR ADC and uses highly digital architecture operating at a lowsupply voltage. At the supply voltage of 1.3 V, the 12-bit SAR ADC exhibits an ENOB of 8.77while operating at a sampling rate of 142.86 kS/s and ENOB of 8.55 while operating at a samplingrate of 500 kS/s. By using a 1.3-V supply voltage, the achieved power consumption is 27.17 mW. Itis worth mentioning that the advantages of time-mode SAR ADC can be fully expanded if moreadvanced technology applied. The power dissipation of 12-bit SAR ADC at the 1MS/s is only25 mW at 0.8 V in TSMC 65 nm CMOS technology. Considering reasonable process deviation, theFOM is 17.38 fJ/conversion-step when 1.6% mismatch exists between the discharge currents.

CLK

M3a

M2a

M1aVIN M4a

M5a

M6a M9a

M8a

M7a

VDD

TIN

M10a

M11a

M12a

M3b

M2b

M1bVREF M4b

M5b

M6b M9b

M8b

M7b

VDD

TIP

M10b

M11b

M12b

TDC COMPOUT

Figure 29. Schematic of voltage-controlled delay line-based time-domain comparator.



Finally, the factors that deteriorate the linearity and resolution are analyzed, and accordingly, relevantmeasures will be taken for performance improvement for the next step.

ACKNOWLEDGEMENTS

This work was supported by the PhD Programs Foundation ofMinistry of Education of China (No.20111011315)and the National Science and Technology Important Project of China (No. 2010ZX03006-003-01).

REFERENCES

1. Taillefer C. Analog-to-digital conversion via time-mode signal processing. PHD Thesis of McGill University 2003;35–37.

2. Lee SK, Park SJ, Park HJ, Sim JY. A 21 fJ/conversion-step 100 kS/s 10-bit ADC with a low-noise time-domaincomparator for low-power sensor interface. IEEE Journal of Solid-State Circuits 2011; 46(3:651–659.

3. Sauerbrey J, Schmitt-Landsiedel D, Thewes R. A 0.5-v 1-mw successive approximation ADC. IEEE Journal ofSolid-State Circuits 2003; 38(7):1261–1265.

4. H de Man. Ambient intelligence: gigascale dreams and nanoscale realities. In IEEE International Solid-State CircuitsConference (ISSCC). 2005; 1:29–35.

5. Lee SK, Park SJ, Park HJ, Sim JY A 1.3 mW 0.6V 8.7-ENOB successive approximation ADC in a 0.18 mm CMOS.In 2009 Symposium on VLSI Circuits Digest of Technical Papers. 2009; 242–243.

6. Cranninckx J, van der Plas G. A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in90nm digital CMOS. In IEEE International Solid-State Circuits Conference (ISSCC). 2007; 246–247.

7. Shikata, A, Sekimoto R, Kuroda T, Ishikuro H. A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-levelcomparator in 40 nm CMOS. IEEE Journal of Solid-State Circuits, 2012; 47(4):1022–1030.

8. Cho S-H, Lee C-K, Kwon J-K, Ryu S-T. A 550-mW 10-bit 40-MS/s SAR ADC with multistep addition-only digitalerror correction. IEEE Journal of Solid-State Circuits 2011; 46(8):1881–1892.

9. Zhu Y, Chan C-H, Chio U-F, Sin S-W,U S-P, Martins R-P, et al. A 10-bit 100-MS/s reference-free SAR ADC in90 nm CMOS. IEEE Journal of Solid-State Circuits 2010; 45(5):1111–1121.

10. Cho, TS, K-J Lee, J Kong, AP Chandrakasan. A 32-mW 1.83-kS/s carbon nanotube chemical sensor system. IEEEJournal of Solid-State Circuits 2009; 44:2348.

11. van Elzakker M, van Tuijl E, Geraedts P, Schinkel D, Klumperink E, Nauta B. A 1.9 W 4.4 fJ/conversion-step, 10 bit, 1MS/s charge redistribution ADC. In IEEE International Solid-State Circuits Conference (ISSCC). 2008; 244–245.

12. van der Plas G, Decoutere S, Donnay S. A 0.19pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm digitalCMOS process. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).2008;556–567.

13. Wang Z, et al. An in-situ temperature-sensing interface based on a SAR ADC in 45nm LP digital CMOS for thefrequency-temperature compensation of crystal oscillators. In IEEE International Solid-State Circuits Conference(ISSCC). 2010; 316–318.

14. Zhu Y, Chan CH, Sin SW, Seng-Pan U, Martins RP, Maloberti F. A 35 fJ 10b 160 MS/s pipelined-SAR ADC withdecoupled flip-around MDAC and self-embedded offset cancellation. In IEEE Asian Solid-State Circuits ConferenceDigest of Technical Papers (ASSCC). 2011; 61–64.

15. Kuramochi Y, et al. A 0.027-mm2 self-calibrating successive approximation ADC core in 0.18-mm CMOS. IEICETRANS. Fundamentals 2009; E92-A(2):360–366.

16. Chen Y, et al. A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS. IEEE Asian Solid-State Circuits Conference(ASSCC). 2009; 145–148.

17. Agnes A, et al. A 9.4-ENOB 1V 3.8 mW 100kS/s SAR ADC with time-domain comparator. In IEEE InternationalSolid-State Circuits Conference (ISSCC). 2008; 51:246–247.

18. Kobenge SB, Yang H. A novel low power time-mode comparator for successive approximation register ADC. IEICEElectronics Express 2009; 6(16):1155–1160.

19. Pang WY, Wang CS, Chang YK, Chou NK, Wang CK. A 10-bit 500-KS/s low power SAR ADC with splittingcomparator for bio-medical applications. In IEEE Asian Solid-State Circuits Conference Digest of TechnicalPapers (ASSCC). 2009; 149–152.

20. G Promitzer. 12-bit low power fully differential switched capacitor non-calibrating successive approximation ADCwith 1MS/s. IEEE Journal of Solid-State Circuits 2001; 36(7):1138–1143.

21. Liu C-C, et al. A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18mm CMOS. In 2010Symposium on VLSI Circuits Digest of Technical Papers. 2010; 241–242.

22. Zhu Y, et al. Parasitics nonlinearity cancellation technique for split DAC architecture by using capacitive charge-pump.In IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). 2010; 889–892.

23. Maloberti F, et al. Design considerations on low-voltage low-power data converters. IEEE Transactions on Circuitand Systems-I:Fundamental Theory and Applications 1995; 42(11):853–863.

24. Kobenge SB. Circuit techniques for low-voltage low-power successive approximation register analog-to-digitalconverter. PHD Thesis of Tsinghua University 2010.

25. Masaki S, Yamamoto A, Seki F, Asami F, Ohno K, Imai M, Udo S, et al. Level converter for CMOS 3V to from 5V.US Patent: 5,680,064; Date: 1996.05.28


730 F. HUA ET AL.

26. Nikoozadeh A, Murmann B. An analysis of latch comparator offset due to load capacitor mismatch. IEEE Transactionson Circuit and Systems-II: Express Briefs 2006; 53(12):1398–1402.

27. Behzad R. Design of analog CMOS integrated circuits. International Edition 2001.28. Weigandt TC, et al. Analysis of timing jitter in CMOS ring oscillators. In International Symposium on Circuits and

Systems (ISCAS). 1994; 27–30.29. Liu C-C, Chang S-J, Huang G-Y, Lin Y-Z. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching

procedure. IEEE Journal of Solid-State Circuits 2010; 45(4):731–740.30. Liu W, Huang P, Chiu Y. A 12-bit, 45-MS/s, 3-mW redundant successive approximation register analog-to-digital

converter with digital calibration. IEEE Journal of Solid-State Circuits 2011; 46(11):2661–2672.31. Lee C-C, Flynn MP. A SAR-assisted two-stage pipeline ADC. IEEE Journal of Solid-State Circuits 2011;

46(4):859–869.32. Chiang CT, Chang WH. A 12-bit multi-channel dual-mode successive approximation ADC for power management bus

(Pmbus) devices. International Journal of Circuit Theory and Applications. Published online in Wiley Interscience(www.Interscience.wiley.com). DoI:10.1002/cta.811 2011

33. Verma N, Chandrakasan AP. An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensornodes. IEEE Journal of Solid-State Circuits 2007; 42(6):1196–1205.

34. ZMDI. 12-Bit, 200ksps, 8-channel, serial output ADC datasheet. ZADCS146. 201035. Kobenge SB, Qiao F, Yang H. Ultra-low-power time domain comparator. China Patent: ZL 200910081201.8;

Date:2011.11.09


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design considerations for low power time-mode sar adc

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