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IJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 01, 2015 | ISSN (online): 2321-0613

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Design and Analysis of Different Type Single Bit Adder for ALU

Application Jaswant Singh

1 Gaurav Sharma

2

1Research Scholar M.Tech (VLSI)

2Assistant Professor

1,2Department of Electronics & Communication Engineering

1,2Mewar University, Chittoragarh

Abstract— In these dissertation four types of 1-bit adder has

been designed and simulated using 180nm CMOS

technology in tanner tool at a various supply voltage

from1.0V to 1.8 V & compare their results with respect to

various parameters like delay, area & power consumption.

The adder is the most commonly used arithmetic block of

the Central Processing Unit (CPU) and Digital Signal

Processing (DSP), therefore its performance and power

optimization is of utmost importance. With the technology

scaling to deep sub-micron, the speed of the circuit increases

rapidly. Due to continuous scaling of the transistor size and

reduction of the operating voltage has led to a significant

performance improvement of integrated circuits. Low power

consumption and smaller area are some of the most

important criteria for the fabrication of DSP systems and

high performance systems. At the same time, the power

consumption per chip also increases significantly due to the

increasing density of the chip. Therefore comparison has

been carried out by assuming the circuits with minimum size

transistors, to minimize the power consumption. Power

consumption is a function of load capacitance, frequency of

operation, and supply voltage. A reduction of any one of

these parameter is beneficial. A reduction in power

consumption provides several benefits. Less heat is

generated, which reduces problems associated with high

temperature, such as the need for heat sinks. This provides

the consumer with a product that costs less.

Key words: Central Processing Unit (CPU), Digital Signal

Processing (DSP), CMOS technology

I. INTRODUCTION

Rapid growth in semiconductor technology has led to

shrinking of feature sizes of transistors using deep

submicron (DSM) process. Modern portable battery

operated devices such as cell phones, laptops; PDAs are

particularly affected by this as high power dissipation

reduces battery service life. The adder is the most

commonly used arithmetic block of the Central Processing

Unit (CPU) and Digital Signal Processing (DSP), therefore

its performance and power optimization is of utmost

importance. With the technology scaling to deep sub-

micron, the speed of the circuit increases rapidly. At the

same time, the power consumption per chip also increases

significantly due to the increasing density of the chip.

Therefore, in realizing modern Very Large Scale Integration

(VLSI) circuits, low-power and high-speed are the two

predominant factors which need to be considered. Like any

other circuits' design, the design of high-performance and

low-power adders can be addressed at different levels, such

as architecture, logic style, layout, and the process

technology. As the result, there always exists a trade-off

between the design parameters such as speed, power

consumption, and area. Recently, the requirement of

probability and the moderate improvement in battery

performance indicate power dissipation is one of the most

critical design parameters day by day the demand of

probability and mobility is increasing.

Also the area of chip design is taken into

consideration while talking about probability. Hence three

most widely accepted parameters to measure the quality of a

circuit or to compare various circuit styles are area, delay

and power dissipation. There are three major sources of

power consumption in digital CMOS circuits, which are

summarized in the following equation

LeakageCircuitShortSwitchingTotal PPPP

The first term represents the switching component

of power. The short circuit power dissipation is due to the

direct path from short circuit currents Isc, which arises when

both the NMOS and PMOS transistors are active,

conducting current directly from power supply to ground.

Finally, leakage current power dissipation arises from

substrate injection and sub threshold effects, which is

primarily determined by fabrication technology

considerations. The objective of our dissertation is to design

a low-power and smaller area adder and also compare its

performance parameter with different types of adder

architecture

II. BASIC THEORY AND TYPES OF ADDER

Adders are commonly used in the critical path of many

building blocks of microprocessors and digital signal

processing chips. Adders are critical component not only for

addition, but also for subtraction, multiplication, and

division. Addition is one of the fundamental arithmetic

operations. A fast and accurate operation of a digital system

is greatly influenced by the performance of the resident

adders. The most important parameter for measuring the

quality of adder designs is propagation delay, and area.

Adder or summer is a digital circuit that performs

addition of numbers. In modern computers adders reside in

the arithmetic logic unit (ALU) where other operations are

performed. Although adders can be constructed for many

numerical representations, such as Binary-coded decimal or

excess-3, the most common adders operate on binary

numbers.

A. Application of Adders:

Used in CPU side

Used in networking side

Used in DSP oriented system

In application-specific processors

In biomedical applications

In image processing and video processing.

Design and Analysis of Different Type Single Bit Adder for ALU Application

(IJSRD/Vol. 3/Issue 01/2015/132)


B. DGTAL Adder:

20 transistor full adder based on transmission gate produces

buffered outputs of proper polarity for both sum and carry.

In this circuit 2 inverters are followed by two transmission

gates which act as 8-T XOR. Subsequently 8-T XNOR

module follows. To has 4 transistors XOR which in the next

stage is inverted to produce XNOR. These XOR and XNOR

are used generate sum; Cin and inC are multiplexed which

can simultaneously to generate sum. The signals cin is

controlled either by (a. b) or (a ⊗ b). Similarly the cout can

be calculated by multiplexing a and cin controlled by (a b).

The power dissipation in this circuit is more than the 28

transistor. Schematic diagram of DGTAL based adder is

shown in fig 1

Fig. 1: Schematic Diagram of DGTAL Adder

Fig. 2: Layout Diagram of DGTAL Adder

C. CMOS Adder:

The conventional CMOS adder cell using 28 transistors is

based on standard CMOS topology which is shown below in

fig 3. Due to large number of transistors, its power

consumption is high. Large PMOS transistor in pull up

network result in high input capacitances, which cause high

delay and dynamic power consumption. One of the most

significant advantages of this full adder was its high noise

margins and thus reliable operation at low voltages.




Fig. 3: Schematic Diagram of conventional CMOS Adder

Layout diagram of conventional CMOS adder is shown

below in fig 4, which consume 728µm2 area.

Fig. 4: Layout Diagram of conventional CMOS Adder

D. GDI Adder:

A new low power design technique that solves most of the

problems is known as Gate-Diffusion-Input (GDI) method.

This technique reduces power consumption, propagation

delay, and area of digital circuits. GDI method is based on

the use of a simple cell as shown in below figure. At the first

look the design seems to be like an inverter, but the main

differences are

GDI consist of three inputs- G (gate input to

NMOS/PMOS), P (input to source of PMOS) and

N (input to source of NMOS).

Bulks of both NMOS and PMOS are connected to

N or P (respectively), so it can be arbitrarily biased

at contrast with CMOS inverter.

By using this method a wide variety of logic functions can

be implemented using only two transistors. Schematic

diagram of GDI based adder is shown in fig 5.




Fig. 5: Schematic Diagram of GDI Adder

This method is also suitable for designing fast, low-

power circuits, using a less number of transistors, while

improving logic level swing and static power characteristics

and allowing simple top down design by using small cell

library. Schematic and layout diagram of GDI adder is

shown in fig and fig respectively. GDI adder consumes total

360 µm2 area.

Fig. 6: Layout Diagram of GDI Adder

E. RBSD Adder:

RBSD numbers can be represented using the digit set (

1,0,1 ) unlike binary number system, which is represented

using binary digit set (0, 1). The decimal value of RBSD

number can be calculated by following relation

1

0

2n

i

i

ixD

Let the number (4)10 can be represented in binary

as 0100.The same number in RBSD may be represented by

more than one representation i.e. 0011 or 00111 . Hence

in this number system, a number can be represented by more

than one way, so called redundant system. Three steps are

used in RBSD system in which first and second step

generates intermediate data (carry and sum) and third step

gives the final result. Therefore the input numbers can be

added simultaneously in parallel, as there is no rippling of

carry from LSB to MSB. So its speed is fast as compared to

other adders. Schematic diagram & layout diagram of RBSD

adder is shown below in fig 7 & fig 8 respectively. Total

area required for 1-bit RBSD adder is 450 µm2.




Fig. 7: Schematic Diagram of RBSD Adder

Fig. 8: Layout Diagram of RBSD Adder

III. SIMULATION RESULT AND ANALYSIS

A. DGTAL Adder:

1) Working Principle:

In the circuit we have 2 inverters followed by two

transmission gates which act as 8-T XOR. Subsequently 8-T

XNOR module follows. To generate sum, cin and cinb are

multiplexed which can controlled either by (a b) or (a

⊗b).Similarly the cout can be calculated by multiplexing a

and cin which is controlled by (a b). Simulated waveform of

DGTAL full adder is shown in fig 9.

Fig. 9: Simulated waveform of DGTAL Adder




2) Advantage:

It is the fastest adder. The circuit is simpler than the

conventional adder.

3) Disadvantage:

The power dissipation in this circuit is more than the 28T

adder.

Parameters like delay and power dissipation is

calculated at different VDD and at different VTH, which is

shown in table 1 and 2 respectively.

VDD(V) Power Dissipation (µW) Delay(nS)

Sum Cout

1.8 129.585 4.040 5.211

1.6 109.165 4.948 6.068

1.4 87.255 5.383 6.316

1.2 69.955 6.138 6.968

1.0 40.635 6.954 7.367

Table 1: Parameters of DGTAL adder at different VDD

VTH(V) Power Dissipation (µW) Delay(nS)

Sum Cout

0.17 66.08 1.8710 5.0996

0.27 95.06 2.1715 5.7000

0.37 129.58 3.5799 6.2117

0.47 147.52 3.9199 6.8693

0.57 179.90 5.6646 7.0703

Table 2: Parameters of DGTAL adder at different VTH

B. CMOS Adder:

1) Advantages:

One of the most significant advantages of this full adder is

its high noise margins and thus reliable operation at low

voltages. The layout of CMOS gates was also simplified due

to the complementary transistor pairs.

2) Disadvantages:

Due to large number of transistors, dissipate more power

and require large silicon area.

Fig. 10: Simulated waveform of CMOS Adder



shown in table 3 and 4 respectively.

VDD(V) Power Dissipation(µW) Delay(nS)

Sum Cout

1.8 117.485 0.304 2.843

1.6 101.76 0.378 2.879

1.4 88.13 0.502 3.118

1.2 63.75 0.674 3.341

1.0 38.46 1.101 4.233

Table 3: Parameters of CMOS adder at different VDD

VTH(V)

Power Dissipation(µW)

Delay(nS)

Sum Cout

0.17 57.915 0.242 2.785

0.27 89.672 0.265 2.806

0.37 117.485 0.341 2.943

0.47 139.195 0.387 3.073

0.57 173.165 0.499 3.922

Table 4: Parameters of CMOS adder at different VTH

C. GDI Adder:

Simulated waveform of GDI based full adder is shown in fig

10. Sum bit is obtained from




Fig 10: Simulated waveform of GDI based Adder

The output of the second stage of XOR circuit

while Carry bit (Cout) is calculated by multiplexing B and

Cin controlled by (A XNOR B). When both inputs (va and

vb) and carry in (vc) is logic „1‟ then both outputs sum and

carry out (Cout). When even number of inputs to the adder

are logic „1‟, then sum is „0‟ and Cout is logic „1‟ & for odd

numbers of input sum output is logic „1‟ and Cout is „0‟as

shown in fig 10.

1) Advantage:

These features give the GDI cell two extra input pins to use

which makes it flexible than usual CMOS design. It is also a

genius design which is very power efficient without using

large amount of transistor count.

2) Disadvantage:

Major problem of GDI method is that twin-tub CMOS or

silicon on insulator (SOI) process is used to fabricate. Thus,

it will be more expensive to realize a GDI chip. Moreover if

only standard p-well CMOS process is used, the GDI

scheme will face the problem of lacking driving capability

which makes it more expensive and difficult to realize as a

feasible chip.



shown in table 5 and table 6 respectively.

VDD(V)

Power

Dissipation(µW)

Delay(nS)

Sum Cout

1.8 38.870 1.917 1.930

1.6 31.165 1.958 1.981

1.4 26.841 1.997 2.231

1.2 21.820 2.092 2.932

1.0 18.525 2.324 3.193

Table 5: Parameters of GDI adder at different VDD

VTH (V) Power Dissipation(mW)

Delay(nS)

Sum Cout

0.17 21.44 1.922 1.933

0.27 36.615 1.919 1.932

0.37 58.165 1.917 1.930

0.47 89.925 1.898 1.924

0.57 101.245 1.859 9.142

Table 6: Parameters of GDI adder at different VTH

D. RBSD Adder:

Simulated waveform of RBSD adder is shown below in fig

11.

Fig. 11: Simulated waveform of RBSD Adder






shown in table 7 and table 8 respectively.

VDD(V) Power

Dissipation(mW)

Delay(nS)

Sum Cout

1.8 0.989 0.221 0.990

1.6 0.721 0.328 1.303

1.4 0.494 0.350 1.510

1.2 0.288 0.393 1.995

1.0 0.130 0.734 2.621

Table 7: Parameters of RBSD adder at different VDD

VTH(V) Power

Dissipation(mW)

Delay(nS)

Sum Cout

0.17 0.165 0.218 0.939

0.27 0.240 0.246 0.950

0.37 0.389 0.321 0.998

0.47 0.485 0.374 1.247

0.57 0.789 0.420 1.467

Table 8: Parameters of RBSD adder at different VTH

Simulated waveform of RBSD adder which is used

for calculation of average power dissipation is shown in fig

5.11. Formula that is used for average power dissipation is

given below

Average Power Dissipation =2

minmax PP

Fig. 12: Simulated power waveform of RBSD Adder

IV. CONCLUSION AND FUTURE SCOPE

This chapter summarize the conclusion for the proposed

design and also explained about future scope.

A. Conclusion:

In this dissertation adder has been designed and simulated

using 180nm CMOS technology of tanner tool at a various

supply voltage from1.0V to 1.8 V & compare their results

with respect to various parameter. The comparison has been

carried out both assuming circuits with minimum transistors

size, to minimize the power consumption. Power

consumption is a function of load capacitance, frequency of

operation, and supply voltage. A reduction of any one of

these is beneficial. A reduction in power consumption

provides several benefits. Less heat is generated, which

reduces problems associated with high temperature, such as

the need for heat sinks. This provides the consumer with a

product that costs less. In this paper we conclude that

The power consumption of GDI based adder is

50% less from RBSD adder but 26% less speed as

compared to conventional RBSD adder.

Speed & power dissipation of CMOS adder is 10%

& 39% less as compared to RBSD.

Also CMOS adder has high noise margin as

compared to other types of adders.

Layouts of these adders are also designed using

Micro wind. From area comparison we see that

area of GDI based adder is 11% less than RBSD

adder.

B. Future Scope:

However some aspects of the goal have been achieved using

this design, but still a better adder can be made by some

improvement in the circuit design. The adder circuit can be

further extended and modified by the following points.

Delay & power dissipation of RBSD adder can be

further reduced by improving circuit design.

Delay of GDI based adder can be also reduced by

improving circuit design.

More adder circuit can be used for comparison.

In this design we use 180 nm technologies but

latest technology 28nm and more can be used for

batter design and analysis.

The delay and power dissipation can also reduce by

using low power and high speed techniques like VTCMOS,

DTCMOS, and Adaptive CMOS and Adiabatic logic

technology.

REFERENCES

[1] N. Firake and S. Akashe, “Power-Delay Product

Minimization of Mixed Full Adder Topologies for

High-Performance”, African Journal of Computing

& ICT, Vol 7. No. 2, pp: 93-98, ISSN 2006-1781,

June, 2014.

[2] Ruchika Sharma and Rajesh Mehra, “Design of

Error-Tolerant CMOS Adder Using optimized

Transistor Count”, International Journal of

Advanced Research in Computer and

Communication Engineering,Vol. 3, Issue 7, ISSN

(Print) : 2319-5940, July 2014.

[3] Bamin Gambo, Lod Tapin and Sarat Chandra

Hanjabam, “ Low Power and High Performance

Full Adder in Deep Submicron Technology”,

Journal of Electronics and Communication

Engineering Research Volume 2, Issue 3 pp: 07-16

ISSN : 2321-594, 2014

[4] Namarta and Mr. Sukhjit Singh, “ Comparative

Analysis Different Adder Topologies using 180nm

Technology”, International Journal for Science and

Emerging Technologies with Latest Trends,

Volume 14, Issue 1 pp: 07-11,ISSN No. : 2277-

8136, 2014.

[5] S. Arif Basha & C.V. Subhaskara Reddy, “Low

Power Highly Optimized Full Adder By Using

Different Techniques With10 Transistors”,

International Journal of Engineering Research,




Volume No.3 Issue No: Special 2, pp: 95-96,

ISSN:2319-6890, 22 March 2014.

[6] K Srinivas Raju and Dr. B.R. Vikram, “Competent

Fetch Select Adder using 0.12μm Expertise for

Low Power Applications”, International Journal of

Research in Modern Engineering and Emerging

Technology, Vol. 2, Issue: 2, pp: 16-22,ISSN:

2320-6586, June-July 2014.

[7] Kandimalla Brahmani and Danda Aneesha,

“Analysis of Full Adder Design using Various

CMOS Design”, International Journal of

Engineering & Science Research, Vol-4, Issue-7,

pp: 409-414, ISSN 2277-2685, July 2014.

[8] T.S.Ananth, A.Vijay and Dr. G. K. D. Prasanna

Venkatesan, “Low-Power 1-Bit Full-Adder Cell

using Enhanced Pass Transistor Logic and Power

Gating”, International Journal of Advanced

Technology in Engineering and Volume No.02,

Issue No. 06,pp:1-8 ISSN: 2348 – 7550 ,June

2014.

[9] Narayana Reddy and G. Sai Sindhu, “Design of

Low Power 4 bit Ripple Carry Adder using DPTA

synchronous Adiabatic Logic”, International

Journal of Computational Science, Mathematics

and Engineering, Volume 1, Issue 5, pp: 50-59,

ISSN: 2349-8439, November 2014.

[10] Tran Bich Thuan Pham, Yi Wang and Renfa Li,

“Designing one-bit Full-Adder/Subtractor based on

Multiplexer and LUT‟s architecture on FPGA”,

International Journal of Digital Content

Technology and its Applications,

Volume7,Number8,issue8, pp: 454-464, April

2013.

[11] Channe Gowda and Dr. A. R. Aswatha, “Low-

Power 1-Bit Full-Adder Cell Using Modified Pass

Transistor Logic”, International Journal of

Computer Science and Information Technologies,

Vol. 4 (3), pp: 489-491, ISSN: 0975-9646, 2013.

[12] Erya Deng, Yue Zhang, Jacques-Olivier Klein,

Dafine Ravelsona, Claude Chappert and Weisheng

Zhao, “Low Power Magnetic Full-Adder based on

Spin Transfer Torque MRAM”, IEEE 2013.

[13] M. C. Parameshwara, K. S. Shashidhara and H. C.

Srinivasaiah, “A Novel Low Power 1-bit Full

Adder with CMOS Transmission-gate Architecture

for Portable Applications”, ERCICA, pp: 384-388

ISBN: 9789351071020, 2013.

[14] Shalloo Yadav and Kavita Chauhan, “Study and

Analysis of Various Types of Full Adder's Scheme

for 250nmCMOS Technology”, International

Journal of Electrical, Electronic sand Computer

Engineering volume 2, No.2, pp: 61-65, ISSN N.:

2277-2626, 2013.

[15] Dr. R. Ramana Reddy, M. Krishna Murthy and P.

Divakara Varma, “ Design of 1-bit Full Adder/

Subtractor Circuit using a new 5x5 Fault Tolerant

Reversible Gate for Multiple Faults Detection and

Correction”, International Journal of Engineering

Science & Advanced Technology, Volume-3,

Issue-3, pp:79-84, ISSN: 2250-3676, Jun-Jul 2013.

[16] P. Divakara Varmaand R. Ramana Reddy, “A

Novel 1-Bit Full Adder Design Using DCVSL

XOR/XNOR Gate and Pass Transistor

Multiplexers”, International Journal of Innovative

Technology and Exploring Engineering, Volume-2,

Issue-4, pp: 142- 146,ISSN: 2278-3075,March

2013.

[17] Namarta Gupta, “Designing of Full Adder Circuits

for Low Power”, IJSRET, Volume 2 Issue 4, pp:

215-219 , ISSN 2278 – 0882, July 2013.

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