Decoders and Multiplexers

Prof. Sin-Min Lee

Department of Computer Science

San Jose State University

Decoders

• A combinational circuit that converts binary info from n inputs into a max. of 2n unique objects.

• N - to - m decoders: given n inputs, it outputs m <= 2n minterms.

• Note the ``3'' with a slash, which signifies a three bit input. This notation represents three (1-bit) wires.

• A decoder with n input bits, produces 2^n output bits.

Combinational circuit implementation using Decoders

• We can use decoders to express Boolean functions.

• Any Boolean function can be expressed as a sum of products(minterms).

• So, we can use decoders to produce the minterms and OR gates to produce their logical sum.

Design a digital circuit which compares the magnitude of two 2-bit numbers               and             . It has one output f1 such that

f1=1 if and only if X>Y.

Step 1: Derive the truth table that describes the relation between f1

and the inputs x1,x2,y1, and y2, where x1 and y1 each denotes the

most significant bit of X and Y respectively.

Comparator

Example: expressing full adder with decoder

• We have 3 inputs. So, we use the 3-to-8 decoder to generate the minterms.

• Then we OR 1, 2, 4, 7 and 3,5,6,7 according to the Boolean equations:– S(X,Y,Z) = Sm(1,2,4,7)

– C(X,Y,Z) = Sm(3,5,6,7)

Step 2: Now use the 4-variable K-map to derive the minimal sum of product (SOP) expression for f1.

Implementation using MUXs: Now we implement the output f1

using an 8x1MUX. Selection inputs to the MUX are x2 y1 y2

(that is, if x2y1y2=001, input I1 of the MUX is selected).

The implementation table is tabulated as

Implementation using decoders: Now we implement the output f1

using an          decoder and 3-input OR gates.

Decoders

A B C O7 O6 O5 O4 O3 O2 O1 O00 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0

ABC

O0O1O2O3O4O5O6O7

Inputs Outputs

Multiplexers• 2**n data inputs,

n control input, one data output

• Data inputs selected by control are gated are gated to output

• Each AND gate gets 3 control and one data input, selects input based on control

• OR gate adds all selected inputs

Majority Function using a Multiplxer

• Each input wired to 1 or 0• If 0 in table ground Else connect to Vcc. Check if it works!

Other Users of Multiplexers

• Parallel to Serial Conversion• Put 8 bit data in input lines• Step through 000 to 111 in control lines to select

inputs serially• Used in serializing device inputs such as key

board inputs over telephone lines• Inverse operation: Demultiplexing routes single

serial input into multiple outputs depending on value of control lines

Decoders

• Selects one of 2**n inputs

• Each AND gate implements one Boolean expression ABC etc.

Comparators• 4 address

words, A, B compared.

• Output (A =B)

• Users XOR gates: 1 iff both inputs are same

Programmable Logic Arrays (PLA)

• Used to form Sums of products

• Select inputs by burning out fuses

• Example has 12 inputs, 6 outputs, PWR and GND

PGA Computing Majority function

• Can burn appropriate fuses to fabricate Majority function from a PGA. Choose– 3 inputs, 4 AND gates and

1 OR gate– Burn appropriate fuses

• Which one is best for Majority: – SSI with 4 gates– 1 MSI multiplexer– PLA: more efficient