ddr bus simulator - keysight.com · •measure setup and hold times and a ... •indicates a design...

DDR Bus Simulator

Fangyi Rao

R&D Engineer

Graham Riley

Applications Engineer

Updated Sept, 2014 New Keysight EEsof EDA Simulation Tools for

Signal Integrity, Power Integrity, and EMI/EMC

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Outline

– Challenges in DDR4 Designs

– DDR Bus Simulator in ADS2014.11

– Demo

Keysight EEsof EDA Simulation

Tools for Signal Integrity, Pow er

Integrity, and EMI/EMC

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Outline



– Demo




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DDR3 Design Methodology Review • Run transient simulation on IBIS or SPICE models of controller and memory. Collect waveform of

a few thousands of bits

• Measure setup and hold times and a few other critical figures from waveforms

• Run full compliance test to verify final design




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Challenges in DDR4 Design

• Higher data rate means reduced UI and smaller margins

• Timing margin is eroded by ISI

• RJ also consumes margin

• Reduced VDDQ

• Harder to achieve design goals




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Impact of ISI




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Border of traces

of 103 bits

Border of traces

of 1016 bits

8ps 5ps

• At 800 Mb/s, timing margin deceases by 1% UI from 103 bits to 1016 bits, i.e. ISI tail < 1%UI

• At 3200 Mb/s, margin deceases by 9% UI from 103 bits to 1016 bits, i.e. ISI tail ~ 9%UI

15ps 13ps

800 Mb/s 3200 Mb/s

5” DQ line

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Design Uncertainty at High Speed • The higher the data rate, the more margin is overestimated using small number of bits

• Simulating waveform of 1016 bits is impractical

• Tail of ISI leads to design uncertainty

• RJ also contributes to uncertainty as it is no longer negligible compared to UI at high

data rate

• Uncertainty grows with data rate

• Traditional design methodology relies on safety margin to guard against design

uncertainties




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Low Speed Timing Specifications




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(RJ is a small enough fraction of UI that it can be ignored)

10-5 BER

10-16 BER

(stable system)

Unstable system

Nearly zero errors

Optimal timing Impact on

binning and

yields is small

10-5 error rate Only a small safety

margin relative to

UI is needed after

testing for 105 bits

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What Breaks at High Speed?




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Reliability margin is no longer “free”

10-5 BER

10-16 BER

(stable system)

Unstable system

Nearly zero errors

Optimal timing

10-5 error rate

Traditional

method requires

excessive margin

Excess margin

not needed in

DDR4 spec.

~ 50 ps

Eye Diagram

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Eliminating Design Uncertainty




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• But how much margin is needed?

• Excessive margin leads to difficulties in meeting design goals

• Inadequate margin puts system reliability at risk

• Alternative approach: compute trace probability distribution and make sure

probability inside a setup-hold mask does not exceed target bit error rate (10-16)

• Rx mask, including deterministic and random jitter and noise, is introduced in

DDR4 for DQ

• Indicates a design methodology shift from setup/hold time centric to BER centric

• Avoid overly conservative design and ensure reliability

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Outline



– Demo




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DDR Bus Simulator in ADS2014.11




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• Rigorous statistical calculations for DQ and DQS eye probabilities at arbitrarily low BER

• Equivalent to running infinite number of bits. Eliminate design uncertainty due to ISI and RJ

• Check eye contours at target BER (10-16) against DDR4 Rx mask

• Account for crosstalk between signal lines

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Built-in DQ and DQS Driver Models




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• Driver de-emphasis models

• Account for asymmetry between rise and fall edges

• Physical jitter model. Transitions in stimulus are shifted by Tx jitter

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Built-in DQ and DQS Receiver Models




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Continuous-time-linear-equalizer

(CTLE) model

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Using Other Device Models




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• Support IBIS, sub-circuit and Verilog-A models for driver and receiver

• Asymmetric rise and fall edges in these models are also captured

• Allow mix-and-match between built-in, IBIS, circuit and Verilog-A models

IBIS driver

Sub-circuit Rx

Built-in driver

IBIS Rx

Simple driver as

pattern generator

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BER Mask Margin Measurements




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• Comprehensive margin measurements versus DDR4 Rx mask

• Timing and voltage margins between mask and contour at target BER are reported for

each mask corner

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Batch Simulation




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• Support sweep on design variables, data files (e.g. Touchstone file) and corners

• Automatic generation of spreadsheet summary for design of experiments

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Outline



– Demo




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Thank you




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ddr bus simulator - keysight.com · •measure setup and hold times and a ... •indicates a design...

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