dc1826a - ltc238918-bit/16-bit, 2.5msps low noise, sar
TRANSCRIPT
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DEMO MANUAL DC1826A
DESCRIPTION
LTC238918-Bit/16-Bit, 2.5Msps Low Noise, SAR ADCs with Pin-Configurable
Analog Input Range
Demonstration circuit 1826A features the LTC®2389 low noise, high speed successive approximation register ADC which operates from a single 5V supply. The following text refers to the LTC2389-18, but also applies to the LTC2389-16, the only difference being the number of bits. The LTC2389-18 supports pin-configurable fully differential (±4.096V), pseudo-differential unipolar (0V to 4.096V), and pseudo-differential bipolar (±2.048V) analog input ranges, allowing it to interface with multiple signal chain formats. The LTC2389-18 achieves ±2.5LSB INL (maximum), with no missing codes at 18 bits.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
BOARD PHOTO
The DC1826A demonstrates the performance of the LTC2389-18 in conjunction with the DC718 QuikEval™ II data collection board.
The demonstration circuit 1826A is intended to demon-strate recommended grounding, component placement and selection, routing and bypassing for this ADC. Several suggested driver circuits for the analog inputs will be presented.
Design files for this circuit board are available at http://www.linear.com/demo
Figure 1. DC1826A Connection Diagram
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DEMO MANUAL DC1826A
DC718 QUICK START PROCEDURE
DC1826A SETUP
Check to ensure that all switches and jumpers are set as shown in the connection diagram of Figure 1. The default connections configure the ADC to use the onboard refer-ence and regulators to generate the required common mode voltages. The analog input is DC-coupled. Connect the DC1826A to a DC718 USB high speed data collection board using connector J4. Then, connect the DC718 to a host PC with a standard USB A/B cable. Apply ±9V to the indicated terminals. Then, apply a low jitter signal source to J2. The default setup uses a single-ended to differential converter so that it is only necessary to apply a single-ended input signal to J2. Connect a low jitter 2.5MHz (100MHz for serial) 3.3VP-P sine wave or square wave to connector J1 for parallel operation. Note that J1 has a 49.9Ω termination resistor to ground.
DC Power
The DC1826A requires ±9VDC and draws 100mA. Most of the supply current is consumed by the CPLD, opamps, regulators and discrete logic on the board. The 9VDC in-put voltage powers the ADC through LT1763 regulators which provide protection against accidental reverse bias. Additional regulators provide power for the CPLD and opamps. See Figure 1 for connection details.
Run the QuikEval II software (PScope.exe version K73 or later) supplied with the DC718 or download it from www.linear.com.
Complete software documentation is available from the help menu. Updates can be downloaded from the tools menu. Check for updates periodically as new features may be added.
The PScope™ software should recognize the DC1826A and configure itself automatically.
Click the collect button (see Figure 7) to begin acquiring data. The collect button then changes to pause, which can be clicked to stop data acquisition.
Clock Source
You must provide a low jitter 3.3VP-P sine or square wave to J1. The clock input is AC-coupled so the DC level of the clock signal is not important. A generator like the HP8644 or the DC1216A-A is recommended. Even a good generator can start to produce noticeable jitter at low frequencies. Therefore, it is recommended for lower clock rates to divide down a higher frequency clock to the desired sample rate. For serial operation, the ratio of clock frequency to conversion rate is 50:1. The maximum serial conversion rate is 2Msps. If the clock input is to be driven with logic, it is recommended that
DC1826A ASSEMBLY OPTIONSASSEMBLY VERSION U1 PART NUMBER MAX CONVERSION RATE NUMBER OF BITS SERIAL MAX CLKIN FREQUENCY
DC1826A-A LTC2389CMS-18 2.5Msps 18 100MHz
DC1826A-E LTC2389CMS-16 2.5Msps 16 100MHz
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DEMO MANUAL DC1826A
the 50Ω terminator (R6) be removed. Slow rising edges may compromise the SNR of the converter in the presence of high amplitude higher frequency input signals.
Data Output
Parallel data output from this board (0V to 3.3V default), if not connected to the DC718, can be acquired by a logic analyzer, and subsequently imported into a spreadsheet, or mathematical package depending on what form of digital signal processing is desired. Alternatively, the data can be fed directly into an application circuit. Use Pin 3 of J4 to latch the data. The data can be latched using either edge of this signal. The data output signal levels at J4 can also be reduced to 0V to 2.5V if the application circuit cannot tolerate the higher voltage. This is accomplished by mov-ing JP4 to the 2.5V position.
Reference
The default reference is the LTC2389-18’s internal 4.096V reference. If an external reference is desired use the on-boardLTC6655-4.096 reference. It is enabled by stuffing 0Ω resistors R7, R9 and R10 and removing 0Ω resistor R8.
Analog Input
The default driver for the analog inputs of the LTC2389-18 on the DC1826A is shown in Figure 2. This circuit converts a single-ended 0V to 4.096V input signal applied at AIN
+ into a differential signal with a swing of ±4.096V between the +IN and –IN inputs of the ADC. In addition, this circuit band limits the input frequencies to approximately 16MHz.
It is also possible to drive the LTC2389-18 pseudo differ-entially both with unipolar and bipolar outputs. The circuit of Figure 3 shows the pseudo-differential unipolar driver. This is connected on the DC1826A by removing R27 and placing 0Ω resistors in the R31 and R42 positions.
Figure 4 shows the pseudo-differential bipolar driver circuit. This is connected on the DC1826A by removing R29, R30, C25 and C26 and placing 0Ω in the R30 position.
Alternatively, if your application circuit produces a differ-ential signal which can drive the ADC, the circuit shown in Figure 5 can be used. This is connected in the DC1826A by removing R29, R30, R37, C23, C25 and C26 and by adding a 0Ω resistor for R30 and R25. At this point it will be necessary to drive both AIN
+ and AIN–.
Figure 2. Default Driver Circuit
Figure 3. Pseudo-Differential Unipolar Driver
Figure 4. Pseudo-Differential Bipolar Driver
Figure 5. Fully Differential Driver
DC1826A SETUP
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DEMO MANUAL DC1826A
AC-Coupling the Inputs
The circuit in Figure 5 can be AC-coupled on the DC1826A by putting JP1 and JP2 in the AC position and adding a 1k resistor at the R11 and R40 locations. Using just JP1 and adding R11 allows a single-ended input signal to be AC-coupled. AC-coupling the inputs may degrade the distortion performance of the ADC due to nonlinearity of the coupling capacitors (C12 and C31).
Data Collection
For SINAD, THD or SNR testing, a low noise, low distortion generator such as the B&K Type 1051 or Stanford Research DS360 should be used. A low jitter RF oscillator such as the HP8644 or DC1216A-A is used as the clock source.
This demo board is tested in-house by attempting to du-plicate the FFT plot shown in Figure 7a of the LTC2389-18 data sheet. This involves using a 2.5MHz clock source, along with a sinusoidal generator at a frequency of 2kHz. The input signal level is approximately –1dBfs. The input is level shifted and filtered with the circuit shown in Fig-ure 6. A typical FFT obtained with DC1826A is shown in Figure 7. Note that to calculate the real SNR, the signal level (F1 amplitude = –0.998dB) has to be added back to the SNR that PScope displays. With the example shown in Figure 7 this means that the actual SNR would be 98.50dB instead of the 97.52dB that PScope displays. Taking the RMS sum of the recalculated SNR and the THD yields a SINAD of 98dB which is fairly close to the typical number for this ADC.
There are a number of scenarios that can produce mis-leading results when evaluating an ADC. One that is common is feeding the converter with a frequency that is a submultiple of the sample rate, and which will only exercise a small subset of the possible output codes. The proper method is to pick an M/N frequency for the input sine wave frequency. N is the number of samples in the FFT. M is a prime number between one and N/2. Multiply M/N by the sample rate to obtain the input sine wave frequency. Another scenario that can yield poor results is if you do not have a signal generator capable of ppm frequency accuracy or if it cannot be locked to the clock frequency. You can use an FFT with windowing to reduce the “leakage” or spreading of the fundamental, to get a close approximation of the ADC performance. If an amplifier or clock source with poor phase noise is used, the windowing will not improve the SNR.
Layout
As with any high performance ADC, this part is sensitive to layout. The area immediately surrounding the ADC on the DC1826A should be used as a guideline for placement, and routing of the various components associated with the ADC. Here are some things to remember when laying out a board for the LTC2389-18. A ground plane is necessary to obtain maximum performance.
Keep bypass capacitors as close to supply pins as pos-sible. Use individual low impedance returns for all bypass capacitors. Use of a symmetrical layout around the analog inputs will minimize the effects of parasitic elements. Shield analog input traces with ground to minimize coupling from other traces. Keep traces as short as possible.
Component Selection
When driving a low noise, low distortion ADC such as the LTC2389-18, component selection is important so as to not degrade performance. Resistors should have low values to minimize noise and distortion. Metal film resistors are recommended to reduce distortion caused by self heating. Because of their low voltage coefficients, to further reduce distortion NPO or silver mica capacitors should be used. Any buffer used to drive the LTC2389-18 should have low distortion, low noise and a fast settling time such as the LT6350.
DC1826A SETUP
Figure 6. Level-Shift Circuit
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DEMO MANUAL DC1826A
Jumper and Switch Functions
JP1: Selects AC- or DC-coupling of AIN+. The default setting
is DC.
JP2: Selects AC- or DC-coupling of AIN–. The default setting
is DC.
JP3: VCM sets the DC bias for AIN+ and AIN
– when the inputs are AC-coupled. VREF /2 is the default setting.
JP4: VCCIO sets the output levels at J2 to either 3.3V or 2.5V. Use 3.3V to interface to the DC718 which is the default setting.
JP5: EEPROM default position is WP. The position of this jumper should not be changed.
SW1
SER_PARL: Off enables serial operation. Sample rate is the CLKIN frequency divided by 50. On enables parallel operation. Sample rate is equal to the CLKIN frequency.
OB/2CL: Off enables offset binary output code in fully-differential mode and unipolar range with straight binarycode in pseudo-differential mode. On enables 2’s comple-ment output code in fully-differential mode and bipolar range with 2’s complement output code in pseudo-dif-ferential mode.
CSL: Off disables SDO and gates SCK off. On enables SDO and gates SCK on.
PD/FDL: Off enables pseudo-differential mode. On enables fully-differential mode.
The default position for all switches is on.
DC1826A SETUP
Figure 7. PScope Screenshot
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DEMO MANUAL DC1826A
PARTS LISTITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
DC1826A Required Circuit Components
1 7 C1, C2, C3, C4, C5, C6, C51 Cap., X7R, 0.1μF, 25V, 10%, 0603 AVX 06033C104KAT2A
2 5 C7, C21, C27, C29, C34 Cap., X5R, 1μF, 25V, 20%, 0603 AVX 06033D105MAT2A
3 0 C8, C14 (OPT) Cap., 0805
4 1 C9 Cap., X5R, 1μF, 25V, 10%, 0805 AVX 08053D105KAT2A
5 11 C10, C12, C22, C23, C30, C31, C36, C41, C47, C52, C57
Cap., X5R, 10μF, 6.3V, 20%, 0603 Taiyo Yuden JMK107BJ106MA-T
6 2 C11, C19 Cap., X7R, 1000pF, 50V, 10%, 0805 AVX 08055C102KAT1A
7 0 C13, C15, C16, C17, C18, C24, C32, C33 (OPT) Cap., 0603
8 17 C20, C28, C35, C37, C38, C39, C40, C42, C43, C60, C61, C62, C63, C64, C65, C66, C67
Cap., X5R, 0.1μF, 10V, 10%, 0402 AVX 0402ZD104KAT2A
9 2 C25, C26 Cap., NPO, 330pF, 25V, 5%, 0603 AVX 06033A331JAT1A
10 1 C44 Cap., X5R, 47μF, 16V, 20%, 1210 Taiyo Yuden EMK325BJ476MM
11 5 C45, C48, C53, C55, C58 Cap., X7R, 1μF, 16V, 20%, 0603 AVX 06033C105MAT2A
12 4 C46, C50, C54, C56 Cap., X7R, 0.01μF, 100V, 10%, 0603 AVX 06031C103KAT2A
13 2 C49, C59 Cap., X5R, 10μF, 10V, 20%, 0805 Taiyo Yuden LMK212BJ106MG
14 7 E1, E2, E4, E5, E7, E8, E10 Turret, Testpoint Mill Max 2308-2-00-80-00-00-07-0
15 3 E3, E6, E9 Turret, Testpoint Mill Max 2501-2-00-80-00-00-07-0
16 5 JP1, JP2, JP3, JP4, JP5 Headers, 3 Pins, 100mil Ctrs. Samtec TSW-103-07-L-S
17 1 JP6 Headers, Dbl. Row, 2 x 5, 100mil Ctrs. Samtec TSW-105-07-L-D
18 3 J1, J2, J3 BNC Connector Connex 112404
19 1 J4 Box Conn, 0.1 Ctr, 40 Pin Samtec TSW-120-07-L-D
20 4 MH1, MH2, MH3, MH4 Stacking Spacers, Snap-On, 0.25" Tall Keystone 8831
21 2 R1, R3 Res., Chip, 33, 0.06W, 5%, 0603 Vishay CRCW060333R0JNEA
22 3 R2, R4, R58 Res., Chip, 1k, 0.06W, 5%, 0603 Vishay CRCW06031k,00JNEA
23 1 R5 Res., Chip, 33, 0.06W, 5%, 0402 Vishay CRCW040233R0JNED
24 1 R6 Res., Chip, 49.9, 0.25W, 1%, 1206 Vishay CRCW120649R9FKEA
25 0 R7, R9, R10 (OPT) Res., 0402
26 1 R8 Res./Jumper, Chip, 0Ω, 1/16W, 1A, 0402 Vishay CRCW04020000Z0ED
27 0 R11, R12, R13, R18, R19, R22, R23, R25, R31, R40, R42 (OPT)
Res., 0603
28 4 R14, R15, R20, R41 Res./Jumper, Chip, 0Ω, 1/16W, 1A, 0603 Vishay CRCW06030000Z0EA
29 2 R16, R27 Res., Chip, 10, 0.06W, 5%, 0603 Vishay CRCW060310R0JNEA
30 2 R17, R21 Res., Chip, 49.9, 0.06W, 1%, 0402 Vishay CRCW040249R9FKED
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DEMO MANUAL DC1826A
PARTS LISTITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
31 5 R24, R26, R54, R56, R57 Res., Chip, 1k, 0.06W, 5%, 0402 Vishay CRCW04021k,00JNED
32 5 R28, R32, R36, R39, R59 Res., Chip, 10k, 0.06W, 5%, 0402 Vishay CRCW040210k,0JNED
33 2 R29, R30 Res., Chip, 402, 0.06W, 1%, 0402 Vishay CRCW0402402RFKED
34 4 R33, R34, R35, R38 Res., Chip, 300, 0.06W, 5%, 0402 Vishay CRCW0402300RJNED
35 1 R37 Res., Chip, 75, 0.06W, 5%, 0603 Vishay CRCW060375R0JNEA
36 1 R43 Res., Chip, 0Ω, 0.06W, 1A, 0603 Vishay CRCW06030000Z0EA
37 1 R44 Res., Chip, 3.92k, 0.06W, 1%, 0603 Vishay CRCW06033K92FKEA
38 2 R45, R53 Res., Chip, 1.00k, 0.06W, 1%, 0603 Vishay CRCW06031k,00FKEA
39 3 R46, R47, R48 Res., Chip, 4.99k, 0.06W, 1%, 0603 Vishay CRCW06034K99FKEA
40 1 R49 Res., Chip, 1.69k, 0.06W, 1%, 0603 Vishay CRCW06031k,69FKEA
41 1 R50 Res., Chip, 1.54k, 0.06W, 1%, 0603 Vishay CRCW06031k,54FKEA
42 1 R51 Res., Chip, 2.80k, 0.06W, 1%, 0603 Vishay CRCW06032K80FKEA
43 1 R52 Res., Chip, 665, 0.06W, 1%, 0603 Vishay CRCW0603665RFKEA
44 1 R55 Res., Chip, 10k, 0.06W, 5%, 0603 Vishay CRCW060310k,0JNEA
45 0 R60 (**OPT) Res., Chip, 301, 0.06W, 1%, 0402 Vishay CRCW0402301RFKED
46 1 SW1 Switch, Slide, SW-219-4M CTS Electronic Components 219-4MST
47 0 TP1, TP2 (OPT) Testpoint, Test Pad Component Corp. TP-107-02
48 2 U2, U4 I.C., Inverter, SC70-5 Fairchild Semi. NC7SV,U04P5X
49 1 U3 I.C., Inverter, SC70-5 Fairchild Semi. NC7SZ04P5X
50 1 U5 I.C., Precision Buff., Ref., MSOP(08)-MS8 Linear Technology Corp., LTC6655BHMS8-4.096
51 1 U6 I.C., Single D, Flip Flop, US8 ON Semi. NL17SZ74USG PbF
52 1 U7 I.C., Op Amp, SO(08) (Narrow-150mil) Linear Technology Corp., LT6201IS8
53 1 U8 I.C., mPower Regulator, SO(08) (Narrow-150mil)
Linear Technology Corp., LT1763CS8-1.8
54 2 U9, U10 I.C., mPower Regulator, SO(08) (Narrow-150mil)
Linear Technology Corp., LT1763CS8
55 1 U11 I.C., mPower Regulator, SO(08) (Narrow-150mil)
Linear Technology Corp., LT1763CS8-5
56 1 U12 I.C., Serial EEPROM, TSSOP-8 Microchip, 24LC024-I/ST
57 1 U13 I.C., mPower Regulator, TSOT23-S5 Linear Technology Corp., LT1964ES5-SD
58 1 U14 I.C., Max II Family, EPM240T Altera EPM240GT100C5N
59 5 XJP1, XJP2, XJP3, XJP4, XJP5 Shunt, 0.1" Ctrs. Samtec SNT-100-BK-G
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DEMO MANUAL DC1826A
PARTS LISTITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
DC1826A-A Required Circuit Components
1 1 DC1826A General BOM
2 1 R60 Res., Chip, 301, 0.06W, 1%, 0402 Vishay CRCW0402301RFKED
3 1 U1 IC, LTC2389CLX-18 Linear Technology Corp., LTC2389CLX-18
4 1 Fab, Printed Circuit Board Demo Circuit DC1826A
DC1826A-E Required Circuit Components
1 1 DC1826A General BOM
2 1 U1 IC, LTC2389CLX-16 Linear Technology Corp., LTC2389CLX-16
3 1 Fab, Printed Circuit Board Demo Circuit DC1826A
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DEMO MANUAL DC1826A
SCHEMATIC DIAGRAMS
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41
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C:\P
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JEC
TS
\182
6A\S
CH
\182
6A_0
0_R
EV
4.D
SN
RE
VIS
ION
HIS
TO
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VIS
ION
HIS
TO
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pone
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1234
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hm
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hm
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42
5 3
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hm
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hm
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T)
C32
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T)
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T)
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C21
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300
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R33
300
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T)
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1
3
2
R22
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T)
R22
(OP
T)
C20
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02
C20
0.1u
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02
C17
C17
C33
(OP
T)
C33
(OP
T)
U1A
LTC
238X
CLX
U1A
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238X
CLX
SER_PARL_MODE04
GND_MODE15
OB/2CL6
D0/
A0
7D
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18
D2
9D
310
D4
11D
512
D6
13D
714
D8
15D
916
D10
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DIN
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CLK
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1425
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26D
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US
Y29
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CSL31
RESET32
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42
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R26 1K 04
02
R35
300
0402
R35
300
0402
TP
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VS
TL
TP
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VS
TL
R37
75R37
75
R21
49.9
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R21
49.9
0402
C9
1uF
0805
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R38
300
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R38
300
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R6
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1% 1206
R6
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R20
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hmR
200
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U2
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hm04
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R5 33
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R5 33
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R13
(OP
T)
R13
(OP
T)
C11
1000
pF08
05
C11
1000
pF08
05
C25
330p
F
C25
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F
R42
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T)
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T)
C5
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NL1
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CP
1
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PR7
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CLR6
R39
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FC
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1uF
R17
49.9
0402
R17
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C28
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02
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02
R18
(OP
T)
R18
(OP
T)
R31
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T)
R31
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T)C4
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F
C4
0.1u
F
C10
10uF
C10
10uF
C6
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FC
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1uF
R23
(OP
T)
R23
(OP
T)
C31
10uF
C31
10uF
R3
33R3
33
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(OP
T)
R40
(OP
T)
R12
(OP
T)
R12
(OP
T)
U3
NC
7SZ
04P
5XU
3N
C7S
Z04
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42
5 3 R11
(OP
T)
R11
(OP
T)
C22
10uF
6.3V
C22
10uF
6.3V
R25
(OP
T)
R25
(OP
T)
OU
T+
IN -IN
U7B
OU
T+
IN -IN
U7B
5 67
R36
10K
0402
R36
10K
0402
R16 10R16 10
C30
10uF
C30
10uF
R4
1KR4
1K
C23
10uF
C23
10uF
+IN -IN
OU
T
U7A
+IN -IN
OU
T
U7A
3 21
48
C16
(OP
T)
C16
(OP
T)
J1C
LK10
0MH
z M
AX
3.3V
PP
J1C
LK10
0MH
z M
AX
3.3V
PP
U5
LTC
6655
BH
MS
8-4.
096
U5
LTC
6655
BH
MS
8-4.
096
SH
DN
1
VIN
2
GN
D3
GN
D4
GN
D5
VO
UT
_S6
VO
UT
_F7
GN
D8
R30
402
1%R30
402
1%
C24
(OP
T)
C24
(OP
T)
R29
402
1%R29
402
1%
R14
0 O
hm
R14
0 O
hm
R19
(OP
T)
R19
(OP
T)
JP3
EX
T
INT
CM
JP3
EX
T
INT
CM
1 32
C14
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T)
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C14
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T)
0805
C18
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T)
C18
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T)
R34
300
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R34
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C29
1uF
C29
1uF
C19
1000
pF08
05
C19
1000
pF08
05
C12
10uF
C12
10uF
10dc1826afa
DEMO MANUAL DC1826A
SCHEMATIC DIAGRAMS
Fig
ure
9. D
C18
26A
Low
Noi
se,
Hig
h S
peed
SA
R A
DC
Fam
ily
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
CLK
OU
T
DB
5
DB
6
DB
0
DB
1
DB
2
DB
3
DB
4
DB
7
DB
8
DB
9
DB
10
DB
11
DB
12
DB
13
DB
14
DB
15
DB
16
DB
17
+1.
8V+
9V_I
NV
++
9V_I
N
+3.
3V+
9V_I
N+
5V+
9V_I
N
V-
-9V
_IN
+5V
+3.
3V
SIZE
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TE:
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TO
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3.3V
2.5V
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1 32
C59
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0805
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10uF
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0805
C53
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C53
1uF
16V
C36
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C36
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R48
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C55
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16V
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C49
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0805
R46
4.99
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8V
E4
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8VC
451u
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V
C45
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16V
C48
1uF
16V
C48
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D
E6
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R52
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V-
C51
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F
C51
0.1u
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C43
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MT
EC
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W-1
20-0
7-L-
D
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SA
MT
EC
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W-1
20-0
7-L-
D
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
C57
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6.3V
C57
10uF
6.3V
C40
0.1u
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0.1u
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238X
CLX
U1B
LTC
238X
CLX
GN
D17
GN
D1
GN
D20
GN
D35
GN
D41
GN
D44
VD
D47
VD
D46
VD
D45
VD
D40
VD
D2
VD
D19
VD
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OV
DD
18
GN
D48
C58
1uF
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C58
1uF
16V
C41
10uF
C41
10uF
C39
0.1u
F04
02
C39
0.1u
F04
02
U10
LT17
63C
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U10
LT17
63C
S8
GND7
SH
DN
5
IN8
BY
P4
OU
T1
GND6S
EN
SE
/AD
J2
GND3
C38
0.1u
F04
02
C38
0.1u
F04
02
U12 24
LC02
4-I/S
T
U12 24
LC02
4-I/S
T
A0
1
A1
2
A2
3
VS
S4
VC
C8
WP
7
SC
L6
SD
A5
R51
2.80
K1%R
512.
80K
1%
U11
LT17
63C
S8-
5U
11LT
1763
CS
8-5 GND
7
SH
DN
5
IN8
BY
P4
OU
T1
GND6S
EN
SE
/AD
J2
GND3
E3
+9V
/+10
VIN
E3
+9V
/+10
VIN
C46
0.01
uFC
460.
01uF
C52
10uF
6.3V
C52
10uF
6.3V
R43
0 O
hmR43
0 O
hm
E8
+5V
E8
+5V
C47
10uF
6.3V
C47
10uF
6.3V
U9
LT17
63C
S8
U9
LT17
63C
S8
GND7
SH
DN
5
IN8
BY
P4
OU
T1
GND6S
EN
SE
/AD
J2
GND3
U13
LT19
64E
S5-
SD
U13
LT19
64E
S5-
SD
SH
DN
3IN
2O
UT
5
AD
J4
GN
D1
C37
0.1u
F04
02
C37
0.1u
F04
02
R50
1.54
K1%R
501.
54K
1%
C54
0.01
uFC
540.
01uF
JP5
PR
OG
EE
PR
OM W
P
JP5
PR
OG
EE
PR
OM W
P
1 32
R45
1.00
K1%R
451.
00K
1%
C35
0.1u
F04
02
C35
0.1u
F04
02
E5
V+
E5
V+
R53
1.00
K1%R
531.
00K
1%
U8
LT17
63C
S8-
1.8
U8
LT17
63C
S8-
1.8
GND7
SH
DN
5
IN8
BY
P4
OU
T1
GND6S
EN
SE
/AD
J2
GND3
E7
+3.
3V
E7
+3.
3V
R44
3.92
K1%R
443.
92K
1%
C56
0.01
uFC
560.
01uF
C50
0.01
uFC
500.
01uF
11dc1826afa
DEMO MANUAL DC1826A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SCHEMATIC DIAGRAMS
Fig
ure
10.
DC
1826
A L
ow N
oise
, H
igh
Spe
ed S
AR
AD
C F
amil
y
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DE
V_O
E
DE
V_C
LRN
DB
12D
B13
DB
14D
B15
CLK
OU
T
D13
/SC
LK
CN
VS
T_3
3
MO
DE
1M
OD
E0
DB
16D
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DEMO MANUAL DC1826A
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2012
LT 0412 REV A • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica-tion engineer.
Mailing Address:
Linear Technology
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Copyright © 2004, Linear Technology Corporation