DC Link Voltage Swinging and Load CurrentUnbalance in Fault Tolerant VSI. Overview and

Compensation Strategies.V. Boscaino, A. O. Di Tommaso, F. Genduso and R. Miceli, member IEEEDEIM, Department of Energy Information engineering and Mathematical models,

University of Palermo, 90128 block 9,Palermo, Italy, email: rosario.miceli@unipa.it

Abstract—The topic of this paper is the discussion on theperformance of a three-phase fault tolerant inverter with par-ticular attention to the underrated aspect of current unbalancesoccurring due to the DC link voltage fluctuates after the inverterreconfiguration.

Capacitor voltage unbalance affects not only the averageoutput voltage of the inverter, but also its performance. In fact,the inverter performance depends on the fluctuating DC-linkvoltage components rather than on the average DC-link voltage.

After a brief analysis of the voltage fluctuation phenomenaresulting from fault tolerant configuration and their effect onload current unbalance, the Authors consider different compen-sating preventive or repressive strategies in different applicationscenarios. These strategies can operate both in open and closedloop control. The paper highlights their advantages, drawbacksand analyzes their different behavior.

Index Terms—Power electronics, Power converters, AC motordrives, fault-tolerance, Inverters.

I. INTRODUCTION.

Nowadays, reliability of power electronic converters hasincreased more and more over time. The progress in the fieldof semiconductor devices technology has allowed designersand producers to realize many complex converter convertersstructures with a very small failure rates with respect tothe past. However, although less frequent, a fault event isunavoidable anyway and, sooner or later, such an event willoccurs.

On the other hand, many loads now present a special needfor continue operation; this need is certainly greater than inthe past. Not many years ago, hospitals and and a few more,were considered the only privileged loads, but actually, ina different scenario, following digital public administration,managements of large data centers with many capital sensitiveinformation, proper conduction of business, management of apublic transportation system and so on, clearly require alwayhigher levels of reliability of the electrical power system.

This is even more important by considering that the in-creased level of network interconnections may imply that afailure, apparently limited to a specific area, may have a greatimpact, even at great distances.

In this scenario, fault tolerance of a power a system hasclearly become of paramount importance. Fault tolerance is inbrief the set of those features allowing different apparatuses

to continue their operation with an acceptable level of perfor-mance, even in the presence of one or more faults, wheneverpossible and after a proper reconfiguration.

It is hard to say, in the beginning, what "acceptable level ofperformance" really means because this can only be definedcase by case, following the systems under consideration andtheir particular application.

There are delicate frameworks in which a full stop of thesystem heavily undermines safety (e.g. the case of a submarineapplications) and then clearly, in order to guarantee continuityand safety, the predefined “acceptable performance level” cannot be assumed in too restrictive way.

On the contrary, in an electrical drive whose fundamentalspecification is the accuracy (such as in a fine positioningsystem), the inability to achieve this goal after a fault, mustnecessarily imply a lower level of fault tolerance because pre-cision and fault tolerance are often antithetical specifications.Therefore, it may be preferable that the drive is completelystopped [1].

Although lifetime prediction is very useful in componentsselection stage, this design approach can not prevent fromperformance degradation, damages to the supplied equipmentsor even hazards to human life. In this way, if a fault occursthe system will handle the fault avoiding damages, at worstderating its own performances. Fault detection, handling andpost-fault operation are now mandatory in modern powerstages. Within inverter power stages, internal switch faults areusually classified into open-circuit or short-circuit faults.

This paper considers the problem of fault tolerance in three-phase inverter and discusses what specifically is meant by postfault "appropriate level of performance".

In the past many authors have dealt with the general problemof fault tolerant control of a VSI, focusing the main aspect inthe better way to control the unfaulted power devices. In thispaper, instead, the different aspect of the post fault and recon-figuration unbalance of currents is considered. Sometimes thisproblem has been neglected or wrongly underrated.

The load current unbalance resulting in fault tolerant modeis mainly due to voltage changes on the the DC Link ca-pacitances. The post fault unbalance is indeed caused by thecirculation of the load current on the faulty phase in thecapacitors after reconnecting the faulted phase to the DC Link

split point [1]–[3].

II. PROBLEM STATEMENT.

The faults of a three-phase inverter comes fundamentallyfrom a short circuit, untimely opening, lack of control in powerdevices due to interruption of the drivers signals flow or tomalfunction of the drivers. With this regard it should be threedifferent behaviors can be distinguished after the fault.

1) An open-circuit fault affects only one controllable de-vice: The current flowing across the faulted phase cancirculate only during half wave, closing its patternthrough the freewheeling diode and/or the other deviceof the leg. The fault condition could persist long enough,causing deterioration in performance;

2) An open-circuit fault affects an IGBT and its companionfreewheeling diode: In this case, the current on thefaulted phase vanishes, unless it is conducted by theremaining IGBT. The load current conducted by thehealthy IGBT is highly pulsating.

3) An entire leg of the inverter is disconnected due to thefault: This may happen if the fault occurring to onedevice propagates to the second device of the sameleg. This is the typical case of packaged modules orthat of fast fuses or another protection intervention. Fordamages of an entire leg, the current flowing across thefaulted phase becomes zero.

Splitting open circuit fault occurrence in the three cases isessential for the correct definition of a proper diagnosis indexthat does not lead to false positives enabling a prompt action.Anyway, basically a fault tolerant strategy operation consistsin the following steps:

1) diagnosis of the faulted phase;2) exclusion of the faulted phase;3) reconfiguration using auxiliary devices and restart.

These steps should take place indeed without any one optingfor an inverter shuts down.

In the technical literature, redundant and non-redundanttopologies are distinguished [4]. Redundant topologies arebased on a circuital redundancy of parts of the original circuit.After fault occurrence, the redundant circuitry replaces thefaulted part of the original circuit [5]–[7]. Gate drive signalsof the faulted part are so connected to the redundant sectionneither modifying the modulation strategy nor the invertertopology. Redundant structures do not usually suffer fromperformance decrease at the expenses of increasing costs.As shown in Fig.1, in non-redundant architectures a limitednumber of additional devices is usually required. After faultoccurrence, the architecture is reconfigured by means of addi-tional devices and the switching strategy is properly modifiedto accommodate the post-fault architecture [8]–[11].

Non-redundant topologies may suffer from performancedecrease. In non-redundant topologies, after locating the fault,the corresponding phase-leg is disconnected and circuit recon-figuration will be performed by auxiliary switching devices.Circuit reconfiguration is usually realized by connecting the

Figure 1: Typical non redundant fault-tolerant inverter topol-ogy

faulted phase pole to the midpoint of the inverter DC link bymeans of auxiliary switching devices. Therefore, reconfigura-tion usually causes a voltage unbalance on the DC link thusleading to a capacitor over-rating and increasing distortion.Furthermore, DC Link voltage unbalance also causes theappearance of an inverse current component [3], [12]. Inelectrical drives applications, this inverse component should beavoided because of its additional breaking torque, narrowingthe motor torque range and contributing to the whole systempower derating. A limitation of the DC link unbalance isthen the key to improve system performances in post-faultoperation.

As already shown in the technical literature, in a fault-tolerant inverter the modulation strategy must be changed toavoid an inverse component of the load currents. In particular,the reference voltage must be significantly changed to cancelits inverse component [2].

In case of a fault, voltage references (uref1 and uref2) aretwo sinusoidal signals controlling the healthy legs, whereasthe reference of the faulty leg vanishes. Let’s assume that thecorresponding complex signals are:

Uref1 = Uxej0 Uref2 = Uxe

−jϕ (1)

where Ux is the RMS voltage value and ϕ is the phasedisplacement between the signals.

With this fundamental assumption, the magnitude of thereference voltage inverse component results:

|Uinv(ABC)| =√

2Ux

√1 + cos(ϕ± 2π

3) (2)

in which the sign “+” is for a fault on the external phases Aand C, while the sign “-” is for a fault on the central phaseB. In both cases, for ϕ ± 2π

3 = π i.e. for ϕ = ±π3 (“+” forphase A and C and “-” for phase B) |Uinv| = 0.

Unfortunately (2) has been derived by assuming a constantDC Link Voltage. The DC Link voltage is not effectivelyconsidered constant. As confirmed by both simulations andexperimental results, a variable DC Link voltage produces a

0.5 0.52 0.54 0.56 0.58 0.6 0.62−10

−8

−6

−4

−2

0

2

4

6

8

10

t [s]

curr

ents

[A]

a)

0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1−15

−10

−5

0

5

10

15

t [s]

curr

ents

[A]

b)

Figure 2: Current pattern at 50 Hz a) and at 5 Hz b)respectively before and after inverter reconfiguration and faulttolerant mode

residual inverse component on the load currents. Furthermore,the DC Link midpoint potential becomes unconstrained [13].

In particular Fig. 2 a) and b) show the load current patternbefore and after fault and reconfiguration at 50 Hz and 5 Hzrespectively. It is evident that in the case of low frequency, theunbalance of the load currents is much greater than at 50 Hzwith serious consequences for the power quality in general.In the case of an electrical drive, such a current unbalancewill results in a greater torque and speed ripple, especially forsmall inertia drives.

Fig. 3 a) show the DQO components computed in thesynchronously rotating reference frame that show clearly howafter fault and reconfiguration such current components cannot be considered constant.

Fig. 3 b) shows the dependency of the amplitude of theD and Q components of current in the rotating referenceframe versus frequency; it is noted that at low frequency theamplitude of the oscillating components is significant and canreach intolerable levels.

By using the same DQO coordinate transformation on themathematical model of the inverter in fault tolerant mode onecan obtain the following dynamical equation for the DC link

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0

2

4

6

8

t [s]

i d, iq, i

o [A]

a)

10−1

100

101

102

100

frequency [Hz]

∆ i d ∆

i q [A]

b)

Figure 3: Oscillating components of id (blue) and iq (green)a) and their amplitude vs output frequency a)

voltages:

3C du1

dt = − (idSq + iqSd) sin (2θ)− (iqSq − idSd) cos (2θ)−−√

2iqSosin (θ) +√

2idSocos (θ)− 2iqSq − 2idSd + 3io

3C du2

dt = − (idSq + iqSd) sin (2θ)− (iqSq − idSd) cos (2θ)−−(√

2iqSo −√

6iq)

sin (θ)−(√

6id −√

2idSo)

cos (θ)

−2iqSq − 2idSd + 3io(3)

where Sd, Sq and S0 are the transformed components of theswitching functions, id, iq and i0 are the current componentsand θ = ωt is the system angle. It is evident that the partialDC Link voltage will be affected by oscillating components atω and 2ω angular frequency. The solution of the system (3) isnot easy and can only be addressed numerically via computersimulation.

III. COMPENSATING STRATEGIES.

A. Direct compensation.

In order to reduce voltage swinging on the DC bus, the firstsolution could be use of large capacitors because this naturallyattenuates voltage variations, but it has drawbacks like highcosts and larger sizes.

0 500 1000 1500 2000−100

0

100

time [ms]

Ure

f [V

]

Figure 4: Reference voltages generated by the current con-trollers before and after the fault.

Different compensating strategies of DC link voltage fluc-tuations can be implemented, but, basically, they can be tracedback to the modification of the reference voltage. This change,in fact, corrects the width of the individual PWM pulses forthe actually operating power devices in order to correct thecharging and discharging phenomena on the partial DC Linkcapacitors [14].

Since the current unbalance depends on voltage unbalancecaused by inverse components, the problem is solved byintroducing an opposite inverse component into the referencevoltages to erase the existing one coming out from DC voltageswinging, so recovering performance on the load current.

It is not difficult to show that by introducing in the ref-erence voltage a compensating term that takes the change ofinstantaneous voltage on the DC Link into account, the outputvoltages and current are properly corrected.

In more details, if ∆V is the voltage variation the partialDC Link voltages can be written as:{

u1 =UDC(stiff)

2 + ∆V

u2 =UDC(stiff)

2 −∆V(4)

where UDC(stiff) is the ideal value of a stiff DC Link voltage.By choosing the reference voltages as:

v′ref =u1 + u2UDC(stiff)

(vref −∆V ) (5)

where vref is the uncompensated reference voltage, v′ref isthe compensated reference voltage, the average voltage valueon the load is not modified and compensation of DC voltageswinging is guaranteed.

This compensating strategy is effective, but requires the DCLink voltage measurement.

Usually the measurement of the DC Link voltage is not per-formed in closed loop systems and in electric drives where thereference voltages are provided by the current regulators witha compensatory term computed by the controllers themselves[15].

Figure 4 show the reference voltage for a three phaseinverter directly generated by the current controllers beforeand after the fault. It is evident from the same Fig. 4 thatthe healthy leg reference voltages are not equal in magnitudeand the difference is just due to the introduced compensatingterm. Figure 5b shows the corresponding pattern of the actual

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0

20

time [s]

Cu

rren

ts [

A]

(a) Currents with compensated modulation before and after the fault

−10 −5 0 5 10

−10

−5

0

5

10

iα [A]i β [

A]

Current space vector

(b) Corresponding Space vector current trajectory

Figure 5: Motor currents at load and related space vectortrajectory at closed loop before and after the fault.

0.41 0.415 0.42 0.425 0.43 0.435 0.44

−2

−1.5

−1

−0.5

0

0.5

1

1.5

2

time [s]

modu

lating

and

carri

er si

gnals

Figure 6: Modulating and carrier signals in the proposedmodified modulation strategy

load currents (which are much more balanced than during un-compensated modulation) and the corresponding space vectortrajectory that reveals to be almost circular, as it should be inthe case of a triplet of balanced currents.

B. Indirect compensation via a modified fault tolerant PWMmanagement.

Since the topology of a fault tolerant three-phase inverteris identical to that of a T-Type converter, it is possible to usesuch similarity to implement a different compensation strategythat use auxiliary bidirectional devices, Unlike traditional faulttolerant inverter, where auxiliary devices only perform the taskof static breakers, new they are PWM-like controlled [16].

0

0.2

0.4

0.6

0.8

1

HA

0

0.2

0.4

0.6

0.8

1

HB

0.21 0.22 0.23 0.24 0.25Time (s)

0

0.2

0.4

0.6

0.8

1

HC

Figure 7: Gate drive waveforms of the reconfiguration bi-directional switches under a fault condition on leg A.

Figure 6 helps to illustrates the modified modulation strat-egy. In the fault-tolerant operation mode the modulating sig-nals of the healthy legs are always 60 degrees phase shifted(thick lines in Fig. 6), whereas the one of the faulted phaseis throughout null. Two biased triangular carrier signals (thinlines in Fig. 6) are compared with the modified voltagereferences, as in the traditional multi level modulation of aT-type inverter. The upper inverter device and the midpointconnected one are driven by comparing the modulating signalsand the upper carrier. Conversely, the lower inverter switchesand the midpoint connected ones are driven by comparingthe modulating signals and the lower carrier. To avoid signalcollisions in control of the midpoint auxiliary devices theswitching pulses coming from the two different comparatorsare subjected to a XOR logic gate.

The auxiliary devices switching frequency equals the mainswitches PWM frequency. Therefore, conventional triacs arenot well suited for the proposed algorithm. Bi-directionalswitches become here mandatory. A uniform sharing of theload current through both capacitors is due to the modulationof the auxiliary switches, thus reducing charge and dischargetransients on the DC Link capacitor.

Simulation results for this compensation strategy are shownhereafter. A fault on the upper IGBT of phase A is emulated.At 0.2 s, the fault is emulated in PSIM environment byswitching-off the upper IGBT of phase A. The upper IGBTwill be forced in the OFF state until the end of systemsimulation. The diode of the upper IGBT is still correctlyworking. In Fig. 7 H array elements waveforms are displayed.As shown by simulation results, the fault is correctly iden-tified and located by the detection subsystem at 0.22 s bythe diagnosis algorithm [17]. The bi-directional switch ofthe faulted leg (A) is permanently forced to OFF state, thereconfiguration switch of the faulted leg is permanently forcedto the ON state to achieve circuit reconfiguration. The bi-directional auxiliary switches of healthy legs are modulatedaccording to the proposed fault-tolerant strategy.

In Fig. 8, load current waveforms and phase-to-neutralvoltage waveforms are shown.

0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 0.32

−5

0

5

Load

Cur

rent

s [A

]

0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 0.32

−200

0

200

Van

[V]

0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 0.32

−200

0

200

Vbn

[V]

0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 0.32

−200

0

200

Time [s]

Vcn

[V]

IA IB IC

Figure 8: Current and phase-to-neutral voltage waveformsunder phase A upper IGBT failure condition.

0.2 0.4 0.6 0.8 1

Time (s)

140

145

150

155

160

Vc1 [V] Vc2 [V]

Figure 9: Voltage waveforms across C1 and C2 DC linkcapacitors, according to the proposed fault-tolerant strategy.

In Fig. 9, voltage waveforms across capacitor C1 and C2 ofthe DC link are plotted. After circuit reconfiguration, a voltageunbalance occurs on the DC Link. As shown by simulationresults, under a fixed 150V DC link voltage, the peak deviationof the DC link midpoint voltage, during post-fault operation,is equal to 6 V and the transient is almost extinguished after0.5 s after fault detection. The steady state voltage ripple is 6V.

Simulation based on this method revealed that the fault-tolerant algorithm with PWM control of auxiliary switchingdevices improves performances and significantly reduces theDC link voltage unbalance by 40%.

A further benefit brought by the proposed algorithm is thereduction of the transient peak voltage.

If compared with the traditional fault-tolerant algorithm,the discussed one significantly reduces the inverse currentcomponent, even at early stage of the transient. This is of keyimportance in electrical drives where inverse and harmoniccurrent components entail an unavoidable derating of themotor.

IV. CONCLUSIONS

The topic of this paper has been the discussion of theperformance in a three-phase fault tolerant inverter with par-ticular attention to load current unbalances due to the DC linkvoltage swinging after the inverter reconfiguration. Capacitorvoltage unbalance does not only affect the average value ofthe synthesized inverter output voltage, but also the inverterperformance in general. Indeed, the inverter performance de-pends on the amplitude of the low frequency DC-link voltagewith respect to the average DC-link voltage. These harmoniccomponents depend on the DC-link capacitor size, and thedistortion introduced from load and grid throughout the DC-link mid-point.

Then the Authors examined the different approaches to com-pensation. The first strategy consists in the direct compensationof the effects of the DC link voltage swinging on the outputvoltage in order to bring the load currents to a condition ofsymmetry and balance. This strategy is very effective, butrequires the direct measurement of the partial voltages on theDC link increasing the whole equipment cost, except when thesystem includes a closed loop current control, for which thecompensating term is naturally calculated by the same currentcontroller.

The second compensation strategy could be defined as"preventing" because it reduces the voltage fluctuations of theDC link in order to limit the resulting unbalance of the loadcurrents to acceptable values for the correct operation of theinverter in its operating field.

This second strategy does not completely eliminate thevoltage variation effects, but does not requires additionalvoltage probes, and reduces the voltage fluctuations to the40% of the non compensated case. This reduction significantlyimproves the current balance and also introduces an elementof additional flexibility allowing the inverter to be controlledas a T-Type also in non fault tolerant mode.

ACKNOWLEDGMENTS

This publication was partially supported by the PONPON04a2_H "i-NEXT" Italian research program. This workwas realized with the contribution of SDES (SustainableDevelopment and Energy Savings) Laboratory - UNINETLAB- University of Palermo.

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