ModelSim OverView

What we already learnedWhat we already learned

● Verilog can model: behavioral, RTL structure● Module: basic unit in Verilog● A tutorial: Module instantiation, stimulus, respone● Procedure block: initial, always

ModelSim RTL simulation1. Create libraries.2. Map to libraries.3. Compile source code and testbenches.4. Load the design.5. Add design stimulus.6. View the simulation results.7. Advance the simulator

ModelSim Tutorial

ModelSim Tool OverView

ModelSim Flow 1

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Link

Vlog order independent

ModelSim use mode

Command Mode

Batch Run

ModelSim Tutorial

Projects

ModelSim: New Project File > New > Project

− *.mpf

Add Existing File

HDL files 路徑名稱不能有中文

Add Existing File

File > Add to Project

Compile

Mouseright click

Load Design

Mouse doubleClick

Simulate > End Simulation.

OPEN CLOSE A PROJECT FILE > OPEN

FILE > CLOSE

ModelSim Tutorial

Projects Folder

Add Folder File > Add to Project > Folder.

Add a sub folder File > Add to Project > Folder.

Move Files to folder HDL

NOTE:NO actual directories created in the file system.

ModelSim Tutorial

Simulation Configuration

Simulation Configuration File > Add to Project > Simulation Configuration.

Loading

ModelSim Tutorial

Project Setting

Right Click > Properties...

Project Setting

ModelSim Tutorial

Waveform Display

Waveform Window

Add wave

View wave Add wave * OR

VIEW > DEBUG WINDOWS > WAVE

Add signals to waveform

Or, Mouse Drag-and-Drop

Zoom-in 2X Zoom-in

2X Zoom-out

Full

Cursor in Wave Window

Rename the Cursor

Mouse Right Click A

Add Cursor

Click Rename

Cursor2 to B

Drag Bto measurethe Delta

Cursor

CURSOR HERE

Window Undock & Dock

Tools > Combine Signal

Save Waveform Format: File > Save

File > LoadSelect wave.do

ModelSim Tutorial

SDF

SDF SDF versions 1.0 through 4.0 vsim

-sdfmin [<instance>=]<filename>-sdftyp [<instance>=]<filename>-sdfmax [<instance>=]<filename>

Exvsim -sdfmax /testbench/u1=myasic.sdf testbench

OrSimulate > Start Simulation> SDF

$sdf_annotate system task $sdf_annotate (["<sdffile>"], [<instance>],

["<config_file>"], ["<log_file>"], ["<mtm_spec>"], ["<scale_factor>"], ["<scale_type>"]);

Ex$sdf_annotate("myasic.sdf", testbench.u1);$sdf_annotate("myasic.sdf", testbench.u1, , , "maximum");

The SDF TIMESCALE construct specifies time units of values in the SDF file. The annotator rounds timing values from the SDF file to the time precision of the module that is annotated. For example, if the SDF TIMESCALE is 1ns and a value of .016 is annotated to a path delay in a module having a time precision of 10ps (from the timescale directive), then the path delay receives a value of 20ps. The SDF value of 16ps is rounded to 20ps. Interconnect delays are rounded to the time precision of the module that contains the annotated MIPD.

ModelSim Tutorial

Library

Appendix