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D.GNANA SAI DATTATREYA REDDY

Mob No : 9493868985Email : gnanasaibtech.sree22@gmail.com, gnanasai.dattatreya@amd.com

Objective: Seeking a challenging and growth oriented job in VLSI frontend to utilize my

skills and abilities and a position that offers me professional growth while being resourceful, innovative and flexible.

SUMMARY:

Working at AMD as consultant from past 1 year and 8 months, through SoCtronics as ASIC Engineer.

Worked on SoC Low power verification, which involved verification of system states and core states in multi voltage SoC’s.

Power aware Gate simulations, Setting up the GateCosim environment

Worked at Soctronics on verifying OVM complaint USB 2.0 using System Verilog for 7 months

EDUCATIONAL QUALIFICATION:

B.Tech in Electronics and Communication with an aggregate of 65% from DRK Institue of Science and Technology, Bowrampet,Qutubullapur Mandal Hyderabad (JNTU) in June-2009

Intermediate (Maths, Physics, Chemistry) with First Class (89%) from Sri Chaithanya Junior College, Kukatpally, Hyderabad in June-2005

SSC with First Class (90.5%) from CAM (EM) High School, Gudur, Nellore in June-2003

TECHNICAL SKILLS:

Programming Languages : C, C++Scripting Languages : C-SHELL, PERLHDL’s : Verilog, System VerilogRelevant Concepts : LEC, Synthesis

Tools used : VCS, Verdi

ACHEIVEMENTS:

Received Spot Recognition Award from AMD for delivering results for the tasks assigned.

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PROJECT PROFILE:

PROJECT #1

Verification X86 processor at Block level

Languages : Verilog, C++Duration : 10 monthsRole : Porting the testcases, running test cases and debugging the failures

Description : Verification of the net list using the Gates-Cosim.

As part of this ported the test cases, developed verification environment for GateCosim, debugged the failures and proposed some RTL coding guidelines which will avoid GateCosim mismatches

For early verification of the SoC, all the blocks are merged together and created merged SoC net list and verified much before the full chip net list is available.

PROJECT #2

Low power verification of next generation Fusion client SoC

Languages : Verilog, System verilog, PERLDuration : 9 monthsRole : Analyzing the specification

Developing the test plan Developing the environment and test bench

Verification of the functionality.

Description : This is a brand new product and it has many low power states, which can be verified only at the SoC level.

Developed the test plan, developed the voltage regulator model for client fusion SoC, and checkers for the checking the critical power signals, and successfully executed all the tasks.

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PERSONAL PROFILE:

Name : Gnana Sai Dattatreya ReddyFathers Name : Venkata Krishna ReddyAddress : Plot No:72, Sri Sai nagar,

Ashok Nagar, Ramachandra Puram, Medak Dist, Andhra Pradesh

Mob no : 9493868985

Date of birth : Sex : MaleMarital status : SingleNationality : IndianLanguages known : English, Telugu & Hindi

(D. Gnana Sai Dattatreya Reddy)