Datapath and Control

Andreas KlappeneckerCPSC321 Computer

Architecture

Administrative Issues

Exam has been graded Grades need to be entered by TA

Attendance in the labs Lab 3 assignment Make-up exam T 2:00pm-2:50pm

Goal of this lecture Revisit the single-cycle processor

datapath control Why are the instructions structured in

the way they are? Multi-cycle processor

The Single-Cycle Processor

Revisited

Instruction Word Formats

Register format

Immediate format

Jump format

op-code rs rt rd shamt functop-code rs rt rd shamt funct

op-code rs rt immediate valueop-code rs rt immediate value

op-code 26 bit current segment addressop-code 26 bit current segment address

6 5 5 16

6 5 5 5 5 6

6 26

Hardware components

PC

Instructionmemory

Instructionaddress

Instruction

a. Instruction memory b. Program counter

Add Sum

c. Adder

ALU control

RegWrite

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Data

Data

Registernumbers

a. Registers b. ALU

Zero5

5

5 3

16 32Sign

extend

b. Sign-extension unit

MemRead

MemWrite

Datamemory

Writedata

Readdata

a. Data memory unit

Address

Datapath for MIPS instructions

Seven control signals

Datapath Each instruction type required

some hardware components Designed the datapaths for the

different instruction types Merged the datapaths

reuse hardware whenever possible use multiplexors to combine

datapaths

R-Format Instructions

Register format

op-code rs rt rd shamt functop-code rs rt rd shamt funct

6 5 5 5 5 6

Datapath for a load and store

1. register access 2. memory access calculation3. read or write from memory4. in the case of a load, write into register file

Datapaths for Instruction Fetch, Memory and R-type Instructions

Note the added multiplexor switching between register 2 and sign-extended immediate value

Control

Selecting the operations to perform (ALU, read/write, etc.) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction Example: add $8, $17, $18 Instruction Format:

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct

ALU's operation based on instruction type and function code

For example, what should the ALU do with this instruction?

lw $1, 100($2)

35 2 1 100

op rs rt 16 bit offset

Control

ALU Control Logic

ALU cntrl

Function

000 and

001 or

010 add

110 sub

111 slt

Depending on instruction,the ALU has to perform one of the five operations

Why is the control for sub110 and not 011?

ALU Control

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (5– 0)

ALUOp0

ALUOp

ALU control block

Instruction ALUOp Instruction Funct field Operationoperation ALUOp1 ALUOp0 Opcode F5 F4 F3 F2 F1 F0lw sw 0 0 lw/sw X X X X X X 010beq 0 1 beq X X X X X X 110add 1 X R-type X X 0 0 0 0 010sub 1 X R-type X X 0 0 1 0 110and 1 X R-type X X 0 1 0 0 000or 1 X R-type X X 0 1 0 1 001slt 1 X R-type X X 1 0 1 0 111

Control

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20– 16]

Instruction [25– 21]

Add

Instruction [5– 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31– 26]

4

16 32Instruction [15– 0]

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1

Instruction [15– 11]

ALUcontrol

ALUAddress

Multi-Cycle Processor

Performance Improvement Fixed cycle time

obviously inefficient Variable cycle time

faster timing more complex

Multiple Clock Cycles break up instructions into one-cycle steps balance amount of work to be done restrict each cycle to use only one major

functional unit store values at end of cycle for use in later cycles

Reuse functional units ALU used to compute address and to increment

PC Memory used for instruction and data

Control signals not just determined by instruction additional complexity is introduced here

Finite state machine can be used for control

Multicycle Approach

Multicycle Datapath

PC

Memory

Address

Instructionor data

Data

Instructionregister

Registers

Register #

Data

Register #

Register #

ALU

Memorydata

register

A

B

ALUOut

Outlook

Discuss the details of the datapath Instruction fetch/decode/execute

cycle Construct the finite state machine

for control More complicated processors: Use

microprogramming to simplify control

Finite state machines: a set of states and next state function (determined by current state + input) output function (determined by current state + input)

Moore machine (output based only on current state)

Finite State Machines

Next-statefunction

Current state

Clock

Outputfunction

Nextstate

Outputs

Inputs