data brief - evalmastergan1 - demonstration board for ...data brief db4284 - rev 1 - august 2020 for...

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Features Half-bridge demonstration board equipped with MASTERGAN1 and able to withstand 600 V VCC input on screw connector or pin strip configured for MASTERGAN1 supply voltages Complete set of features to drive MASTERGAN1 with single or complementary driving signal Embedded deadtime generator to convert single PWM signal into dual complementary LIN and HIN signals with independently adjustable deadtimes On board 3.3 V regulator for external circuitry supply (up to 50 mA) 35°C/W junction to ambient thermal resistance to evaluate large power topologies High frequency connector for MASTERGAN1 GL and GH pin monitoring Spare footprint for low side shunt, external bootstrap capacitors and high voltage high capacitance bulk capacitor RoHS compliant Description The EVALMASTERGAN1 board is an easy to use and quick to adapt tool to evaluate the characteristics of MASTERGAN1 and to quickly create new topologies without the need of complete PCB design. The EVALMASTERGAN1 provides an on-board programmable inputs deadtime generator with a single VCC supply (typ. 6 V). An embedded linear voltage regulator offers 3.3 V rail to supply low voltage logic circuit like microcontrollers or FPGA. Some spare footprints are also included to customize the board to operate with final application. These customizations include: use of separate input signal or single PWM signal, use of external bootstrap diode, separate supply for VCC, PVCC or Vbo and also the use of low side shunt resistor for peak current mode topologies. All pins of MASTERGAN1 are accessible. The EVALMASTERGAN1 is 56 x 70 mm wide, FR-4 PCB resulting in an R th(J-A) of 35 °C/W, without forced airflow. Product status link EVALMASTERGAN1 Demonstration board for MASTERGAN1 high power density half-bridge high voltage driver with two 650 V enhanced mode GaN HEMT EVALMASTERGAN1 Data brief DB4284 - Rev 1 - August 2020 For further information contact your local STMicroelectronics sales office. www.st.com

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Page 1: Data brief - EVALMASTERGAN1 - Demonstration board for ...Data brief DB4284 - Rev 1 - August 2020 For further information contact your local STMicroelectronics sales office. 1 Architecture

Features• Half-bridge demonstration board equipped with MASTERGAN1 and able to

withstand 600 V• VCC input on screw connector or pin strip configured for MASTERGAN1 supply

voltages• Complete set of features to drive MASTERGAN1 with single or complementary

driving signal• Embedded deadtime generator to convert single PWM signal into dual

complementary LIN and HIN signals with independently adjustable deadtimes• On board 3.3 V regulator for external circuitry supply (up to 50 mA)• 35°C/W junction to ambient thermal resistance to evaluate large power

topologies• High frequency connector for MASTERGAN1 GL and GH pin monitoring• Spare footprint for low side shunt, external bootstrap capacitors and high voltage

high capacitance bulk capacitor• RoHS compliant

DescriptionThe EVALMASTERGAN1 board is an easy to use and quick to adapt tool to evaluatethe characteristics of MASTERGAN1 and to quickly create new topologies withoutthe need of complete PCB design.

The EVALMASTERGAN1 provides an on-board programmable inputs deadtimegenerator with a single VCC supply (typ. 6 V). An embedded linear voltage regulatoroffers 3.3 V rail to supply low voltage logic circuit like microcontrollers or FPGA.

Some spare footprints are also included to customize the board to operate with finalapplication. These customizations include: use of separate input signal or singlePWM signal, use of external bootstrap diode, separate supply for VCC, PVCC or Vboand also the use of low side shunt resistor for peak current mode topologies.

All pins of MASTERGAN1 are accessible.

The EVALMASTERGAN1 is 56 x 70 mm wide, FR-4 PCB resulting in an Rth(J-A) of 35°C/W, without forced airflow.

Product status link

EVALMASTERGAN1

Demonstration board for MASTERGAN1 high power density half-bridge high voltage driver with two 650 V enhanced mode GaN HEMT

EVALMASTERGAN1

Data brief

DB4284 - Rev 1 - August 2020For further information contact your local STMicroelectronics sales office.

www.st.com

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1 Architecture and components placement

Figure 1. EVALMASTERGAN1 – top component placement

Figure 2. EVALMASTERGAN1 – bottom component placement

EVALMASTERGAN1 Architecture and components placement

DB4284 - Rev 1 page 2/13

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2 Board power-up and input connection

The following image shows how to supply MASTERGAN1, how to provide LIN and HIN inputs and set theprogrammable deadtime generator.

Figure 3. EVALMASTERGAN1 – Supply and signal connection

The LIN, HIN inputs can be supplied from the on-board deadtime generator or directly from an external generator(as DSP/MCU) with the following settings:

Table 1. Connector map

Ref.Pin

#Name Function Description

J2

1 VCC INPUT power Board supply voltage: set to a value between 4.5 V and 6 V

2 VDD (3V3) OUT power Output voltage of on-board 3.3 V regulator: it can be used to supplyexternal circuitry (50 mA max.)

3 GND PWR Board reference potential

4 HIN_B OUT digital Buffered HIN signal (0-3.3 V level output)

5 LIN_B OUT digital Buffered LIN signal (0-3.3 V level output)

6 GND PWR Board reference potential

7 PWM INPUT digital PWM input signal (0 to 3.3 V or 5 V) – see Table 3

8 SD_IN INPUT digital Disable input signal (0 to 3.3 V or 5 V) – see Table 3

9 GND PWR Board reference potential

J3

1 HIN OUT (INPUT) digital

The pin is connected to HIN pin of MASTERGAN1: the pin can beused either to monitor the output of the deadtime generator or toforce the input to MASTERGAN1 according to the status of R4 (seeTable 2)

2 GND PWR Board reference potential

3 GND PWR Board reference potential

4 LIN OUT (INPUT) digital

The pin is connected to LIN pin of MASTERGAN1: the pin can beused either to monitor the output of the deadtime generator or toforce the input to MASTERGAN1 according to the status of R7 (seeTable 2)

EVALMASTERGAN1 Board power-up and input connection

DB4284 - Rev 1 page 3/13

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Ref.Pin

#Name Function Description

J4 1,2,3 HV INPUT powerThese three pins are connected to VS pins of MASTERGAN1:connect high voltage potential to this pin according toMASTERGAN1 recommended values (520 V)

J5 1,2,3 OUT OUTPUT power These three pins are connected to OUT pins of MASTERGAN1:connect the load to this terminal (resonant tanks, transformers,…)

J6 1,2,3 LS_S POWER

These three pins are connected to SENSE pins of MASTERGAN1:the board is configured with shorted sense resistor (R15), thereforethis pin can be connected to the reference voltage of high voltagepotential (GND_P)

J121 VCC INPUT power Board Supply voltage: set to a value between 4.5 V and 6 V

2 GND POWER Board reference potential

CN1 GH OUTPUTTo be used with proper MMCX male connector to monitor the GH pinof MASTERGAN1 with high bandwidth, high voltage differentialprobes (optically isolated probes are recommended)

CN2 GL OUTPUTTo be used with proper MMCX male connector to monitor the GL pinof MASTERGAN1 with high bandwidth differential probes (opticallyisolated probes are recommended)

Table 2. Device input selection

R4, R7 Input source Function and description

0-47 Ω (closed) J2: PWM pin LIN & HIN are generated by the on-board deadtime generatorfrom a single PWM signal on J2, PIN 7.

Open J3: LIN & HIN pinDirect connection to LIN & HIN MASTERGAN1 pins.

LIN, HIN input range: up to 20 V

Table 3. Input signal truth table

SD_IN PWM LIN HIN

L X L L

H L H L

H H L H

The recommended power-on sequence is to turn VCC on first, then apply the HV bus voltage. The recommendedpower-off sequence is to turn off the HV bus supply first, then VCC.

EVALMASTERGAN1 Board power-up and input connection

DB4284 - Rev 1 page 4/13

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3 Schematic diagram

Figure 4. EVALMASTERGAN1 schematic – high density power driver

PGND

GND_

POWE

R

BOOT

_IN

LS_S

47R

VCC

VCC

HV

PVCC

VCC

VCCHV

PVCC

BOOT

HV

VCC

OUTb

GL

GH

LIN

HIN

SD_I

N

PGND

LS_S

TP13

C19

330p

F/X7

R

R13

0R

J060

3

D5 BZT5

85B6

V2T

SOD5

23

TP14

TP8

C10

1uF/

25V/

X5R

C080

5

R10

1k

C15

4.7u

F/25

VC0

805

D3A

N.M

.TU

MD2

SM12

TP2

C17

47nF

/25V

/X7R

C040

2

J9 N.M

.

1 2

D4 BZT5

85B6

V2T

SOD5

23

R17

N.M

.J0

805

C14

N.M

.C0

402

C16

47nF

/25V

/X7R

C040

2

R12

0R

J060

3J4

1 2 3

TP9

C23

22pF

/25V

TP15

C13

47nF

/25V

/X7R

C040

2

TP3

J6

1 2 3TP

6

TP18

TP10

TP11

D3

N.M

.SM

A12

TP4

J5

1 2 3

TP16

R21

10R

R060

3

R16

N.M

.J0

805

R14

10R

R080

5

C18

N.M

.C0

402

R9 10k

R15

0R

C22

1uF/

10V/

X7R

C060

3

TP12

JP3 CL

OSED

J060

3

J1 N.M

.

1 2

C11

1uF/

25V/

X5R

C080

5

J11

N.M

.

1 2

J7 N.M

.

1 2

JP1 OP

ENJ0

603

U6 PVCC

1GL

2

PGND

3

SENSE4

SENSE5

SENSE6

SENSE7

SENSE8

SENSE9

SENSE10

SENSE11O

UT12

OUT

13O

UT14

VS15

VS16

VS17VS

18

VS19

GH20

OUT

b21

BOO

T22

LIN

24

SD/D

IAG

25HI

N26

VCC

27

GND

28

EP1_

GND

32

EP3_

OUT

34

EP2_SNS33

TP19

C20

22pF

/25V

J10

N.M

.

1 2 3

R11

0R

J060

3

TP17

SD

SD

HIN

LIN

PGND

PGND

OUTBO

OTpi

n

VCCp

in

PGND

PVCC

pin

OUT

BOOT

pin

OUTb

PVCC

pin

LIN

HIN

OUTb

MAST

ERGA

N1

EVALMASTERGAN1 Schematic diagram

DB4284 - Rev 1 page 5/13

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Figure 5. EVALMASTERGAN1 schematic – deadtime generator and connectors

HS D

T

NOT

BUFF

ERLS

DT

BUFF

ERBU

FFER

LS V

gs

HS V

gs

Elec

tr.

P 10

VDD

VDD

VDD

VDD

VDD

VDD

VCC

VCC

VCC

HV

HIN

LIN

GHGL

OUTb

SD_I

N

PGND

U4 74LV

C1G1

7W5

NC1

A2

GND

3Y

4VC

C5

C7 330p

F/X7

RC0

603

C29

N.M

.C2

225

C6

100n

F/25

V/X7

R

C060

3

R447

R

R060

3

R3N.

M.

J060

3

J21 2 3 4 5 6 7 8 9

TR1

1K

R20

0R

J060

3

U2 74LV

C1G1

7W5

NC1

A2

GND

3Y

4VC

C5

CN1

BNC

conn

.

S1

G12

G23

G34

G45

R6N.

M.

J060

3

C25

1uF/

10V/

X7R

C060

3

R23

0RJ0

603

R8 47k

R060

3

C24

100n

F/25

V/X7

RC0

603

C3 330p

F/X7

RC0

603

JP2

OPEN

J060

3

C26

1uF/

10V/

X7R

C060

3

R19

0R

J060

3

J12

1 2

TR2

1K

C5

100n

F/25

V/X7

R

C060

3

C8 22pF

/25V

C060

3

U5KF

33BD

-TR

Vout

1

GND

3GN

D2

GND

6GN

D7

Vin

8

INH

5

C28

470n

F/63

0V/X

7RC2

225

J31 2 3 4

D2BA

S70J

sod-

323

12

CN2

BNC

conn

.

S1

G12

G23

G34

G45

R10R

R040

2

+C2

7N.

M.

U3 74LV

C1G1

4W5

NC1

A2

GND

3Y

4VC

C5

R22

0RJ0

603

U1 74LV

C1G1

7W5

NC1

A2

GND

3Y

4VC

C5

C1

100n

F/25

V/X7

R

C060

3

R20R

R040

2

D1BA

S70J

sod-

323

12

C2

100n

F/25

V/X7

R

C060

3

R18

0R

J060

3

R747

R

R060

3

HIN_

B

LIN_

B

PWM

HIN_

BLI

N_B

PWM

EVALMASTERGAN1 Schematic diagram

DB4284 - Rev 1 page 6/13

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4 Bill of material

Table 4. Bill of material

Item Q.ty Ref. Value Description Manufacturer Part Number

1 2 CN1, CN2 BNC connector MMCX straightreceptacle Cinch 135-3701-201

2 5 C1, C2, C5,C6, C24

100 nF/X7R,

Size 0603,

25 V,

SMT ceramiccapacitor

5 2 C10, C11

1 uF/X5R,

Size 0805,

25 V,

SMT ceramiccapacitor

6 3 C13, C16,C17

47 nF/X7R,

Size 0402,

25 V,

SMT ceramiccapacitor

7 2 C14, C18N.A.,

Size 0402,SMT ceramic

capacitor

8 1 C15

4.7 uF/X7R,

Size 0805,

25 V,

SMT ceramiccapacitor

9 3 C22, C25,C26

1 uF/X7R,

Size 0603,

10 V,

SMT ceramiccapacitor

10 1 C27 N.A. Electrolytic Cap,Diam. 22 p. 10,

11 1 C28470 nF/X7R, Size2225,

630 V,

SMT ceramiccapacitor

12 1 C29

N.A.,

Size 2225,

630 V,

SMT ceramiccapacitor

13 2 D1, D2 BAS70J Schottky diodes STMicroelectronics BAS70JFILM

14 1 D3 N.A.600 V, 1A, turbo 2

ultrafast high voltagerectifier

STMicroelectronics STTH1R06A

15 1 D3A N.A. 600 V, 0.2 A super-fast recovery diodes

ROHMSemiconductor RFU02VSM6S

16 2 D4, D5 BZT585B6V2T ZENER 6.2 V 300mW Diodes Incorporated BZT585B6V2T

17 2 JP1, JP2Open,

Soldering pads,SMT jumper

18 3 J1, J7, J9 N.A.Strip connector 2 pos,

2.54 mm

19 1 J2 STRIP 1x9Strip connector 9 pos,

2.54 mm

EVALMASTERGAN1 Bill of material

DB4284 - Rev 1 page 7/13

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Item Q.ty Ref. Value Description Manufacturer Part Number

20 1 J3 STRIP 1x4Strip connector 4 pos,

2.54 mm

21 3 J4, J5, J6 STRIP 1x3Strip connector 3 pos,

2.54 mm

22 1 J10 N.A. Strip connector 3 pos,2.54 mm

23 1 J11 N.A.Strip connector 2 pos,

2.54 mm

24 1 J122P_screw,

pitch 5.08 mm,Terminal block T.H. 2

pos, 5.08 mm Wurth Elektronik 691213510002

25 2 R1, R2 0R, Size 0402 SMT resistor

26 2 R3, R6 N.A., Size 0603 SMT resistor

27 2 R4, R7 47R, Size 0603 SMT resistor

28 1 R8 47k, Size 0603 SMT resistor

29 1 R9 10k, Size 0603, SMT resistor

30 1 R10 1k, Size 0603, SMT resistor

31 9

R11, R12,R13, R18,R19, R20,R22, R23,

JP3

0R, Size 0603, SMT resistor

32 1 R14 10R, Size 0805, SMT resistor

33 1 R15 Closed,Soldering pads, SMT jumper

34 2 R16, R17N.A.,

Size 0603,SMT resistor

35 1 R21 10R, Size 0603, SMT resistor

37 2 TR1, TR2 1K, 12 turns5 mm 12 turns surface

mount miniaturetrimmers

BOURNS 3224W-1-102E

38 3 U1, U2, U4 74LVC1G17W5 Single Schimitt-Trigger buffer Diodes Incorporated 74LVC1G17W5 / -7

39 1 U3 74LVC1G14W5 Single Schimitt-Trigger inverter Diodes Incorporated 74LVC1G14W5 / -7

40 1 U5 KF33BD-TR Very low drop voltageregulators with inhibit STMicroelectronics KF33BD-TR

41 1 U6 MASTERGAN1

High power densityhalf-bridge high

voltage driver with two650 V enhanced

mode GaN HEMT

STMicroelectronics MASTERGAN1

EVALMASTERGAN1 Bill of material

DB4284 - Rev 1 page 8/13

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Revision history

Table 5. Document revision history

Date Version Changes

06-Aug-2020 1 Initial release.

EVALMASTERGAN1

DB4284 - Rev 1 page 9/13

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Contents

1 Architecture and components placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 Board power-up and input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

EVALMASTERGAN1 Contents

DB4284 - Rev 1 page 10/13

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List of tablesTable 1. Connector map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Table 2. Device input selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Table 3. Input signal truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Table 4. Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 5. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

EVALMASTERGAN1 List of tables

DB4284 - Rev 1 page 11/13

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List of figuresFigure 1. EVALMASTERGAN1 – top component placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Figure 2. EVALMASTERGAN1 – bottom component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Figure 3. EVALMASTERGAN1 – Supply and signal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 4. EVALMASTERGAN1 schematic – high density power driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 5. EVALMASTERGAN1 schematic – deadtime generator and connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

EVALMASTERGAN1 List of figures

DB4284 - Rev 1 page 12/13

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IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to STproducts and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. STproducts are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design ofPurchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or servicenames are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2020 STMicroelectronics – All rights reserved

EVALMASTERGAN1

DB4284 - Rev 1 page 13/13