curtis lcd2226fr manual

Model: LT2298 MST106

1. Safety Precaution..……………………………………………………….1~2

2. Production Specification ……………………………………………….3~4

3. Remote Control View …………………………………………………….5~7

4. Circuit Diagram and Component Position …………………………….8~ 18

5. Basic Operations & Circuit Description …………………………….19~22

6. Main IC Information……………………………………………………….23~224

7. Panel Information………………………………………………………….225~247

8. PSU Information…………………………………………………………….248～266

9. BOM List……………………………………………………………. 267～273

10.Software Upgrade Reference…………………………………………….202~207

This manual is the latest at the time of printing, and does not

include the modification which may be made after the printing,

by the constant improvement of product.

SERVICE MANUAL

PRODUCT SAFETY NOTICE

Many electrical and mechanical parts in thisapparatus have special safety-relatedcharacteristics.

These characteristics are offer passedunnoticed by visual spection and the protectionafforded by them cannot necessarily be obtainedby using replacement components rates for ahigher voltage, wattage, etc.

The replacement parts which have thesespecial safety characteristics are identified by marks on the schematic diagram and on the partslist.

Before replacing any of these components,read the parts list in this manual carefully. Theuse of substitute replacement parts which do nothave the same safety characteristics as specifiedin the parts list may create shock, fire, or otherhazards.9. Must be sure that the ground wire of the ACinlet is connected with the ground of theapparatus properly.

5. When replacing a MAIN PCB in the cabinet,always be certain that all protective areinstalled properly such as control knobs,adjustment covers or shields, barriers, isolationresistor networks etc.

6. When servicing is required, observe the originallead dressing. Extra precaution should be givento assure correct lead dressing in the highvoltage area.

7. Keep wires away from high voltage or hightempera ture components.

8. Before returning the set to the customer,always perform an AC leakage current checkon the exposed metallic parts of the cabinet,such as antennas, terminals, screwheads,metaloverlay, control shafts, etc., to be sure the setis safe to operate without danger of electricalshock. Plug the AC line cord directly to theAC outlet (do not use a line isolationtransformer during this check). Use an ACvoltmeter having 5K ohms volt sensitivity ormore in the following manner.Connect a 1.5K ohm 10 watt resistor paralleledby a 0.15µF AC type capacitor, between agood earth ground (water pipe, conductor etc.,)and the exposed metallic parts, one at a time.Measure the AC voltage across the combinationof the 1.5K ohm resistor and 0.15 uFcapacitor. Reverse the AC plug at the ACoutlet and repeat the AC voltage measurementsfor each exposed metallic part.The measured voltage must not exceed 0.3VRMS.This corresponds to 0.5mA AC. Any valueexceeding this limit constitutes a potentialshock hazard and must be correctedimmediately.The resistance measurement should be donebetween accessible exposed metal parts andpower cord plug prongs with the power switch"ON". The resistance should be more than6M ohms.

Good earth groundsuch as the waterpipe, conductor,etc.

Place this probeon each exposedmetallic part

AC VOLTMETER

AC Leakage Current Check

2／1082／113

Product Specification General Description 1. Main features Production Description Panel Supplier and Model Main Chip Market

CX LCD TV 22” PAL/SECAM System AC100V-240V LPL:V216B1-P01Mstar106Europe

1.1 VIDEO SECTION Display size 21.6 inch 16:9Display Resolution 1366X768 Pixel Pitch 0.1165(H)mm×0.3495(V)mm Peak Brightness 400 cd/m2

Contract Ratio 800:1 View Angle Hor. : =170 And Vert. =160 degree Color Deeps 16.7M Color PC Resolution Supporting VGA ,SVGA,XGA HDTV Compatible 480p, 576p, 720p, 1080i,1080p 50/60Hz Picture Size Y es Picture Mode Yes Advanced 3D Noise Reduction YesColor Temperature Control Yes Comb Filter Yes (3D)Second De-interlace for Sub picture No Picture Freeze Function Yes ATV RF System PAL BG/DK/I, SECAM BG/DK/L/L' DTV System MODULATION COFDM,2k/8k QPSK,16/64QAMDTV VIDEO SYSTEM MPEG-2 MP@ML DTV SOUND SYSTEM MPEG-1 Layer1,2 / MPEG-2 Layer 2

1.2 AUDIO SECTION

Audio Output Power (10%THD) 2W×2 Sound Mode (Preset) Yes SRS NoSurround YesTone Control Yes 1.3 Input Terminals

Antenna Input (Din Type) ×1 Video (RCA) Input × 1 S-Video Input ×1 VGA Input ×1 SCART ×1 Stereo Audio Input×2

1.4 Output Terminals No1.5 Others

Closed Caption / V-Chip No Teletext Yes

WEST/EAST/RUSSIAN/FARSI Teletext Language OSD Language English/French//Spanish/Portuguese/Italian/German

3／113

Stereo Decode Yes Power Rating AC 100-240V, 50/60Hz Power Consumption <60W 1.6 Support the Signal Mode This machine can support the different from VGA signal mode in 4 kinds No

Resolution

Horizontal Frequency(Hz)

Vertical Frequency(KHz)

1) 640×480 31.50 60.00 2) 800x600 35.16 56.25

37.90 60.00 3) 800x600 50.00

1.7 SDTV / HDTV /HDMI(YCbCr / YPbPr)

No

Resolution

Horizontal Frequency(KHz)

Vertical Frequency(Hz)

1) 480i 15.734 60.00 60.002) 480p(720×480) 31.468 3) 576i(720×576) 15.625 50.00

4) 576p(720X576) 31.250 50.00 5) 720p(1280×720) 37.50 50.00 6) 720p(1280×720) 45.00 60.00 7) 1080i(1920×1080) 28.13 50.00

8) 1080i(1920×1080) 33.750 60.00

4／113

4) 1024x768 48.4 60.00

- C X 5 0 6

Remote Control View

previouse

Enter

CLOCK Teletex clock on and off

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC-OP2

VCC-OP2

VCC-OP2

AMP-PLout

AMP_RIN1

MUTE_AMP

AMP_LIN1 AMP-PLout

AMP-PRout

MUTE_AMP

PWD_MT

AMP-PRout

VCC-OP2

PWD_MT

SP_RSP_R

SP_LSP_L

12VA

12VA

6VA

6VA

6VA

6VA

12VA

12VA

3.3VU

MUTE_AMP3

AUOUTR03

LINEOUTL 9

AUOUTR13

AUOUTL13

LINEOUTR 9

AUOUTL03

PWR-ON/OFF1,3

TDA1517PAUDIO OP

Near MST.IC

Ground in the middle of the L/R

HOLE

Near MST.ICGround in the middle of the L/R

2009-9-29

R2764.7KR2764.7K

1 H12TPAD

H12TPAD

R275 4.7KR275 4.7K

R183

NC

R183

NC

C23

618

nC

236

18n

+CA51

100uF/16V

+CA51

100uF/16V R27947KR27947K

R29

913

KR

299

13K

C23

91n

C23

91n

+ CA52100uF/16V

+ CA52100uF/16V

R30147KR30147K

1 H5TPAD

H5TPAD

R374 3.3KR374 3.3K

R298 47KR298 47K

R41.2KR41.2K

1 H8TPAD

H8TPAD

C24

510

0nF

C24

510

0nF

C234 100pC234 100p

C26

018

nC

260

18n

R29

622

KR

296

22K

1

23

Q36NCQ36NC

C31

00.

1uC

310

0.1u

3

21

84

-

+U33ATL062

-

+U33ATL062

+ CA55470uF/16V

+ CA55470uF/16V

R371 0RR371 0R

C252 100pC252 100p

5

67

84

-

+U33B TL062

-

+U33B TL062

R30

213

KR

302

13K

CA464100uF/16V

CA464100uF/16V

C23

31n

C23

31n

R330 NC-470RR330 NC-470R

R30910KR30910K

1

23

Q243904Q243904

Q223906Q223906

123

45

6

7

8 9

H6PAD

H6PAD

R293 1KR293 1K

R315 NCR315 NC

R325470RR325470R

R292

10k

R292

10k

1 H13TPAD

H13TPAD

R11 NCR11 NC

1

H47TPADH47

TPAD

R127

10K

R127

10K

R3331.2KR3331.2KR179

NC

R179

NC

11223344

CN21

CON4_2.54/NC

CN21

CON4_2.54/NC

+CA62 470uF/16V+CA62 470uF/16V

1 H9TPAD

H9TPAD

C26

4 ncC

264 nc

C247 2.2uC247 2.2u

22 33 77

6644

55

88

11HP1

HP-JACK

HP1

HP-JACK

R373 4.7KR373 4.7K

R1

1.2K

R1

1.2K

R355 0RR355 0R

C23

82.

2uC

238

2.2u

123

45

6

7

8 9

H4PAD

H4PAD

R2861KR2861K

C246 100pC246 100p

R28410RR28410R

R305 100RR305 100R

R278 100RR278 100R

1

H51TPADH51TPAD

R2832.2MR2832.2M

C257 2.2uC257 2.2u

R294 100RR294 100R

C23

718

nC

237

18n

R274100RR274100R

+CA50

470uF/16V+

CA50

470uF/16V

123

45

6

7

8 9

H1PAD

H1PAD

R13 NCR13 NC

C244

470U/10V

C244

470U/10V

DD51NC-EZJZ1V270RA/NCDD51NC-EZJZ1V270RA/NC

R28147KR28147K

1 H10TPAD

H10TPAD

C26

8ncC26

8nc

1

H48TPADH48TPAD

R306 10KR306 10K

R285 47KR285 47K

R311 100RR311 100RC31210uF/6.3VC31210uF/6.3V

R322470RR322470R

R28010KR28010K

C243

47U/16V

C243

47U/16V

C2412.2uC2412.2u

R6410KR6410K

1

H50TPADH50TPAD

R35

222

KR

352

22K

3

12

DD32BAV99

DD32BAV99


DD

64NC

-EZJ

Z1V

270R

A/N

CD

D64N

C-E

ZJZ1

V27

0RA

/NC

R331NC-1KR331NC-1K

R2902.2MR2902.2M

1

23

Q23NC-3904Q23NC-3904

R308 47KR308 47K

C31110uF/6.3VC31110uF/6.3V

5

67

84

-

+U32B TL062

-

+U32B TL062

R291 10KR291 10K

R303 NCR303 NC

1

23

Q25NC-3904Q25NC-3904

C25

918

nC

259

18n

R28747KR28747K

3

21

84

-

+U32ATL062

-

+U32ATL062

R30

413

KR

304

13K

R314 47KR314 47K

R144

10K

R144

10K

L25 10uHL25 10uH

1 H11TPAD

H11TPAD

11223344

CN20

CON4_2.54/NC

CN20

CON4_2.54/NC

DD

56N

C-E

ZJZ1

V27

0RA

/NC

DD

56N

C-E

ZJZ1

V27

0RA

/NC

C256 2.2uC256 2.2u

R307 10KR307 10K

+CA61 470uF/16V+CA61 470uF/16V

1 H7TPAD

H7TPAD

R376 4.7KR376 4.7K

1 H49TPADH49TPAD

C2292.2uC2292.2u

123

45

6

7

8 9

H3PAD

H3PAD

R5710KR5710K

C2422.2uC2422.2u

R12 NCR12 NC

123

45

6

7

8 9

H2PAD

H2PAD

INV11

GN

D2

SVRR3

OUT1 4

GN

D5

OUT2 6

VP7

M/SS8

INV29

GN

D10

GN

D11

GN

D12

GN

D13

GN

D14

GN

D15

GN

D16

GN

D17

GN

D18

GN

D19

GN

D20

U31TDA1517U31TDA1517

C235 2.2uC235 2.2u

1

23

Q37NCQ37NC

CA465100uF/16V

CA465100uF/16V

R28

813

KR

288

13K

R295 10KR295 10K

R332

1.2K

R332

1.2K

C240 100pC240 100p

R28922KR28922K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+5V_USBO

USB_OCD_N

USB_DPOUSB_DMO

+5V_USBO

USB_DPOUSB_DMO

5VA

USB_DP3USB_DM3

USB_OCD_N 3

C1430.1UC1430.1U

DD58

EZJZ1V80010

DD58

EZJZ1V80010

1234

CON42

CON4_2.0

CON42

CON4_2.0

R282 0RR282 0R

R32851KR32851K

DD44

EZJZ1V80010

DD44

EZJZ1V80010

1 2

F3SMD1206P100TFF3SMD1206P100TF

R297 0RR297 0R

R272100KR272100K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AV1-V

AVOUT-V

AVOUT-VAV1-V

Pr

AV1-L

SC1_FSO SC1_FSO

LINEOUTRAV1-RLINEOUTL

Pb

Y

VGAT_B

VGAT_G

VGAT_R

VGA-G

VGA-B

VGA-R

DDC-SCLIN

VGA-HS

DDC-SCLDDC-SDA

VGA-VS

VGA-HS

VGA-VS

VGA-HS

VGA-VS

DDC-SDAIN

DDC-SDAIN

DDC-SCLIN

VGA-B

VGA-R

DDC-SDA

DDC-SCL

VGA-G

AV1-L

AV1-R

SV1-YSV1-C

Y

Pb

Pr

SV2-Y

SV2-CHD-Y

HD-Pb

HD-Pr

SPDIFOUT

SPDIFOUT

AV3-R

AV3-V

AV3-L

AV3-V

AV3-L

AV3-R

Comp_L

Comp_R

SV1-C

SV1-Y

SV1-C

SV1-Y

AV2-R

AV2-L

SV2-Y

SV2-C

DVD_PBIN

DVD_YIN

DVD_PRIN

HD-Y

HD-Pb

HD-Pr

VGA-BVGA-G

VGA-R

RGB1_GiRGB1_BiRGB1_Ri

RGB1_GiVGAT_BVGAT_G

DVD_PBIN

VGAT_R

DVD_PRIN

RGB1_BiRGB1_Ri

DVD_YIN

Y

Pb

Pr

DVD_ON/OFF

AV2-L

AV2-R

HD-Y

HD-Pb

HD-Pr

5VA

5VPI

VGA-5V

VGA-5V

5VA

5VU

5VA

5VA

5VPI

5VPI5VA

12VU

3.3VU

5VA

AV1-Vin+ 3

CVBS_OUT3

SC1_FS 3

LINEOUTL 11

LINEOUTR 11

SC1_FB 3

ISP-RXD 3

VGA_HSYNC1 3

VGA_VSYNC1 3

VGA-Lin 3

VGA-Rin 3

ISP-TXD 3

AV1-Lin 3

AV1-Rin 3

RGB0-SOG 3

RGB0_BIN+ 3

RGB0_GIN+ 3

RGB0_RIN+ 3

DVDIR_EN3

IR_in3

DVD_ON/OFF3

SPDIFO3

DVD_ON/OFF3

AV3-Vin+ 3

HD-Lin 3

HD-Rin 3

SV1-Yin 3

SV1-Cin 3

AV2-Lin 3

AV2-Rin 3

SV2-Yin 3

SV2-Cin 3

RGB1_SOG 3

RGB1_R+ 3

RGB1_G+ 3

RGB1_B+ 3

HD-VSW03

DVD_ON/OFF

VIDEO_OUT

SCART

If U6=24C01/24C02,you shouldsolder R125 and left R119 float

VGA INPUT

Keep AGND trace with signal Keep spacing for L/R

DVD CONNECTOR

DVD CONTROL

CLOSED TO MSD109

SPDIF Output

SPDIF Switc

Keep AGND trace with signal Keep spacing for L/RKeep trace width(12mil+)

实贴

单排

AV插

座

R174 NC/4.7KR174 NC/4.7K

R94 0/NCR94 0/NC

R114 100RR114 100R

C87 10UC87 10U

R125NCR125NC

C33560pC33560p

R4675RR4675R

C186

0.1uF

C186

0.1uF

C22 2.2uC22 2.2u

R22547KR22547K

L24 0RL24 0R

R6015kR6015k

L45 FBL45 FB

L11 0RL11 0R

DD17EZJZ1V270RA/NC

DD17EZJZ1V270RA/NC

DD60

EZJZ1V270RA

DD60

EZJZ1V270RA

DD14EZJZ1V270RA/NC

DD14EZJZ1V270RA/NC

S1A2S1B5S1C11S1D14

S2A3S2B6S2C10S2D13

IN1

DA 4DB 7DC 9DD 12

VCC 16

GND 8EN 15

U17

PI5V330

U17

PI5V330

C96 47nC96 47n

R1540RR1540R

R10

922

KR

109

22K

DD59

EZJZ1V270RA

DD59

EZJZ1V270RA

R156 0RR156 0R C140.1uC140.1u

R12

210

KR

122

10K

C91 10UC91 10U

DD63

EZJZ1V270RA/NC

DD63

EZJZ1V270RA/NC

R36 10KR36 10K

R8212KR8212K

NC1NC2NC3GND4 SDA 5SCL 6VCLK 7VCC 8

U6 24C21U6 24C21

34

2 1

56

7

CON16 S-VdieoCON16 S-Vdieo

R23

675

RR

236

75R

+ CA5

470u

F/16

V + CA5

470u

F/16

V

R3412KR3412K

L1

NC/FB 600(4.5X3.2)

L1

NC/FB 600(4.5X3.2)

DD31

NC-EZJZ1V270RA

DD31

NC-EZJZ1V270RA

D80R D80RR111 100RR111 100R

R21647KR21647K

R12

975

RR

129

75R

12345

CON4

CON5-2.0/NC

CON4

CON5-2.0/NC


R130 47RR130 47R

L68FB220/100mAL68FB220/100mA

C47560pC47560p

R101 10KR101 10K

C90 10UC90 10U

R11

075

RR

110

75R

R21147KR21147K

R232

75

R232

75

R131 47RR131 47R

1234

CON13

CON6_2.0mm

CON13

CON6_2.0mm

L13 0RL13 0R

R79 470RR79 470R

C34560pC34560p

R8912KR8912K

DD19

EZJZ1V270RA

DD19

EZJZ1V270RA

C65560pC65560p

C26560pC26560p

R83 47RR83 47R

R51 47RR51 47R

C17 47nC17 47n

C43 1nC43 1n

R105 100RR105 100R

C18NCC18NC

R113 0RR113 0R

R29 47RR29 47R

S11

S33G14

D1 8D2 7D3 6D4 5

S22

U19

9435SOIC08

U19

9435SOIC08

DD52EZJZ1V270RADD52EZJZ1V270RA

R5075RR5075R

C38560pC38560p

C16 47nC16 47n

R80 10KR80 10K

C63 2.2uC63 2.2u

C21330pC21330p

DD41

EZJZ1V270RA

DD41

EZJZ1V270RA

R19547KR19547K

R23010

R23010

C89 10UC89 10U

C48 47nC48 47n

1

H39TPADH39TPAD

C27330pC27330p

DD23NC-EZJZ1V270RADD23NC-EZJZ1V270RA

R59 390RR59 390R

C155

0.1uF

C155

0.1uF

C76NCC76NC

R42 10KR42 10K

1234

CON12

CON4-2.0

CON12

CON4-2.0

C97 8.2nC97 8.2n

R33 47RR33 47R

R86

75R

R86

75R

R19247KR19247K

R71NCR71NC

1H44

TPADH44

TPAD

C64330pC64330p

C42 47nC42 47n

R40 10KR40 10K

R40

94.

7KR

409

4.7K

1

H42TPAD

H42TPAD

DD5

NC-EZJZ1V270RA

DD5

NC-EZJZ1V270RA

Q323906Q323906

1

H38TPADH38TPAD

R70 1KR70 1K

1

H23TPADH23TPAD

C59NC_0.1u

C59NC_0.1u

R112 10KR112 10K

R63120RR63120R

1

H45TPADH45

TPAD

R2298.2KR2298.2K

C28010uF/6.3VC28010uF/6.3V

R77NCR77NC

L29 0RL29 0R

R62 75RR62 75R

C66 2.2uC66 2.2u

DD61

EZJZ1V270RA

DD61

EZJZ1V270RA

L28 0RL28 0R

DD18EZJZ1V270RA/NC

DD18EZJZ1V270RA/NC

R23

575

RR

235

75R

R10

822

KR

108

22K

R12

875

RR

128

75R

R54 10RR54 10R

C283

10uF

C283

10uF

C85 10UC85 10U

R28 47RR28 47R

DD6

EZJZ1V270RA/NC

DD6

EZJZ1V270RA/NC


R24

675

RR

246

75R

C101NCC101NC

R228

47K

R228

47K

R6910KR6910K

R78330RR78330R

DD11ADUC10S033R3/NCDD11ADUC10S033R3/NC

D9NC-1N4148 D9NC-1N4148

DD13

EZJZ1V270RA/NC

DD13

EZJZ1V270RA/NC

R32 10KR32 10K

C46 47nC46 47n

3

1 2DD48BAT54CDD48BAT54C

1

H24TPADH24TPAD

R11910KR11910K

DD62

EZJZ1V270RA/NC

DD62

EZJZ1V270RA/NC

R21047KR21047K

IN1

VDD2

GND3 S1 4

D 5

S2 6U46

NC_ADG779

U46

NC_ADG779

C55 2.2uC55 2.2u

1

H41TPADH41TPAD

L55

NC/FB 600(4.5X3.2)

L55

NC/FB 600(4.5X3.2)

R95 0/NCR95 0/NC

R11512KR11512K

1H43

TPADH43

TPAD

5104938271

15

14

13

12

116

16 17

CON7 VGACON7 VGA

C28 2.2uC28 2.2u

C51 47nC51 47n

R87

75R

R87

75R

Q133904Q133904

C254560pC254560p

DD45

EZJZ1V270RA/NC

DD45

EZJZ1V270RA/NC

1

2

P16

Y

P16

Y

DD16EZJZ1V270RA/NC

DD16EZJZ1V270RA/NC

R85 10KR85 10K

C77 47nC77 47n

R3075RR3075R

123

CON35

CON3-2.0

CON35

CON3-2.0

L12 0RL12 0R

2

4

6

8

10

12

14

16

18

20

1

3

5

7

9

11

13

15

17

19

21

2425

P14

SCART

P14

SCART


R3812KR3812K

1

H37TPAD

H37TPAD

R84 47RR84 47R

+

CA1

0

470u

F/16

V/N

C

+

CA1

0

470u

F/16

V/N

C

R56470RR56470R

C23 47nC23 47n

213

CON40 RCA1CON40 RCA1

R10612KR10612K


C50 2.2uC50 2.2u

1

H40 TPADH40 TPAD

C45 47nC45 47n

C74330pC74330p

R5833kR5833k

R93 0/NCR93 0/NC

R55 NCR55 NC

C49 47nC49 47n

C73NCC73NC

1

23Q14

3904Q143904

R4312KR4312K

C265 10uF/6.3VC265 10uF/6.3V

DD12

EZJZ1V270RA/NC

DD12

EZJZ1V270RA/NC

1

2

P18

Y

P18

Y

C25NCC25NC

123456

CON34

CON6-2.0

CON34

CON6-2.0

R88

75R

R88

75R

R76 100R76 100

R138 470RR138 470R

R81 47RR81 47R

DD43

EZJZ1V270RA

DD43

EZJZ1V270RA

R14547KR14547K

C20NCC20NC

C68560pC68560p

R3175RR3175R

R48 47RR48 47R

C35 2.2uC35 2.2u



R23447KR23447K

534

21

CON8

PHONEJACK

CON8

PHONEJACK

C79 10UC79 10U

R3575RR3575R

1

2

P17

Y

P17

Y


R22647KR22647K

DD42

EZJZ1V270RA

DD42

EZJZ1V270RA

R196

47K

R196

47K

R510KR510K

R12

110

KR

121

10K

1

3

5

7

8

9

210

4

11

614

15

16

12

13

R

L

V

V

R

L

CON23

RCA_3_1

R

L

V

V

R

L

CON23

RCA_3_1

12

CON10CON2-2.0 CON10CON2-2.0

R5375RR5375R

C37 2.2uC37 2.2u


R132 47RR132 47R

C19330pC19330p

C100 47nC100 47n

R103 100RR103 100R

R231

1.5K

R231

1.5K

C40330pC40330p

R4112KR4112K

C269 10uF/6.3VC269 10uF/6.3V

C41 0.1uC41 0.1u

R45 47RR45 47R

DD10EZJZ1V270RA/NCDD10EZJZ1V270RA/NC

R22747K

R22747K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HOTPLUG

RXB2P

DDCBSCL

RXB0N

RXB2N

RXB0P

RXBCLKP

RXB1PRXB1N

RXBCLKNDDCBSDA

DB2+

DB2-DB1+

DB1-DB0+

DB0-CLKB+

CLKB-

RXB1NRXB1PRXB2NRXB2PRXBCLKNRXBCLKPDDCBSCLDDCBSDA

RXB0NRXB0P

HOTPLUG

cec

cec

CLKB- CLKB+ DB2- DB0+DB0-DB1-DB2+ DB1+

5VA

5VU3.3VU

5VU 5VU5VU 5VU5VU 5VU5VU5VU

HOTPLUG 3

RXB0N3RXB0P3RXB1N3RXB1P3

RXB2P3RXB2N3

RXBCLKN3RXBCLKP3

DDCBSDA3DDCBSCL3

HDMI-CECR152 22KR152 22K

DATA2+ 1DATA2 SHIELD 2

DATA2- 3DATA1+ 4

DATA1 SHIELD 5DAT1A- 6DATA0+ 7

DATA0 SHIELD 8DATA0- 9

CLK+ 10CLK SHIELD 11

CLK- 12CEC 13

NC 14SCL 15SDA 16

DDC/CEC GND 17+5V POWER 18

HOT PLUG 192020

2121

2323 2222

CON9

HDMI

CON9

HDMI

R141 10RR141 10R

R136 10RR136 10R

R377NC/0RR377NC/0R

R1571KR1571K

R142 10RR142 10R

DD

55N

C-E

ZJZ1

V27

0RA

DD

55N

C-E

ZJZ1

V27

0RA

R146 10RR146 10R

DD

50N

C-E

ZJZ1

V27

0RA

DD

50N

C-E

ZJZ1

V27

0RA

R135 10RR135 10RR133 10RR133 10R

R388100RR388100R

3

1

2

DD39BAT54CDD39BAT54C

11

22

33

44

55

66DD25

BAV99DW

DD25

BAV99DW

R159NCR159NC

R137 10RR137 10R

R153 22KR153 22K

11

22

33

44

55

66DD26

BAV99DW

DD26

BAV99DW

11

22

33

44

55

66D62

BAV99DW

D62

BAV99DW

R32427KR32427K

R161 10KR161 10K1

1

22

33

44

55

66DD24

BAV99DW

DD24

BAV99DW

A0 1

A1 2

A2 3

GND 4

VCC8

WP7

SCL6

SDA5

U12

24C02

U12

24C02Q123904Q123904

R143 10RR143 10R

R139 10RR139 10R

G

D S

Q56

2N7002

Q56

2N7002

DD

54N

C-E

ZJZ1

V27

0RA

DD

54N

C-E

ZJZ1

V27

0RA

R15810KR15810K

C129

0.1u

C129

0.1u

R140 10RR140 10R

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCM_CE_N

PCM_A10

PCM_A11PCM_A9PCM_A8

PCM_IRQA_N

PCM_A13PCM_A14

PCM_A12PCM_A7PCM_A6PCM_A5PCM_A4PCM_A3PCM_A2PCM_A1PCM_A0PCM_D0PCM_D1PCM_D2

PCM_D7

PCM_D4PCM_D5PCM_D6

PCM_D3

PCM_CE_N

PCM_CD_N

PCM_OE_N

PCM_WE_NPCM_IRQA_N

PCM_REG_N

PCM_WAIT_NPCM_RESET

PCM_IORD_NPCM_IOWR_N

PCM_CD2_N

PCM_CD1_N

TS_MICLK

TS_MDI0TS_MDI1TS_MDI2TS_MDI3

TS_MDI4TS_MDI5TS_MDI6TS_MDI7

PCM_A[14:0]

TS_MDO3TS_MDO4TS_MDO5TS_MDO6TS_MDO7

TS_MOCLK

TS_MDO2

TS_MOVALTS_MOSTARTTS_MDO0TS_MDO1


PCM_WAIT_NPCM_RESET

PCM_REG_NPCM_OE_NPCM_WE_N

PCM_D[7:0]

PCM_CD2_NPCM_CD1_N

PCM_CD_N

TS_D4

TS_MDO0TS_MDO1TS_MDO2TS_MDO3TS_MDO4TS_MDO5TS_MDO6TS_MDO7

TS_MDO[7:0]

TS_D5TS_D6TS_D7

TS_D[7:0]TS_D0TS_D1TS_D2TS_D3

TS_MOCLKTS_MOSTARTTS_MOVAL

PCM_VS1

VCC-PCMCIA

VCC-PCMCIA

VCC-PCMCIA

VCC-PCMCIA

3.3VU3.3VU

3.3VU

3.3VU

+3.3VPCM

3.3VU 5VU VCC-PCMCIA

5VU

5VU

+3.3VPCM

TS_CLK 3

PCM_CD_N 3PCM_RESET 3PCM_WAIT_N 3PCM_REG_N 3PCM_OE_N 3PCM_WE_N 3PCM_IORD_N 3PCM_IOWR_N 3PCM_CE_N 3PCM_IRQA_N 3

PCM_A[14:0] 3

PCM_D[7:0] 3

TS_D[7:0] 3

TS_MOSTART0 3TS_MOVAL0 3

TSSTART5

TSCLK 5TSVALID 5

TS_MDI[7:0] 5

PCM_VS15

PCM_VS1

PCM_PWR_CTL1

PCM_PWR_CTL

LOW: ONHIGH: OFF

R717 NCR717 NC

R714

4.7K

R714

4.7KC4560.1uC4560.1u

+C458

100uF

+C458

100uF

D6SS14D6SS14

GND 1D3 2D4 3D5 4D6 5D7 6

CE1# 7A10 8OE# 9A11 10

A9 11A8 12

A13 13A14 14

WE# 15READY 16

VCC 17VPP1 18

MIVAL 19MICLK 20

A12 21A7 22A6 23A5 24A4 25A3 26A2 27A1 28A0 29D0 30D1 31D2 32

WP 33GND 34

GND35CD1#36MDO337MDO438MDO539MDO640MDO741CE2#42VS1#43IORD#44IOWR#45MISTRT46MDI047MDI148MDI249MDI350VCC51VPP252MDI453MDI554MDI655MDI756MOCLK57RESET58WAIT#59INPACK60REG#61MOVAL62MOSTART63MDO064MDO165MDO266CD2#67GND68 G

ND

69G

ND

70

CONN1PCMCIA_CONNCONN1PCMCIA_CONN

R71110KR71110K

C4602.2uC4602.2u

75

31

86

42RP43 100X4

75

31

86

42RP43 100X4

R657 4.7KR657 4.7K

R421NCR421NC

+C461

10uF

+C461

10uF

R3934.7KR3934.7K

75

31

86

42RP44 100X4

75

31

86

42RP44 100X4

R7124.7KR7124.7K

R3924.7KR3924.7K

R4201KR4201K

C852 0.1uFC852 0.1uF

1

32

Q57MMBT3904Q57MMBT3904

R7084.7KR7084.7K

S11G12S23G24

D1 8D1 7D2 6D2 5

U7CEM4953U7CEM4953

C209

nc

C209

nc

R166 100RR166 100R

D51N4001D51N4001

R165 100RR165 100R

12

43

5VCC

GND

U27

NC7SZ32

VCC

GND

U27

NC7SZ32

1

32

Q54MMBT3904Q54MMBT3904R710 4.7KR710 4.7K

R70910KR70910K

R3974.7KR3974.7K

R167 100RR167 100R

R658 1KR658 1K

C459100nFC459100nF

C853

0.1uF

C853

0.1uF

R3914.7KR3914.7K

R715 100R715 100

R7134.7KR7134.7K

C854

0.1uF

C854

0.1uF

R7184.7KR7184.7K

1

32

Q55MMBT3904Q55MMBT3904

D4

1N4001

D4

1N4001

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TV-Video

IF_TV

TV-Video

RF-AGC

IF_OUT_tuner

#IF_OUT_tuner

T_SDA

IF_T

V

T_R

F-A

GC

T_SCL

TIF_AGC

#IF_OUT_tuner

IF_OUT_tuner

T_SDA

TIF_AGC

IF_T

V

T_SCL

RF-

AG

CT_

RF-

AG

C

T_R

F-A

GC

CONTROL-AGC#

CO

NTR

OL-

AGC

#

T_RF-AGC

RF-AGC

5V-OUT

12VA5V_TUNER

5V_B15V_TUNER

5V_B2

5V_TUNER

5V-OUT

5V_TUNER

5V-OUT

5V-OUT

5V-OUT

5V_B

2

5V_B

1

5V_B

2

5V_B25V_TUNER

5V_B

1

5V_TUNER

ATV-Vin- 3

ATV-Vin+ 3

IF_AGC 5

SD

A3,

5

SC

L3,

5

SIFP 3

SIFM 3

CONTROL_AGC

T_SDA 5T_SCL 5

IF_OUT

#IF_OUT

T_SDAT_SCL

TUNER POWER

closed to tuner

closed to demod

To tuner RF AGC

From R2S10407 RF AGC

GPIO Control

R2S10401:PAL NTSCR2A10407:PAL SECAM

20080506 20080506

closed to tuner

2009-9-29

改为220R 2009-9-29

2009-9-29

2009-9-29

R504 47R504 47

L66

0

L66

0

R459 47R459 47

C46

410

uC

464

10u

R262

100K

R262

100K

R48

81.

2KR

488

1.2K

R452 1kR452 1kC78 47nC78 47n

C34

40.

1uf

C34

40.

1uf

R1774.7KR1774.7K

C82 47nC82 47n

1

32

Q443904Q443904

2ING

4OUT1G

ND

3

5OUT21 IN SAW

U29K3953D

SAW

U29K3953D

C34

50.

01U

FC

345

0.01

UF

R428100R428100

C16522nFC16522nF

R455

10K

R455

10K

321

4

IN GND O

UT

U18

LM7805IN GND O

UT

U18

LM7805

R42

430

KR

424

30K

C40

40.

22uf

C40

40.

22uf

C318 10nC318 10n

L40

FB/220_500MA/NC

L40

FB/220_500MA/NC

L47FB

L47FB

C267

0.1u

C267

0.1u

R4534.7KR4534.7K

C2810.1uC2810.1u

R456 100KR456 100K

C119 0.1uC119 0.1u

R49

533

kR

495

33k

R182NCR182NC

1

23Q29

3904

Q29

3904

C463

1u

C463

1u

C34

310

0nC

343

100n

L83 FB/220_500MAL83 FB/220_500MA

C30

11u

fC

301

1uf

R50

76.

8KR

507

6.8K

C13

80.

1uC

138

0.1u

R41

52.

7KR

415

2.7K

R49

12.

7KR

491

2.7K

C277 10nC277 10n

R178 1KR178 1K

AN

T P

OW

1

RF

AG

C2

AS

3

SC

L4

SD

A5

XTA

L O

UT

6

MB

7

AIF

OU

T8

IF A

GC

9

IF O

UT2

10

IF O

UT1

11

GN

D12

GN

D13

GN

D14

GN

D15

U20TDAG2-D02A-TUNER/NC

U20TDAG2-D02A-TUNER/NC

R503100KR503100K

R425 100R425 100

C313

10u

C313

10u

R50

215

0R

502

150

C19

90.

1uC

199

0.1u

VIF

11

VIF

22

PO

RT

3

VC

O F

/B4

DE

-EM

S5

AU

DIO

-FB

6

VO

UT

7

EQ

F/B

8

GN

D9

SIF

OU

T10

RE

AG

C11

VC

O/IF

12V

CO

FB

13

RF

AG

C14

RE

F IN

15

IF A

GC

16

SD

A17

SC

L18

VC

C19

AP

C F

IL20

AFT

OU

T21

AFC

FIL

22

SIF

IN23

GN

D24

U26R2S10407

U26R2S10407

R4540/NCR4540/NC

R147 33R/2WR147 33R/2W

R50675R50675

C34

60.

22uf

C34

60.

22uf

C448

1u/NC

C448

1u/NC

5V1

RFA

GC

2

AS

3

SC

L4

SD

A5

XTA

L O

UT

6

5V7

AIF

OU

T8

IF A

GC

9

IF O

UT2

10

IF O

UT1

11

GN

D12

GN

D13

GN

D14

GN

D15

GND16 GND17 GND18 GND19 GND20 GND21

U22

BLH-702

U22

BLH-702

C39

833

pfC

398

33pf

R434 47R434 47

C226

NC/330p

C226

NC/330p

R42

239

KR

422

39K

R45

739

0R

457

390

R40

010

KR

400

10K

R148 33R/2WR148 33R/2W

+

CA

910

0uF/

16V

+

CA

910

0uF/

16V

A1GND2 VCC 6

NC 5B3 S 4

U34

FSA1156

U34

FSA1156

C27

50.

01U

FC

275

0.01

UF

R1751KR1751K

C317 10nC317 10n

12

3 Y44MHzY44MHz

R436 220R436 220

C465

0.1u

C465

0.1u

R426 100R426 100

1

32

Q453904Q45

3904

C446

0.1u/NC

C446

0.1u/NC

C46

910

u/N

CC

469

10u/

NC

C266

0.1u

C266

0.1u

R49

715

0/N

CR

497

150/

NC

C118 0.1uC118 0.1u

1

32

Q463906Q463906

C41

40.

22uf

C41

40.

22uf

+CA72

47uF/16V

+CA72

47uF/16V

C230 10nC230 10n

+

CA7347uF/16V

+

CA7347uF/16V C177

10nFC17710nF

R49

639

kR

496

39k

C262

1NF

C262

1NF

C34

80.

1uC

348

0.1u

C28

410

uC

284

10u

R423

22K

R423

22K

D66 BA277D66 BA277ING2 OUT1 4G

ND

3

OUT2 5IN1 SAW

U23

D9650H

SAW

U23

D9650H

C258220nC258220n

C34

710

nC

347

10n

+

CA

210

0uF/

16V

+

CA

210

0uF/

16V

R505 47R505 47

R435 220R435 220

C285

NC/330p

C285

NC/330p

R482100KR482100K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TS_MDI2

IFind

#IFind

TS_MDI7

TS_MDI5TS_MDI6

TS_MDI4TS_MDI3

TS_MDI0TS_MDI1

AGC1

TS1_DO

SCL

TS1_STARTTS1_VALID

T_SCL

TS1_CK

T_SDA SDA

TS1_CKTS1_DOTS1_VALIDTS1_START

IF_OUT

#IF_OUT

AVDD

VDD_T

VDD_T

Vcore

VDD_T

VCC3.3_TVCC3.3_T

AVDDVcore

VCC1.8_TVCC1.8_T

VDD_T

PLLVDD

VDD_TPLLVDDVCC1.8_T

VCC3.3_T

VCC1.8_TVCC3.3_T

VCC3.3_T5VA

SYS-RESET 3

TSVALID 7TSSTART 7

TS_MDI[7:0] 7

TSCLK 7

SDA 3,6SCL 3,6

IF_OUT6

#IF_OUT6

T_SDA6T_SCL6

TS1_DO1 3TS1_CK1 3

TS1_VALID1 3TS1_START1 3

IF_AGC6

按图纸安装 2009-9-22

C169

0.1uF

C169

0.1uF

+ C117

10uF

+ C117

10uF

VIN3

GN

D1

VOUT 2Vout 4

U11 AP1117-18U11 AP1117-18

C443

0.1uF

C443

0.1uF

C128

0.1uF

C128

0.1uF

C187

0.1uF

C187

0.1uF

C441

0.1uF

C441

0.1uF

C670.1uFC670.1uF

R1884.7K R1884.7K

L35

330NH/NC

L35

330NH/NC

R223 33R223 33

C183

0.1uF

C183

0.1uF

R260

1K

R260

1K

R207

10K

R207

10K

+C8010uFC1206

+C8010uFC1206

L38

FB/220_500MA

L38

FB/220_500MA

C19222pF/NCC19222pF/NC

+ C52

10uFC1206

+ C52

10uFC1206

C167 33pFC167 33pF

C127

0.1uF

C127

0.1uF

75

31

86

42RP12 33X4

75

31

86

42RP12 33X4

R170 33R170 33

C191

0.1uF

C191

0.1uF

L31

FB/220_500MA

L31

FB/220_500MA

C920.1uFC920.1uF

L30

FB/220_500MA

L30

FB/220_500MA

R205 33R205 33

R214

2.2M

R214

2.2M

C164

0.1uF

C164

0.1uF

R201 33R201 33

C44

0.1uF

C44

0.1uF

R220 33R220 33

+ C193

10uF

+ C193

10uF7 5 3 1

8 6 4 2

RP1447X4

7 5 3 1

8 6 4 2

RP1447X4

C171 33pFC171 33pF

C184

0.1uF

C184

0.1uF

VIN3

GN

D1

VOUT 2Vout 4

U16 GM11733U16 GM11733

C168

0.1uF

C168

0.1uF

C175

0.1uF

C175

0.1uF

+C70

10uFC1206

+C70

10uFC1206

C178

56PF/NC

C178

56PF/NCR217 33R217 33

X1

20.48MHZ

X1

20.48MHZ

R2154.7K R2154.7K

R176 100R176 100

C174

0.1uF

C174

0.1uF

R181 33R181 33

+C5310uFC1206

+C5310uFC1206

R1800/NCR1800/NC

C16622pF/NCC16622pF/NC

C126

0.1uF

C126

0.1uF

C125

0.1uF

C125

0.1uF

C185

0.1uF

C185

0.1uF

+ C116

2.2uF

+ C116

2.2uF

VIN30

VIN31

AGC142AGC2/GPP241AVDD28AGND29AGND32VDD33RFLEV34

PLLVDD21PLL1TEST26PLLGND22

GPP343

CLK2/GPP035DATA2/GPP136

XTO

24

XTI

23

OSC

MO

DE

27

VSS

1VS

S3

VSS

8VS

S14

VSS

20VS

S25

VSS

38VS

S40

VSS

46VS

S55

VSS

60

RESET 9CLK1 4DATA1 5

IRQ 6

SLEEP 10STATUS 11

BKERR 62

MOSTRT 47MOVAL 48

MDO7 58MDO6 57MDO5 56MDO4 53MDO3 52MDO2 51MDO1 50MDO0 49MOCLK 61MICLK 63

SAD

D0

18SA

DD

117

SAD

D2

16SA

DD

315

SAD

D4

12

SMTE

ST44

CVD

D64

CVD

D59

CVD

D39

CVD

D37

CVD

D19

CVD

D7

VDD

54VD

D45

VDD

13VD

D2U14

CE6353

U14

CE6353

C131

0.1uF

C131

0.1uF

75

31

86

42RP13 33X4

75

31

86

42RP13 33X4

L32

FB/220_500MA

L32

FB/220_500MA

R204 8.2KR204 8.2K

R219 33R219 33

+ C115

10uF

+ C115

10uF

R203 33R203 33

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

WEZ

MCLK+MCLK-

CKE

CKE

MVREF-1

LDQS0

MCLK-DQM1

MCLK+CLKN0

MDATA[15:0]

DATA11DATA10DATA9DATA8

DATA15DATA14DATA13DATA12

DQS[1:0]

DQM[1:0]

MDATA[15:0]

MCKE

MADR[12:0]

CASZ

DQS0 MVREF-1

BA0BA0BA1

DATA0

DATA4

DATA7DATA6DATA5

MDATA4

MDATA0

MDATA7

MDATA2MDATA1

MDATA3

MDATA6MDATA5

MADR7

MADR1MADR1

MADR5MADR6

MADR3MADR4

MADR8

MADR2

MADR9

MADR[12:0]

WEZM0

DATA1

UDM0

CASZM0

MADR0

DATA3MADR11 DATA2MADR10

UDQS0

MDATA10

MDATA13

MDATA9

MDATA11

MDATA14MDATA15

MDATA12

MDATA8

CASZWEZ

MBA0

DQS1

RASZM0RASZ

MBA1

LDM0DQM0 RASZCLK0

BA1

MADR12

DMQC0VCC2.5V

VCC2.5V

DMQC0

DMQC0DQM[1:0] 3

MCLK+ 3MCLK- 3

CKE 3WEZ 3CASZ 3RASZ 3BA0 3BA1 3

DQS[1:0] 3

MADR[12:0] 3

MDATA[15:0] 3

Close to MStar ICClose to Mstar IC

Close to DDR-SDRAM

Close to MStar IC

DDR-SDRAM DATA[15:0]

2M X 16bit X 8BK

Close to DRAMClose to DDR-SDRAM

Close to MStar IC

DDR-SDRAM DATA[15:0] Power

390mA

CLOSED TO MEMORY

调试时：用22欧姆.调试时：用22欧姆.调试时：用22欧姆.

调试时：用22欧姆.

调试时：用56欧姆.调试时：用56欧姆.

调试时：RP10/RP34用56欧姆.

调试时：用22欧姆.

R72 56RR72 56R

R75 22RR75 22R

C42510uFC42510uF

R118 56RR118 56R

R74 22RR74 22RR102 22RR102 22R

A029A130A231A332A435A536A637A738A839A940A10/AP28A1141

DQ0 2DQ1 4DQ2 5DQ3 7DQ4 8DQ5 10DQ6 11DQ7 13

DQ8 54DQ9 56

DQ10 57DQ11 59DQ12 60DQ13 62DQ14 63DQ15 65

BA026BA127

CS24

RAS23 CAS22 WE21

LDM20UDM47

LDQS16UDQS51

CKE 44CLK 45CLK 46

MVDD 1MVDD 18MVDD 33VDDQ 3VDDQ 9VDDQ 15VDDQ 55VDDQ 61

VSS34VSS48VSS66VSSQ6VSSQ12

VSSQ58VSSQ64

VREF 49

VSSQ52

NC14NC17

NC 19NC 25

NC 43

NC 53NC 50

NC 42

U9HY5DU561622ETP-4 256Mb_TSOP66U9HY5DU561622ETP-4 256Mb_TSOP66

C436100nFC436100nF

R120 150R_1%R120 150R_1%

R1161KR1161K

L19FB/220_500MAL19FB/220_500MA

75

31

86

42

RP10 RP22X4

75

31

86

42

RP10 RP22X4

C438100nFC438100nF

C439100nFC439100nF

R396 56RR396 56R

75

31

86

42

RP17 RP22X4

75

31

86

42

RP17 RP22X4

C435100nFC435100nF

R395 56RR395 56R

75

31

86

42

RP34 RP22X4

75

31

86

42

RP34 RP22X4

R97 22RR97 22R

75

31

86

42

RP38 RP22X4

75

31

86

42

RP38 RP22X4

C42610uFC42610uF

R117 56RR117 56R

C434100nFC434100nF

C541nFC541nF

R394 22RR394 22R

C428100nFC428100nF

R1071KR1071K

R104 56RR104 56R

C433100NFC433100NF

C437100nFC437100nF

C440100nFC440100nF

R73 56RR73 56R

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ATV-Vin+ATV-Vin-

CVBS_OUT

KE

Y0

AV

DD

_DD

R

MD

ATA

1D

QM

0

DQ

S0

MD

ATA

0

FLA

SH

_WP

KE

Y1

AVDD_ADC

CIN_1+YIN_1+

VCOM1

CIN_2+YIN_2+

SPI-SDII

RXOC+

PCM_RESET

SPI-SCKI

MDATA12

AVDD_LPLL

AUCOM

MDATA15

DQS1

AUVRM

AUCOM

AUVRPAUVAG

Jupi

ter-

PW

M0

Jupi

ter-

PW

M1

AU

VR

PA

UV

AG

TS_M

OV

AL0

TS_M

OS

TAR

T0TS

_CLK

TS_D

0TS

_D1

TS_D

2TS

_D3

TS_D

4TS

_D5

TS_D

6TS

_D7

AV

DD

_MP

LL

MDDR_VREF

MDATA9

AV

DD

_OTG

VD

DC

AVDD_DDR

RXBCLKPRXBCLKN

VD

DP

HOTPLUG

RXB1P

MDATA11RXB1N

RXB0PRXB0N

AVDD_DVI

AV

DD

L_D

VI

WE

ZB

A0

BA

1

CA

SZ

RA

SZ

MD

ATA

5M

DA

TA6

MD

ATA

7

MD

ATA

4A

VD

D_D

DR

MD

ATA

2M

DA

TA3

VD

DC

AV

DD

_DD

R

AV

DD

_AU

JUP

ITE

R-X

TALI

JUP

ITE

R-X

TALO

MDATA14

DQM1

AU

VR

MTE

STP

IN

POWER_KEY


PCM_WAIT_N

PCM_REG_N

PCM_IRQA_N

PCM_OE_NPCM_WE_N

MADR0

M_A

DR

10M

_AD

R11

M_A

DR

7

M_A

DR

12

M_A

DR

8M

_AD

R9

MDATA8

M_A

DR

5

M_A

DR

0M

_AD

R1

M_A

DR

6

M_A

DR

2M

_AD

R3

M_A

DR

4

MADR12MADR11MADR10MADR9MADR8MADR7MADR6MADR5MADR4MADR3MADR2MADR1

AV

DD

_ME

MP

LL

OTG

_RE

XT

REFM

REFP

VCLP

DDCBSCLDDCBSDAHDMI-REXT

VCLPREFPREFM

AVDD_ADC

RGB0_BIN-

RGB0_RIN-

RGB0_GIN-

VD

DP

PC

M_D

7P

CM

_D6

MDATA10

PC

M_D

5P

CM

_D4

PC

M_D

3P

CM

_D2

PC

M_D

1P

CM

_D0

PC

M_A

14P

CM

_A13

PC

M_A

12P

CM

_A11

PC

M_A

10P

CM

_A9

PC

M_A

8

PC

M_A

7P

CM

_A6

PC

M_A

5P

CM

_A4

PC

M_A

3

VD

DC

PC

M_A

2P

CM

_A1

PC

M_A

0

RXB2NRXB2P

RXE3+RXE3-

RXE1-RXE1+

RXE0+

RXEC+RXEC-

RXE0-

RXE2+RXE2-

SIFMSIFP

VDDC

AVDD_SIF

AVDD_DDR

RXO2+RXO2-

RXO0-

RXO1-RXO1+

RXO0+

I2C

_SC

L

MC

LK+

CK

E

MC

LK-

MD

DR

_VR

EF

RXOC-

SPI-CSNI

UA

RT-

TXU

AR

T-R

X

Jupi

ter-

RS

T

PCM_CD_N

MDATA13

HD-VSW0

SPI-SDOI

US

B_D

MU

SB

_DP

AD

J-P

WM

I2C

_SD

A

WEZ

MCLK+MCLK-

CKE

DQS[1:0]

DQM[1:0]

MDATA[15:0]

MADR[12:0]

CASZ

BA0RASZ

BA1

RXO3+RXO3-

JUPITER-XTALO

JUPITER-XTALI

SDASCL

Jupiter-RST

UART-TXISP-TXDISP-RXD UART-RX

I2C_SCLI2C_SDA

TS_D[7:0]

SCLSDA

EPM_WP

PCM_A[14:0]

PCM_D[7:0]

PCM_CE_NHOTPLUG

DVDIR_EN

LED_R Jupiter-PWM1

Jupiter-PWM0

Jupiter-PWM1

ON_PANEL

RGB0_BIN+

RGB0-SOGRGB0_GIN+

RGB0_RIN+

RGB1_R+

RGB1_B+

RGB1_G+RGB1_SOG

SPI-SCK

SPI-CSN

SPI-SDISPI-SDO

DV

DIR

_EN

SY

S-R

ES

ET

HD-LinHD-Rin

AV1-LinAV1-Rin

AV2-RinAV2-Lin

VGA-LinVGA-Rin

SCLSDA

SPI-CS1NSPI-CS1NI

EPM_WPON_PBACKPWR-ON/OFF

SPI-SDISPI-SCK

SPI-SDOSPI-CS1N

SPI-SDISPI-SCK

SPI-SDOSPI-CSN

FLASH_WP

HD-VSW0

LED_GLED

IR_SYNC

LED

RXO0+

RXO2-RXO1+

RXO0-RXO1-

RXO2+

RXE1+RXE2+

RXE0+RXE1-

RXOC+

RXE2-

RXE0-RXO3+RXO3-

RXOC-

RXEC-RXE3+RXEC+

RXE3-

AVDD_DDRAVDD_DVI

3.3VU

3.3VU

5VU

AVDD_MPLLAVDD_OTG

AVDDL_DVIAVDD_MEMPLL

AVDD_ADC

AVDD_SIF

AVDD_AU

VDDC

VDDP

AVDD_LPLL

3.3VU

3.3VU

3.3VU

3.3VU

3.3VU

3.3VU

5VU

3.3VU

+3.3VD

+3.3VD

3.3VU

3.3VUVDDP

VDDC

VDDC

VDDP

VDDP

+3.3VD3.3VU

VCC-Panel

5VU

RXB0N8RXB0P8

RXB1N8RXB1P8

RXB2P8RXB2N8

RXBCLKN8RXBCLKP8

DDCBSDA8DDCBSCL8

HOTPLUG8

SV1-Cin9SV1-Yin9

ATV-Vin+6

SV2-Yin9SV2-Cin9

CVBS_OUT9

ATV-Vin-6

SIFP6SIFM6

AU

OU

TL1 11

AU

OU

TR1 11

AU

OU

TL0 11

AU

OU

TR0 11

MDATA[15:0] 4

MCLK+ 4MCLK- 4

CKE 4WEZ 4CASZ 4RASZ 4

DQM[1:0] 4

BA0 4BA1 4

DQS[1:0] 4

MADR[12:0] 4

SCL5,6SDA5,6

ISP-RXD 9ISP-TXD 9

RGB0_GIN-9

RGB0_BIN-9

RGB0_RIN-9

TS_D[7:0] 7

TS_C

LK

7

USB_DP 10USB_DM 10

PCM_A[14:0] 7

PCM_D[7:0] 7

PCM_IOWR_N 7

PCM_CE_N 7

PCM_RESET 7

PCM_WAIT_N 7PCM_IRQA_N 7

PCM_REG_N 7

PCM_OE_N 7PCM_WE_N 7

PCM_CD_N 7

PCM_IORD_N 7

TS_M

OS

TAR

T0 7

TS_M

OV

AL0 7

TS1_DO1 5

TS1_CK1 5

TS1_VALID1 5TS1_START1 5

HOTPLUG 8DVDIR_EN 9

DVD_ON/OFF 9

AD

J-P

WM 1

RGB0_BIN+9

RGB0-SOG9RGB0_GIN+9

RGB0_RIN+9

RGB1_R+9

RGB1_B+9

RGB1_G+9RGB1_SOG9

HD-VSW09

SY

S-R

ES

ET

5

SPDIFO 9

AV1-Vin+9AV3-Vin+9

HD-Rin9HD-Lin9

AV1-Rin9AV1-Lin9

AV2-Rin9AV2-Lin9

VGA-Rin9VGA-Lin9

USB_OCD_N10

ON_PANEL 1

ON_PBACK 1PWR-ON/OFF 1,11

RGB0_RIN- 3

RGB0_BIN- 3

RGB0_GIN- 3

SC1_FS9SC1_FB9

VGA_VSYNC19VGA_HSYNC19

PCM_IOWR_N

PCM_CE_N

PCM_WAIT_NPCM_IRQA_N

PCM_REG_N

PCM_OE_NPCM_WE_N

PCM_IORD_N

PCM_RESET

PC

M_P

WR

_CTL

MUTE_AMP11

PCM_VS15PCM_PWR_CTL1

CONTROL_AGC 9

HDMI-CEC

POWER_KEY 5IR_SYNC 5

KE

Y0

11K

EY

111

LED_G

LED_R

Close to ICwith width trace

Close to IC as close as possiblewith width trace

DDR-SDRAM Block

LVDS CONNECTOR

EEPROM

I2C addressat A0.

I2C addressat A4

RESET

DEBUG PORT

Mode Selection

CLOSED TO MSD109

SERIAL FLASH

CLOSED TO msd109

SERIAL FLASH

CLOSED TO msd109

FOR CEC

调试时：RP35/RP36/RP37都用22欧姆.

2009-9-29

OFF：3.25V

ON：0V 0.44V

1.76V

1.88V

红

绿

C36100nFC36100nF

R312 100R312 100

R2909R_1%R2909R_1%

12345

CON33

NC

CON33

NC

L22 10uHL22 10uH

R2214.7KR2214.7K

C417100nFC417100nF

R90 47RR90 47R

C7247nFC7247nF

R23933 R23933

R23

74.

7KR

237

4.7K

C3360.1uC3360.1u

R26 1KR26 1K

75

31

86

42RP50 100X4

75

31

86

42RP50 100X4

Q273904Q273904

R2224.7KR2224.7K

C419NC/100nFC419NC/100nF

R24

14.

7KR

241

4.7K

C421100nFC421100nF

C314

100p

C314

100p

75

31

86

42RP49 100X4

75

31

86

42RP49 100X4

R390 56RR390 56R

R47 1KR47 1K

R382 0RR382 0R

R24033 R24033

C30810uF/6.3VC30810uF/6.3V

R41

910

KR

419

10K

R81K_1%R81K_1%

R41

410

KR

414

10K

A01A12A23GND4 SDA 5SCL 6WP 7VCC 8

U43

24C512

U43

24C512

75

31

86

42RP16 33X4

75

31

86

42RP16 33X4

R41

310

KR

413

10K

C1760.1u

C1760.1u

R22433K R22433K

7531

8642

RP

4710

0X4 7531

8642

RP

4710

0X4

75

31

86

42RP35 RP56X4

75

31

86

42RP35 RP56X4

R33510KR33510K

R41

010

KR

410

10K

CE# 1SO 2

WP# 3VSS 4SI5 SCK6 HOLD#7 VDD8

U25NC/EON-b32-32MBit

U25NC/EON-b32-32MBit

C3010uFC3010uF

C420100nFC420100nF

R30RR30R

R155 33R155 33

R249 100RR249 100R

C1700.1u

C1700.1u

R212

2.2M

R212

2.2MC17220pC17220p

RX1P10AVSS_DVI11RX2N12RX2P13HOTPLUGA14REXT15DDCDA_DA16DDCDA_CK17HSYNC118VSYNC119VCLP20REFP21REFM22BIN1P23SOGIN124GIN1P25RIN1P26BIN0M27BIN0P28GIN0M29GIN0P30SOGIN031RIN0M32

AVDD_ADC234AVSS_ADC235HSYNC036VSYNC037

CVBS3P42CVBS2P43CVBS1P44VCOM145CVBS0P46VCOM047AVDD_ADC48CVBS_OUT49AVSS_CVBSO50AVDD_SIF51SIF_IN1P52SIF_IN1M53VDDC54

LINE_IN_0L56LINE_IN_0R57LINE_IN_1L58LINE_IN_1R59LINE_IN_2L60LINE_IN_2R61LINE_IN_3L62LINE_IN_3R63VIM064

AV

SS

_AU

65

AVD

D_A

USD

M69

AUVR

M66

AUVR

P67

AU

VA

G68

LIN

E_O

UT_

1L72

VDD

P76

GPIO15/CEC 134

I2C

_SD

A(D

DC

R_D

A2)

205

I2C

_SC

L(D

DC

R_C

K2)

206

SA

R0

120

SA

R1

121

SA

R2

122

SA

R3

123

PW

M0

124

PW

M1

125

PW

M2

126

PW

M3

127

HW

RES

ET12

8

SPI_CK 129SPI_DI 130SPI_DO 131SPI_CZ 132VDDP 133

AVDD_DDR 191

SDR_DQ15 180SDR_DQ14 181SDR_DQ13 182SDR_DQ12 183

DDR_DQS1 192

SDR_DQ11 185SDR_DQ10 186

SDR_DQM1 188SDR_DQ9 189SDR_DQ8 190

SDR

_BA0

229

SDR

_WE

_N23

0SD

R_R

AS_N

231

SDR

_CAS

_N23

2

SDR

_DQ

723

4SD

R_D

Q6

235

SDR

_DQ

523

6SD

R_D

Q4

237

SDR

_DQ

323

9SD

R_D

Q2

240

GN

DM

241

SDR

_DQ

M0

242

SDR

_DQ

124

3SD

R_D

Q0

244

AV

DD

L_D

VI

247

XTA

LI25

4

GN

D25

6

RXCP5RX0N6

RX1N9

RX0P7AVDD_DVI8

RXCN4

RIN0P33

AVD

D_D

DR

245

GN

DC

90VD

DC

91

DD

R_D

QS0

246

AVD

D_D

DR

238

XTA

LO25

3

LIN

E_O

UT_

2L70

LIN

E_O

UT_

2R71

GN

DP

77VD

DC

78

UAR

T_TX

(DD

CA_

DAT

)11

8U

ART_

RX(

DD

CA_

CLK

)11

9

B2_RXE3+ 143B3_RXE3- 144B4_RXEC+ 145B5_RXEC- 146B6_RXE2+ 147B7_RXE2- 148G0_RXE1+ 149G1_RXE1- 150G2_RXE0+ 151G3_RXE0- 152VDDP 153

GNDC 166

G6_RXO3+ 154G7_RXO3- 155R0_RXOC+ 156R1_RXOC- 157R2_RXO2+ 158R3_RXO2- 159R4_RXO1+ 160R5_RXO1- 161R6_RXO0+ 162R7_RXO0- 163AVDD_LPLL 164AVSS_LPLL 165

VDDC 167LCK/GPIO100 168LDE/GPIO99 169LHSYNC/GPIO98 170LVSYNC/GPIO97 171

PCM

_D7/

CI_

D7

92PC

M_D

6/C

I_D

693

PCM

_D5/

CI_

D5

94PC

M_D

4/C

I_D

495

PCM

_D3/

CI_

D3

96PC

M_D

2/C

I_D

297

PCM

_D1/

CI_

D1

98PC

M_D

0/C

I_D

099

PC

M_A

14/C

I_A

1410

0P

CM

_A13

/CI_

A13

101

PC

M_A

12/C

I_A

1210

2P

CM

_A11

/CI_

A11

103

PC

M_A

10/C

I_A

1010

4P

CM

_A9/

CI_

A9

105

PC

M_A

8/C

I_A

810

6VD

DP

107

PC

M_A

7/C

I_A

710

8P

CM

_A6/

CI_

A6

109

PC

M_A

5/C

I_A

511

0P

CM

_A4/

CI_

A4

111

PC

M_A

3/C

I_A

311

2P

CM

_A2/

CI_

A2

113

PC

M_A

1/C

I_A

111

4P

CM

_A0/

CI_

A0

115

GP

IO3

116

GP

IO4

117

PCM_IORD_N/CI_RD 135PCM_IOWR_N/CI_WR 136PCM_OE_N 137PCM_WE_N 138PCM_REG_N/CI_CLK 139PCM_CE_N/CI_CS 140PCM_IRQA_N/CI_INT 141PCM_WAIT_N/CI_WACK 142

CI_RESET 172CI_CD 173TS1_D0/FDSP_IMS 174TS1_VLD/FDSP_ICLK 175TS1_SYNC/FDSP_IDI 176TS1_CLK/FDSP_IDO 177IRIN2 178INT2 179

AVDD_DDR 184

GNDM 187I2S

_IN

_WS

/GP

IO44

193

I2S

_IN

_BC

K/G

PIO

4519

4I2

S_I

N_S

D19

5S

PD

IF_I

N19

6I2

S_O

UT_

MC

K19

7I2

S_O

UT_

WS

198

VDD

P19

9G

ND

C20

0VD

DC

201

I2S

_OU

T_B

CK

202

I2S

_OU

T_S

D20

3S

PD

IF_O

UT

204

I2S

_OU

T_M

UTE

207

GP

IO14

/UA

RT_

TX1/

CE

C20

8M

VR

EF

209

DD

R_C

KO_N

210

DD

R_C

KO21

1SD

R_C

KE21

2A

VD

D_M

EM

PLL

213

SDR

_AD

021

4SD

R_A

D1

215

SDR

_AD

221

6SD

R_A

D3

217

SDR

_AD

421

8SD

R_A

D5

219

SDR

_AD

622

0AV

DD

_DD

R22

1SD

R_A

D7

222

SDR

_AD

822

3SD

R_A

D9

224

SDR

_AD

1022

5SD

R_A

D11

226

SDR

_AD

1222

7SD

R_B

A122

8

OTG

_RE

XT

248

AVD

D_O

TG24

9U

SB_D

M25

0U

SB_D

P25

1A

VS

S_O

TG25

2

AVD

D_M

PLL

255

GPIO0/CEC1GPIO1/TX12GPIO23

C1(CVBS7P)38Y1(CVBS5P)39C0(CVBS6P)40Y0(CVBS4P)41

VDD

C23

3

LIN

E_O

UT_

1R(D

AC

O_S

)73

LIN

E_O

UT_

0L(D

AC

O_L

)74

LIN

E_O

UT_

0R(D

AC

O_R

)75

GNDC55TS

_D0/

BT6

56_D

0/FD

SP

_IM

S79

TS_D

1/B

T656

_D1/

DS

P_I

CLK

80TS

_D2/

BT6

56_D

2/FD

SP

_ID

I81

TS_D

3/B

T656

_D3/

FDS

P_I

DO

82TS

_D4/

BT6

56_D

483

TS_D

5/B

T656

_D5

84TS

_D6/

BT6

56_D

685

TS_D

7/B

T656

_D7

86TS

_VLD

87TS

_SY

NC

88TS

_CLK

/BT6

56_C

LK89

GN

D25

7

UART1

U2MSD106CL

UART1

U2MSD106CLR92 47RR92 47R

C331 10uF/6.3VC331 10uF/6.3V

1

32

Q413906Q413906

R360 NCR360 NC

75

31

86

42RP37 RP56X4

75

31

86

42RP37 RP56X4

R35

310

KR

353

10K

C3160.1uFC3160.1uF

R475

10K

R475

10K

C56 47nC56 47n

7531

8642

RP

4610

0X4 7531

8642

RP

4610

0X4

C42210uFC42210uF

R473 4.7KR473 4.7K

R484

10K

R484

10K

R160 33R160 33

R126 33RR126 33R

C241uFC241uF

C8847nFC8847nF

R358 100R358 100

3

1 2

DD30BAV99DD30BAV99

CE# 1SO 2

WP# 3VSS 4SI5 SCK6 HOLD#7 VDD8

U24EON-b32-32MBit

U24EON-b32-32MBit

R40

410

KR

404

10K

1234

CON31

CON4-2.0Debug Port

CON31

CON4-2.0Debug Port

R12347RR12347R

R41

210

KR

412

10K

75

31

86

42RP36 RP56X4

75

31

86

42RP36 RP56X4

C752.2uC752.2u

C24

82.

2uC

248

2.2u

C418100nFC418100nF

7531

8642

RP

4110

0X4 7531

8642

RP

4110

0X4

R39

910

KR

399

10K

R367 1KR367 1K

A01A12A23GND4 SDA 5SCL 6WP 7VCC 8

U21

24C04

U21

24C04

R38

910

KR

389

10K

L73FB/220_100MAL73FB/220_100MA

7531

8642

RP

4210

0X4 7531

8642

RP

4210

0X4

R36

96K

8R

369

6K8

C231 NC-22pC231 NC-22p

R32

11K

R32

11K

R259 10KR259 10K

R91K_1%R91K_1%

R124 33RR124 33R

C416100nFC416100nF

R347

4.7K

R347

4.7K

R41

810

KR

418

10K

R40

310

0R

403

100

C391nFC391nF

R387 0RR387 0R

R41

110

KR

411

10K

R40

210

0R

402

100

R150 33R150 33

C306

0.1uF

C306

0.1uF

R41

610

KR

416

10K

R25247KR25247K

C58 47nC58 47n

C17320pC17320p R316 100R316 100

R24

84.

7KR

248

4.7K

12

3

Y512MHZY512MHZ

R476 100R476 100

C57 47nC57 47n

R10 390R_1%R10 390R_1%

R218NC

R218NC

C315

100p

C315

100p

C3071nC3071n

R359 100R359 100

C342ncC342nc

7531

8642

RP

4810

0X4 7531

8642

RP

4810

0X4

R149 10KR149 10K

R91 47RR91 47R

R40

110

0R

401

100

113355779911111313151517171919

2 24 46 68 8

10 1012 1214 1416 1618 1820 20

2121 22 222323 24 242525 26 262727 28 282929 30 3031313333 32 32

34 34

CON11

2x17x2mm

CON11

2x17x2mm

R25310KR25310K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC-PL

PB-ADJUST

PB-ON/OFFPB-ADJUST

PB-ON/OFF

12VU

5VA

12VA

12VU

5VU VCC-Panel

3.3VU

5VU

5VU

12VU

VCC-PL

12VU

5VA5VDC-DC

12VU 5VDC-DC

12VUE

AVDD_OTG

VDDC

AVDDL_DVI

VDDCVCC1.2V

AVDD_MPLL

VDDP

VCC1.2V5VU

5VA

VCC2.5V

AVDD_ADC

AVDD_DVI

3.3VU

AVDD_SIF

AVDD_AU

3.3VU

AVDD_MEMPLL

AVDD_LPLL

AVDD_DDR

VCC2.5V

AVDD_DDR

AVDD_LPLLAVDD_MEMPLL

AVDD_OTGAVDD_MPLL

AVDD_SIFAVDD_AU

AVDD_ADCAVDD_DVI

VDDPVDDP

5VU

5VUAVDD_MPLL

3.3VU

3.3VU

3.3VU

5VU 3.3VU

12VA

5VU

5VU

5VA5VA

5VU

3.3VU

3.3VU

ON_PANEL3

ADJ-PWM3

ON_PBACK3

PW-ON/OFF-INV1

PW-ON/OFF-INV 12

PWR-ON/OFF3,11

PW-ON/OFF-INV 1

DVD Power Interface

CA75 & C250 close to CON6

C263 & C251 close to CON6

PANEL POWER

Note: Left C255 NC if want to output PWM puls

L:ONH:OFF

4A

5V DC-DC

Note: C8,C9,C11 close to CON15 for EMI

H:ONL:OFF

Low ESR

外接电源时去掉L33,U47,D12,U13

+1.2V FOR MST CORE

Using power plane

H:ONL:OFF

L:ONH:OFF

2009-9-29

2009-9-29

R21 100RR21 100R

R256 470R256 470

C376100nFC376100nF

L14FB/NCL14FB/NC

L17FB/220_500MAL17FB/220_500MA

C197

0.1u

C197

0.1u

C402100nFC402100nF

R16 1KR16 1K

C90.1u/NCC90.1u/NC

+CA39

100uF/16V

+CA39

100uF/16V

R3710K/NC

R3710K/NC

R7 NCR7 NC

L2FB/220_500MAL2FB/220_500MA

C2150.1uC2150.1u

123456

CON2

CON6_2.0mm

CON2

CON6_2.0mm

Q263904Q263904

+CA47

100uF/16V

+CA47

100uF/16V

L74FB/220_500MAL74FB/220_500MA

1 H20TPADH20

TPAD

R17 4.7KR17 4.7K

L5FB/220_500MAL5FB/220_500MA

C103.9n/NCC103.9n/NC

R4410KR4410K

C381

100nF

C381

100nF

L3FB/220_1000MAL3FB/220_1000MA

+C455100uF/16V+C455100uF/16V

+CA15

470uF/16V

+CA15

470uF/16V

+

CA

8

470u

F/16

V

+

CA

8

470u

F/16

V

R33

94.

7KR

339

4.7K

+CA75

10uF/16V/NC

+CA75

10uF/16V/NC

R39

10K/NC

R39

10K/NC

R386 0RR386 0R

+C384

10uF

+C384

10uF

C4302.2u/NCC4302.2u/NC

C3892.2uC3892.2u

F2F2

+ C388

10uF

+ C388

10uF

C375100nFC375100nF

C261

10uF

/6.3

V

C261

10uF

/6.3

V

C373100nFC373100nF

R146.2K_1%R146.2K_1%

D12SK34D12SK34

C10

80.

1uC

108

0.1u

+ C37910uF

+ C37910uF

1

H16TPADH16TPAD

R251 100KR251 100K

R34818KR34818K C

106

0.1u

C10

60.

1u

R257

10K/NC

R257

10K/NC

12

3

54

L3315uH/3A

L3315uH/3A

L4FB/220_500MAL4FB/220_500MA

1

23

Q73904Q73904

+ C37010uF

+ C37010uF

321

4

ADJ

OUT IN

U30

AMS1084-3.3

ADJ

OUT IN

U30

AMS1084-3.3

C372100nFC372100nF

C413

2.2U

C413

2.2U

C181

0.1u

C181

0.1u

L15FB/NCL15FB/NC

C86

10n/NC

C86

10n/NC

R35618KR35618K

1

H14TPADH14TPAD

1 H18TPADH18

TPAD

R2010KR2010K

C130.1uC130.1u

C387100nFC387100nF

R31

94.

7KR

319

4.7K

C410100nFC410100nF

C690.1uC690.1u

C1110.1uC1110.1u

C19

80.

1uC

198

0.1u

L6FB/220_500MAL6FB/220_500MA

C26310uF/6.3V/NC

C26310uF/6.3V/NC

1 H22TPADH22

TPAD

C399100nFC399100nF

D3SS14D3SS14

C390100nFC390100nF

C20

00.

1uC

200

0.1u

+C383

10uF

+C383

10uF

R27

1K

R27

1K

+C45410uF +C45410uF

+

CA

647

0uF/

16V

+

CA

647

0uF/

16V

C32

73.

9n/N

CC

327

3.9n

/NC

R25 NCR25 NC

C4292.2uC4292.2u

C385100nFC385100nF

R24410K_1%

R24410K_1%

C19

60.

1uC

196

0.1u

1

H15

TPAD

H15

TPAD

+ C39610uF

+ C39610uF

C24

910

uF/6

.3V

C24

910

uF/6

.3V

L18FB/220_500MAL18FB/220_500MA

L7FB/220_500MAL7FB/220_500MA

R32

94.

7KR

329

4.7K

R1910KR1910K

R1510KR1510K

L9FB/220_500MAL9FB/220_500MA

R23100K/NCR23100K/NC

Q113904Q113904

C415100nFC415100nF

R255 510R255 510

C2552.2uC2552.2u

R2210KR2210K

12

3

54

L815uH/1A

L815uH/1A

Q93904Q93904

+ C40510uF

+ C40510uF

C4312.2u/NCC4312.2u/NC

R33610KR33610K

Q313904Q313904

+ C39110uF

+ C39110uF

+ C37710uF

+ C37710uF

1

23

Q63904

Q63904

Q423904Q423904

C1100.1uC1100.1u

C10

30.

1uC

103

0.1u

S11G12S23G24

D1 8D1 7D2 6D2 5

U13IRF7314U13IRF7314

L16FB/1AL16FB/1A

321

4

ADJ

OUT IN

U37

AMS1117-3.3/NC

ADJ

OUT IN

U37

AMS1117-3.3/NC

1 H17TPADH17TPAD

R3494.7KR3494.7K

C412100nFC412100nF

C403100nFC403100nF

1 H19TPADH19

TPAD

C374100nFC374100nF

R33

44.

7KR

334

4.7K

C980.1UC980.1U

R3404.7KR3404.7K

1

23

CON5CON5

R24 1KR24 1K

L34FB/220_500MAL34FB/220_500MA

L10FB/220_500MAL10FB/220_500MA

1 12 23 34 45 56 67 78 89 9

10 1011 1112 1213 13

CON21

NC-1x13x2.54mm

CON21

NC-1x13x2.54mm

1

H46TPADH46

TPAD

C411100nFC411100nF

C990.1UC990.1U

R182K_1%R182K_1%

C10

90.

1uC

109

0.1u

L23 FB/220_3AL23 FB/220_3A

+ CA

3

470u

F/16

V + CA

3

470u

F/16

V

R398NC

R398NC

C951nC951n

C408100nFC408100nF

C18

20.

1uC

182

0.1u

C251

0.1u/NC

C251

0.1u/NC

EN7

FB 5

VCC2 OUT 3

BST 1

GND4

SS8

COMP6

U47EC9483U47EC9483

C310nC310n

1H21

TPAD

H21

TPAD

C394100nFC394100nF

C371100nFC371100nF

C409100nFC409100nF

C401100nFC401100nF

C393100nFC393100nF

123456

CON6

CON6_2.0mm/NC

CON6

CON6_2.0mm/NC

R38

44.

7KR

384

4.7K

R320

1K

R320

1K

C407100nFC407100nF

EN7

FB 5

VCC2 OUT 3

BST 1

GND4

SS8

COMP6

U15EC9410U15EC9410

R245 220_1%R245 220_1%

321

4

ADJ

OUT IN

U28

AMS1117-adj

ADJ

OUT IN

U28

AMS1117-adj

C380100nFC380100nF

C3340.1uC3340.1u

C395100nFC395100nF

S11G12S23G24

D1 8D1 7D2 6D2 5

U5IRF7314U5IRF7314

C250

0.1u/NC

C250

0.1u/NC

C931nC931n

C386100nFC386100nF

C27

20.

1u/N

CC

272

0.1u

/NC

C4060.1uC4060.1u

L20 FB/220_1000MAL20 FB/220_1000MA

+ C3781u

+ C3781u

R338 100RR338 100R

C400100nFC400100nF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

E_KEY1

IR_SYNC

KEY0

LED_G

P_KEY

IR_in

KEY1

LED_R

E_KEY0E_KEY1

POWER_KEY

P_KEY

LED_GLED_R

E_KEY0

IR_in

5VU

3.3VU

IR_in

KEY1POWER_KEY

IR_SYNC

LED_GLED_R

KEY0

KEY PAD

close to IC side

C3410.1uFC3410.1uF

C21

010

PFC

210

10PF

R407 680RR407 680RR317 470RR317 470R

C21

20.

1uF

C21

20.

1uF

123456789

CON37

CON9-2.0

CON37

CON9-2.0

R417 10RR417 10R

1 H36TPADH36

TPAD

R25

410

KR

254

10K

R323 470RR323 470R

R429 1KR429 1K

1

H27TPADH27TPAD

C21

30.

1uF

C21

30.

1uF

R380 22KR380 22K

C21

110

0PF

C21

110

0PF

1 H32TPADH32

TPAD

R408 1.2K/NCR408 1.2K/NC

1 H30TPADH30

TPAD

R427 1KR427 1K

1 H26TPADH26

TPAD

R406 680RR406 680R

1

H33TPADH33TPAD

R25

82K

R25

82K

1

H34TPADH34

TPAD

R405 1.2K/NCR405 1.2K/NC1

H28TPADH28TPAD

C27

00.

1uF

C27

00.

1uF

1

H35TPADH35

TPAD

1 H25TPADH25

TPAD

1 H29TPADH29

TPAD12345

CN31

CON5_2.0

CN31

CON5_2.0

C3490.1uFC3490.1uF

R24

32K

R24

32K

1

H31TPADH31TPAD

R379 4.7KR379 4.7K

Basic Operations & Circuit Description Main Electric Components (1). MODULE: There are 1 pc. panel and 1 pcs. PCB including T-CONTROL board, (2).SIGNAL PROCESS There are 3 pcs. PCBs including 1 pc. Main digital board, 1 pc. Keypad board, 1 pc. Remote Control Receiver board (3).POWER There are 1 pc. PCB for power.

13／113

PCB function 1. Power: (1). Input voltage: AC 100V~240V, 50~60Hz. (2). To provide power for PCBs. a). +5Vsb for standby, b). +5VCC for signal power, c). +12V for AMPLIFIER power. d). Converter the low DC voltage +12V to high AC voltage to drive the backlight. 2. Main (Video InterFace) board: (1).Convert TV RF signal to video and audio signal to Main board. (2).Decoder the video signal (TV,CVBS,S-VIDEO) from analog to digital signal. (3).Converter the Video signals( TV,CVBS,S-VIDEO ) and graphics signal (VGA,YPbPr) from internace to progressive, (4).Converter the Digital to fit the panel display mode and output the LVDS signal to Panel. 3. KEY board To get the main button control on LCD_TV as SOURCE,MENU, CHANEL +,CHANEL -, VOL +,VOL-, STANDBY functions. 4. Remote Control board Receive the remote signal and active for the control. 5. T-CONTROL board Converter the LVDS signal to the digital signal for fitting the PANEL.

14／113

PCB failure analysis 1. CONTROL: a. Abnormal noise on screen. b. No picture. 2. MAIN (VIDEO): a. Lacking color, Bad color scale. b. No voice. c. No picture but with signals output, OSD and back light. d. Abnormal noise on screen. 3. POWER: No picture, no power output.

Basic operation of LCD-TV 1. After turning on power switch, power board sends 5Vst-by Volt to Micro Processor IC waiting for ON signals from Key Switch or Remote Receiver. 2. When the ON signal from Key Switch or Remote Receiver is detected, Micro Processor will send ON Control signals to Power. Then Power sends (5Vsc, 12Vsc, ) to PCBs working. This time VIF will send signals to display back light, OSD on the panel and start to search available signal sources. If the audio signalsinput, them will be amplified by Audio AMP and transmitted to Speakers. 3. If some abnormal signals are detected (for example: over volts, over current, over temperature and under volts), the system will be shut down by Power off.

15／113

LCD basic display theory. When an electrical field is applied to the LC planes, the LC molecules re-align themselves so that they are parallel to the electrical field. This electrical process is known as twisted nematic field effect or TNFE. In this alignment, polarized light is not twisted as it passes through the LC material (see Diagram 3A and 3B). If the front polarizer is oriented perpendicular to the rear polarizer, light will pass through the energized display but will be blocked by the rear polarizer. An LCD in this form is acting as a light shutter. Displays with variable characters are created by selectively etching away the conductive surface that was originally deposited on the glass. Etched areas become the display’s background; unetched areas become the display’s characters.

Diagram 3A. The “off” state of a TN LCD-the LC molecules form a twist and therefore cause polarized light to twist as it passes through.

Diagram 3B. The “on” state-the electrical field re-aligns the LC molecules so they do not twist the polarized light.

16／113

MSD106CL DVB LCD/PDP DTV Processor

Preliminary Product Brief Version 0.1

- 1 - 10/1/2007 Copyright © 2007 MStar Semiconductor, Inc. All rights reserved.

Attention Please: Under the technology license agreement between MStar and Dolby/SRS/BBE, MStar is obliged not to provide samples that incorporate Dolby/SRS/BBE technology to any third party who is not a qualified licensee of Dolby/SRS/BBE.

FEATURES n Twin-turbo 8051 Micro-controller Twin-turbo 8051 MCU Interrupt controller Supports ISP One full duplex UART

n Transport Stream De-multiplexer One external TS input and one internal TS

data path Supports both parallel and serial TS interface,

with or without sync signal Maximum TS data rate is 104 Mbps for serial

or 13 MB/sec for parallel 32 general purpose PID filters and section

filters for each transport stream de-multiplexer One video PES and one audio PES channel Supports DVB subtitle and digital teletext Optionally supports MHEG5 Note 1

n MPEG-2 A/V Decoder ISO/IEC 13818-2 MPEG-2 video MP@ML Automatic frame rate conversion Supports resolution in SDTV MPEG-1, MPEG-2 (Layer I/II) audio decoder Optionally supports Dolby1 Digital (AC-3) audio

decoding Note 2 n MPEG-4 Decoder Supports ISO/IEC 14496-2 MPEG-4 ASP video

decoding Supports resolution up to D1

n NTSC/PAL/SECAM Video Decoder Supports NTSC-M, NTSC-J, NTSC-4.43, PAL

(B,D,G,H,M,N,I,Nc), and SECAM Automatic TV standard detection Motion adaptive 3-D comb filter for NTSC/PAL 8 configurable CVBS & Y/C S-video inputs

1 Dolby is a Trademark of Dolby Laboratories.

Supports Teletext level-1.5, Closed Caption (analog CC 608/analog CC 708/digital CC 608/digital CC 708), V-chip and SCTE

Macrovision detection CVBS video output

n Multi-Standard TV Sound Processor Supports BTSC/A2/EIA-J demodulation in NTSC

and A2/NICAM/FM/AM demodulation in PAL Supports MTS Mode MONO/STEREO/SAP in

BTSC/EIA-J and MONO/STEREO/DUAL in A2/NICAM

L/Rx4 and SIF audio input L/R speaker and 2 additional L/R audio line-out Built-in audio output DAC’s Audio processing for loudspeaker channel,

including volume, balance, mute, tone, EQ, virtual stereo/surround, and treble/bass

Optional advanced surround available (Dolby, SRS2, BBE3… etc) Note 3

n Digital Audio Interface HDMI audio channel processing capability Programmable delay for audio/video

synchronization n Analog RGB Compliant Input Ports Two analog ports support up to 1080P Supports PC RGB input up to SXGA@75Hz Supports HDTV RGB/YPbPr/YCbCr Supports Composite Sync and SOG

(Sync-on-Green) separator Automatic color calibration

n High-Performance Scaling Engine Fully Programmable shrink/zoom capabilities Nonlinear video scaling supports various

modes including Panorama n DVI/HDCP/HDMI Compliant Input Port Supports up to 225MHz @ 1080P 60Hz with

12-bit deep-color resolution Single link on-chip DVI 1.0 compliant receiver

2 Trademark of SRS Labs, Inc. 3 Registered trademark of BBE Sound, Inc.




High-bandwidth Digital Content Protection (HDCP) 1.1 compliant receiver

High Definition Multimedia Interface (HDMI) 1.3 compliant receiver with CEC (Consumer Electronics Control) support

Long-cable tolerant robust receiving n Auto-Configuration/Auto-Detection Auto input signal format and mode detection Auto-tuning function including phasing,

positioning, offset, gain, and jitter detection Sync Detection for H/V Sync

n Video Processing & Conversion 3-D motion adaptive video de-interlacers with

edge-oriented adaptive algorithm for smooth low-angle edges

Automatic 3:2 pull-down & 2:2 pull-down detection and recovery

MStar 3rd Generation Advanced Color Engine (MStarACE-3) automatic picture enhancement gives: Brilliant and fresh color Intensified contrast and details Vivid skin tone Sharp edge Enhanced depth of field perception Accurate and independent color control

sRGB compliance allows end-user to experience the same colors as viewed on CRTs and other displays

3-channel gamma curve adjustment Programmable 10-bit RGB gamma CLUT 3-D video noise reduction Frame rate conversion

n Output Interface Supports up to 8-bit dual LVDS

UXGA/WSXGA+ panel interface Supports 2 data output formats: Thine & TI

data mappings Compatible with TIA/EIA With 6/8 bits options Spread spectrum output frequency for EMI

suppression n CVBS Video Output Supports CVBS/S-video bypass output Built-in video encoder for encoding digital

video into CVBS output n 2D Graphics Engine Point draw, line draw, rectangle draw/fill and

text draw BitBlt and stretch BitBlt Raster Operation (ROP)

n Miscellaneous DRAM controller to support up to 16-bit DDR

interface Supports Common Interface for conditional

access SPI bus for external flash USB 2.0 host controller with the flexibility for

connecting external storage devices 256-LQFP package Operating at 1.2V (core), 2.5V (DDR), and

3.3V (I/O and analog) Note: 1. The optional MHEG5 function is available with

MSD106CHL. 2. The optional Dolby Digital function is available with

all MSD106CL models except those with suffixes –Z1. 3. Please see Ordering Guide for details on advanced

surround.




GENERAL DESCRIPTION The MSD106CL is a highly integrated controller IC for LCD/PDP DTV applications with resolutions up to UXGA/WSXGA+. It is configured with an integrated triple-ADC/PLL, a multi-standard TV video and audio decoder, a motion adaptive video de-interlacer, a scaling engine, the MStarACE-3 color engine, an advanced 2D graphics engine, a transport processor, a standard-definition (SD) MPEG video decoder, a 24-bit DSP for MPEG audio decoding, a DVI/HDCP/HDMI receiver, and a peripheral control unit providing a variety of HDTV control functions. The MSD106CL comprises an MPEG-2 transport processor with advanced section filtering capability, an MPEG-2 (MP@ML profile) video decoder, an MPEG layer I and II digital audio decoder with analog audio outputs that are designed to support DVB SDTV programs while handling conditional access. Furthermore, it is also possible to decode MPEG-4, JPEG, MP3 formats from external sources such as USB interfaces. For analog TV, the MSD106CL includes NTSC/PAL/SECAM multi-standard video decoder comprising a 3-D motion adaptive comb filter and time-based correction, and a NICAM/A2 audio decoder to support worldwide television standards. The MSD106CL is also configured with a VBI processor to decode digital information such as Close Caption/V-chip/teletext/WSS/CGMS-A/VPS. In addition, the MStar advanced LCD TV processor enhances video quality, motion adaptive de-interlacer, picture quality adjustment units, and MStarACE-3 color engine. By integrating peripherals including USB 2.0 host controller, UART, IR, SPI, I2C, and PWM, the MSD106CL fulfills all requirements in advanced DTV sets. To further reduce system costs, the MSD106CL also integrates intelligent power management control capability for green-mode requirements and spread-spectrum support for EMI management.




PIN DIAGRAM (MSD106CL)

Pin 1

13

14

17

18

21

23

25

27

28

30

32

34

36

39

41

43

15

16

19

20

22

24

26

29

31

33

35

37

38

40

42

44

45

46

47

48

50

51

52

49

GPIO1/UART_TX1GPIO2RXCKNRXCKPRX0NRX0P

AVDD_33

GND

RX2P

REXT

DDCD_CK

VSYNC1

REFP

BIN1P

RX1NRX1P

RX2N

GPIO125

DDCD_DA

HSYNC1

VCLAMP

REFM

SOGIN1GIN1PRIN1PBINM

BIN0PGINM

GIN0PSOGIN0

RINMRIN0P

AVDD_33GND

CVBS7CVBS5CVBS6CVBS4CVBS3CVBS2CVBS1

VCOM1CVBS0

VCOM0AVDD_33CVBSOUT

GNDAVDD_SIF

1

2

3

4

5

7

9

11

6

8

10

12

53

54

55

56

57

59

61

63

58

60

62

64

VDDCGNDAUL0AUR0AUL1AUR1AUL2AUR2AUL3AUR3

AUCOM

77 78 81 82 85 87 89 91 92 94 96 98 100

103

105

107

79 80 83 84 86 88 90 93 95 97 99 101

102

104

106

108

109

110

111

112

114

115

116

113

AVD

D_A

UAU

OU

TL2

AUO

UTR

2AU

OU

TL1

GN

DVD

DC

AUVR

P

TS0D

ATA[

1]

TS0D

ATA[

3]TS

0DAT

A[4]

AUO

UTR

1AU

OU

TL0

AUO

UTR

0VD

DP

TS0D

ATA[

0]

TS0D

ATA[

2]

TS0D

ATA[

5]TS

0DAT

A[6]

TS0D

ATA[

7]TS

0VAL

IDTS

0SYN

CTS

0CLK

PCM

DAT

A[3]

/CI_

DAT

A[3]

PCM

DAT

A[0]

/CI_

DAT

A[0]

PCM

ADR[

14]/

CI_A

[14]

PCM

ADR[

13]/

CI_A

[13]

PCM

ADR[

12]/

CI_A

[12]

PCM

ADR[

11]/

CI_A

[11]

PCM

ADR[

10]/

CI_A

[10]

PCM

ADR

[9]/

CI_A

[9]

PCM

ADR[

8]/C

I_A[

8]VD

DP

PCM

ADR[

7]/C

I_A[

7]PC

MAD

R[6

]/CI

_A[6

]PC

MAD

R[5]

/CI_

A[5]

PCM

ADR[

4]/C

I_A[

4]PC

MAD

R[3

]/CI

_A[3

]PC

MAD

R[2

]/CI

_A[2

]PC

MAD

R[1

]/CI

_A[1

]PC

MAD

R[0

]/CI

_A[0

]

65 66 67 68 69 71 73 7570 72 74 76 117

118

119

120

121

123

125

127

122

124

126

128

GPI

O3

GPI

O4

SAR0

SAR1

SAR2

SAR3

PWM

2

PWM

0PW

M1

PWM

3

180

179

176

175

172

170

168

166

165

163

161

159

157

154

152

150

178

177

174

173

171

169

167

164

162

160

158

156

155

153

151

149

148

147

146

145

143

142

141

144

CI_CD

GPIO97

GPIO99

CI_RST

GPIO98

PCMOEN

PCMWAIT/CI_WACKPCMIRQ/CI_INTPCMCEN/CI_CSPCMREG/CI_CLK

192

191

190

189

188

186

184

182

187

185

183

181

140

139

138

137

136

134

132

130

135

133

131

129

PCMWEN

PCMIOW/CI_WRPCMIOR/CI_RDGPIO15/CECVDDPSCZSDOSDISCK

244

243

240

239

236

234

232

230

229

227

225

223

221

218

216

214

242

241

238

237

235

233

231

228

226

224

222

220

219

217

215

213

212

211

210

209

207

206

205

208

AVD

D_M

PLL

XIN

XOU

TG

ND

USB

_DP

AVD

DL_

DVI

DQ

S[0]

255

254

253

252

250

248

246

251

249

247

245

204

203

202

201

200

198

196

194

199

197

195

193

AUVA

G

SIF1PSIF1M

GPIO0/UART_RX1/CEC

PCM

DAT

A[1]

/CI_

DAT

A[1]

PCM

DAT

A[2]

/CI_

DAT

A[2]

DQS[1]

MDATA[8]MDATA[9]DQM[1]

AVDD_DDR

MDATA[12]MDATA[13]MDATA[14]MDATA[15]

AVD

D_M

EMPL

LM

CLKE

MCL

KM

CLKZ

MVR

EFG

PIO

14/U

ART_

TX1

I2S_

OU

T_M

UTE

/CEC

DD

CR_C

KD

DCR

_DA

SPD

IFO

I2S_

OU

T_SD

I2S_

OU

T_BC

KVD

DC

GN

D

I2S_

OU

T_M

CKSP

DIF

I

I2S_

IN_W

S

I2S_

IN_S

DI2

S_IN

_BCK

MD

ATA[

0]AV

DD

_DD

R

MDATA[10]MDATA[11]AVDD_DDR

MD

ATA[

1]

VDD

PI2

S_O

UT_

WS

GND

AUVR

MG

ND

DQ

M[0

]G

ND

CASZ

RAS

ZW

EZBA

DR[

0]BA

DR[

1]

HSYNC0VSYNC0

HW

RESE

T

GPIO100

MD

ATA[

7]VD

DC

MD

ATA[

5]M

DAT

A[6]

AVD

D_D

DR

MD

ATA[

4]

MD

ATA[

2]M

DAT

A[3]

USB

_DM

AVD

D_U

SBU

SB_R

EXT

GN

D25

6

GN

D

PCM

DAT

A[6]

/CI_

DAT

A[6]

PCM

DAT

A[5]

/CI_

DAT

A[5]

PCM

DAT

A[4]

/CI_

DAT

A[4]

PCM

DAT

A[7]

/CI_

DAT

A[7]

VDD

C

DD

CA_D

AD

DCA

_CK

VDDPLVA0MLVA0P

LVA3P

LVA1MLVA1PLVA2MLVA2PLVACKMLVACKPLVA3M

GNDGNDAVDD_LPLLLVB0M

LVB3P

LVB0P

LVB3MLVBCKPLVBCKMLVB2PLVB2MLVB1PLVB1M

VDDC

TS1VALIDTS1DATA

INTIRINTS1CLKTS1SYNC

MAD

R[11

]M

ADR[

10]

MAD

R[9]

MAD

R[8]

MAD

R[7]

AVD

D_D

DR

MAD

R[6]

MAD

R[5]

MAD

R[4]

MAD

R[3]

MAD

R[2]

MAD

R[1]

MAD

R[0]

MAD

R[12

]

MS

D1

06

CL

XX

XX

XX

XX

X

XX

XX




PIN DESCRIPTION

Analog Interface

Pin Name Pin Type Function Pin

VCLAMP CVBS/YC Mode Clamp Voltage Bypass 20

REFP Internal ADC Top De-coupling Pin 21

REFM Internal ADC Bottom De-coupling Pin 22

REXT Analog Input External Resister 390 ohm to AVDD_33 15

BIN1P Analog Input Analog Blue Input from Channel 1 23

SOGIN1 Analog Input Sync-On-Green input from Channel 1 24

GIN1P Analog Input Analog Green Input from Channel 1 25

RIN1P Analog Input Analog Red Input from Channel 1 26

BINM Analog Input Reference Ground for Analog Blue Input 27

BIN0P Analog Input Analog Blue Input from Channel 0 28

GINM Analog Input Reference Ground for Analog Green Input 29

GIN0P Analog Input Analog Green Input from Channel 0 30

SOGIN0 Analog Input Sync-On-Green Input from Channel 0 31

RINM Analog Input Reference Ground for Analog Red Input 32

RIN0P Analog Input Analog Red Input from Channel 0 33

HSYNC1 Schmitt Trigger Input w/ 5V-tolerant

HSYNC/Composite Sync for VGA Input from channel 1 18

VSYNC1 Schmitt Trigger Input w/ 5V-tolerant

VSYNC for VGA Input from channel 1 19

HSYNC0 Schmitt Trigger Input w/ 5V-tolerant

HSYNC/Composite Sync for VGA Input from channel 0 36

VSYNC0 Schmitt Trigger Input w/ 5V-tolerant

VSYNC for VGA Input from channel 0 37

Analog Video Input/Output Interface


VCOM1 Analog Input CVBS Video Input Reference Ground 45

VCOM0 Analog Input CVBS Video Input Reference Ground 47

CVBS7 Analog Input CVBS (Composite) Video Input Channel 7 38












CVBSOUT Analog Output CVBS (Composite) Video Output 49

Analog Audio Input/Output Interface


SIF1P Analog Input SIF Audio Input Channel 1 52

SIF1M Analog Input Reference Ground for SIF Audio Input Channel 1 53

I2S_OUT_MCK Output Audio Master Clock Output 197

I2S_OUT_BCK Output Audio Bit Clock Output 202

I2S_OUT_WS Output Word Select Output; 4mA driving strength 198

I2S_OUT_SD Output Audio Serial Data Output; 4mA driving strength 203

I2S_OUT_MUTE/ CEC

Output w/5V-tolerant Audio Output Mute Control / Consumer Electronics Control

207

SPDIFO Output S/PDIF Audio Output; 4mA driving strength 204

I2S_IN_BCK Input Audio Bit Clock Input 194

I2S_IN_WS Input Word Select Input 193

I2S_IN_SD Input Audio Serial Data Input 195

SPDIFI Input S/PDIF Audio Input 196

AUVRM Analog Output Negative Reference Voltage for Audio ADC 66

AUVRP Analog Output Positive Reference Voltage for Audio ADC 67

AUVAG Analog Output Reference Voltage for Audio Common Mode 68

AUL0 Analog Input Audio Line Input Left Channel 0 56

AUR0 Analog Input Audio Line Input Right Channel 0 57







AUOUTL2 Analog Output Main Audio Output Left Channel 2 70

AUOUTR2 Analog Output Main Audio Output Right Channel 2 71









AUCOM Analog Input Reference Ground for Audio Line Input 64

Common Interface Pin Name Pin Type Function Pin

PCMDATA[7:0]/ CI_DATA[7:0]

I/O PCMCIA Data[7:0] / Common Interface Data[7:0]

92-99

PCMADR[14:0]/ CI_A[14:0]

Output PCMCIA Address[14:0] / Common Interface Address[14:0]

100-106, 108-115

PCMIOR/ CI_RD

Output PCMCIA Input/Output Read / Common Interface Read

135

PCMIOW/ CI_WR

Output PCMCIA Input/Output Write / Common Interface Write

136

PCMOEN Output PCMCIA Output Enable 137

PCMWEN Output PCMCIA Write Enable 138

PCMREG/ CI_CLK

Output PCMCIA Register / Common Interface Clock

139

PCMCEN/ CI_CS

Output PCMCIA Card Enable / Common Interface Chip Select

140

PCMIRQ/ CI_INT

Input PCMCIA Interrupt Request / Common Interface Interrupt

141

PCMWAIT/ CI_WACK

Input PCMCIA Extend Bus Wait Cycle / Common Interface Wait Acknowledge

142

CI_RST Output Common Interface Reset 172

CI_CD Input Common Interface Card Detect 173

TS Input Interface Pin Name Pin Type Function Pin

TS0CLK Input w/ 5V-tolerant TS Clock 89

TS0DATA[7:0] Input w/ 5V-tolerant TS Data in Parallel; LSB (bit 0) is for serial TS data 86-79

TS0VALID Input w/ 5V-tolerant TS Data Valid 87

TS0SYNC Input w/ 5V-tolerant TS Sync-Byte Indicator 88

TS1CLK Input w/ 5V-tolerant 2nd TS Clock 177

TS1DATA Input w/ 5V-tolerant 2nd TS Data in Parallel 174

TS1VALID Input w/ 5V-tolerant 2nd TS Data Valid 175

TS1SYNC Input w/ 5V-tolerant 2nd TS Sync-Byte Indicator 176




DVI/HDMI Interface Pin Name Pin Type Function Pin

RX0N Input DVI/HDMI Channel 0 Negative Data Input 6

RX0P Input DVI/HDMI Channel 0 Positive Data Input 7





RXCKN Input DVI/HDMI Negative Clock Input 4

RXCKP Input DVI/HDMI Positive Clock Input 5

LVDS Interface


LVA0M Output LVDS A-Link Channel 0 Negative Data Output 152

LVA0P Output LVDS A-Link Channel 0 Positive Data Output 151





LVACKM Output LVDS A-Link Negative Clock Output 146

LVACKP Output LVDS A-Link Positive Clock Output 145



LVB0M Output LVDS B-Link Channel 0 Negative Data Output 163

LVB0P Output LVDS B-Link Channel 0 Positive Data Output 162





LVBCKM Output LVDS B-Link Negative Clock Output 157

LVBCKP Output LVDS B-Link Positive Clock Output 156






Serial Flash Interface Pin Name Pin Type Function Pin

SCK Output SPI Flash Serial Clock 129

SDI Output SPI Flash Serial Data Input 130

SDO Input w/ 5V-tolerant SPI Flash Serial Data Output 131

SCZ Output SPI Flash Chip Select 132

IRIN Input w/5V-tolerant IR Receiver Input 178

INT Input w/5V-tolerant MCU Bus Interrupt; 4mA driving strength 179

GPIO Interface


GPIO125 I/O w/ 5V-tolerant General Purpose Input/Output; 4mA driving strength 14

GPIO100 I/O General Purpose Input/Output; 4mA driving strength 168




GPIO15/CEC I/O General Purpose Input/Output; 4mA driving strength 134

GPIO14/ UART_TX1

I/O w/ 5V-tolerant General Purpose Input/Output; 4mA driving strength / Universal Asynchronous Transmitter

208




GPIO1/ UART_TX1

I/O w/ 5V-tolerant General Purpose Input/Output; 4mA driving strength / Universal Asynchronous Transmitter

2

GPIO0/ UART_RX1/ CEC

I/O w/ 5V-tolerant General Purpose Input/Output; 4mA driving strength / Universal Asynchronous Receiver / Consumer Electronics Control

1

PWM3 Output Pulse Width Modulation Output; 4mA driving strength 127




SAR3 Analog Input SAR Low Speed ADC Input 3; General Purpose Input/Output

123


122


121






120

DRAM Interface


DQM[1:0] Output Data Mask for Low Byte; active high 188, 242

DQS[1:0] I/O Data Strobe 192, 246

MVREF Input Reference Voltage for DDR SDRAM Interface 209

MCLKZ Output DRAM Memory Negative Differential Clock 210

MCLK Output DRAM Memory Positive Differential Clock 211

MCLKE Output DRAM Memory Clock Enable 212

BADR[1:0] Output DRAM Memory Bank Address 228, 229

WEZ Output Write Enable; active low 230

RASZ Output Row Address Strobe; active low 231

CASZ Output Column Address Strobe; active low 232

MDATA[15:0] I/O DRAM Memory Data Bus 180-183, 185, 186, 189, 190, 234-237, 239, 240, 243, 244

MADR[12:0] Output DRAM Memory Address 227-222, 220-214

USB Interface


USB_REXT USB External Resistor Pin; Connected through 910 ohm (±1%) Resistor to GND (Pin

#252)

248

USB_DM Analog I/O USB Inverting Data Input/Output 250

USB_DP Analog I/O USB Non Inverting Data Input/Output 251

Misc. Interface


DDCD_DA I/O w/ 5V-tolerant HDCP Serial Bus Data/DDC Data of DVI/HDMI Port 16

DDCD_CK Input w/ 5V-tolerant HDCP Serial Bus Clock/DDC Clock of DVI/HDMI Port 17

DDCA_DA I/O w/ 5V-tolerant DDC Data for Analog Port 118

DDCA_CK I/O w/ 5V-tolerant DDC Clock for Analog Port 119

HWRESET Schmitt Trigger Input w/ 5V-tolerant

Hardware Reset; active high 128





DDCR_DA I/O w/ 5V-tolerant DDC Data for ROM 205

DDCR_CK I/O w/ 5V-tolerant DDC Clock for ROM 206

XIN Analog Input Crystal Oscillator Input 254

XOUT Analog Output Crystal Oscillator Output 253

Power Pins


AVDD_SIF 3.3V Power SIF Power 51

AVDD_AU 3.3V Power Audio Power 69

AVDD_DDR 2.5V Power DDR Power 184, 191, 221, 238, 245

AVDD_LPLL 3.3V Power LPLL Power 164

AVDD_MPLL 3.3V Power MPLL Power 255

AVDD_MEMPLL 3.3V Power PLL Power 213

AVDD_33 3.3V Power ADC Power 8, 34, 48

AVDDL_DVI 1.2V Power DVI Power 247

AVDD_USB 3.3V Power USB Power 249

VDDC 1.2V Power Digital Core Power 54, 78, 91, 167, 201, 233

VDDP 3.3V Power Digital Input/Output Power 76, 107, 133, 153, 199

GND Ground Ground 11, 35, 50, 55, 65, 77, 90, 165, 166, 187, 200, 241, 252, 256




ELECTRICAL SPECIFICATIONS

Analog Interface Characteristics Parameter Min Typ Max Unit

VIDEO ADC Resolution 10 Bits

DC ACCURACY

Differential Nonlinearity TBD TBD LSB

Integral Nonlinearity TBD LSB

VIDEO ANALOG INPUT

Input Voltage Range

Minimum 0.5 V p-p

Maximum 1.0 V p-p

Input Bias Current 1 uA

Input Full-Scale Matching 1.5 %FS Brightness Level Adjustment 62 %FS

SWITCHING PERFORMANCE

Maximum Conversion Rate 150 MSPS

Minimum Conversion Rate 12 MSPS

HSYNC Input Frequency 15 200 kHz

PLL Clock Rate 12 150 MHz

PLL Jitter 500 ps p-p

Sampling Phase Tempco 15 ps/°C

DYNAMIC PERFORMANCE

Analog Bandwidth, Full Power 250 MHz

DIGITAL INPUTS

Input Voltage, High (VIH) 2.5 V

Input Voltage, Low (VIL) 0.8 V

Input Current, High (IIH) -1.0 uA

Input Current, Low (IIL) 1.0 uA

Input Capacitance 5 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) VDDP-0.1 V

Output Voltage, Low (VOL) 0.1 V

VIDEO ANALOG OUTPUT

CVBS Buffer Output Output Low Output High

1.5

2.0

V

V




Parameter Min Typ Max Unit

AUDIO

ADC Input 2.0 V p-p

DAC Output 2.0 V p-p

SIF Input Range Minimum Maximum

1.0

0.1

V p-p V p-p

FSSW Input1 0 1.8 V

SAR ADC Input 0 3.3 V

FB ADC Input2 0 1.25 V

Specifications subject to change without notice. Notes: 1. Input full scale is typically 1.8V, but input range is 0 ~ 3.3V. 2. Input full scale is 1.25V, but input range is 0 ~ 3.3V.

Absolute Maximum Ratings Parameter Symbol Min Typ Max Units

3.3V Supply Voltages VVDD_33 -0.3 3.6 V

2.5V Supply Voltages VVDD 25 -0.3 2.75 V

1.2V Supply Voltages VVDD_12 -0.3 1.32 V

Input Voltage (5V tolerant inputs) VIN5Vtol -0.3 5.0 V

Input Voltage (non 5V tolerant inputs) VIN -0.3 VVDD_33 V

Ambient Operating Temperature TA 0 70 °C

Storage Temperature TSTG -40 150 °C

Junction Temperature TJ 150 °C

Thermal Resistance (Junction to Air) Natural Conversion

θJA TBD °C/W

Thermal Resistance (Junction to Case) Natural Conversion

θJC TBD °C/W

Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and does not imply functional operation of the device. Exposure to absolute maximum ratings for extended periods may affect device reliability.




ORDERING GUIDE Model Temperature

Range

Package

Description

Package

Option

MSD106CL 0°C to +70°C LQFP 256

MSD106CL-LF 0°C to +70°C LQFP 256

MSD106CL-S1 0°C to +70°C LQFP 256

MSD106CL-LF-S1 0°C to +70°C LQFP 256









MSD106CL-Z1 0°C to +70°C LQFP 256

MSD106CL-LF-Z1 0°C to +70°C LQFP 256

MSD106CL-Z1-S1 0°C to +70°C LQFP 256

MSD106CL-LF-Z1-S1 0°C to +70°C LQFP 256









Note on product suffix: 1. “LF”: Lead-free version. 2. “S1” ~ “S5”: Advanced surround features. 3. “Z1”: Dolby Digital function not provided.

Code Description

S1 SRS TruSurround XTTM

S2 Dolby® ProLogic® II + Dolby® Virtual Speaker

S3 Dolby® ProLogic® II + Virtual Dolby® Surround

S4 BBE® Digital

S5 BBE® ViVATM

Model Temperature

Range

Package

Description

Package

Option

MSD106CHL 0°C to +70°C LQFP 256

MSD106CHL-LF 0°C to +70°C LQFP 256

MSD106CHL-S1 0°C to +70°C LQFP 256

MSD106CHL-LF-S1 0°C to +70°C LQFP 256









MSD106CHL-Z1 0°C to +70°C LQFP 256

MSD106CHL-LF-Z1 0°C to +70°C LQFP 256

MSD106CHL-Z1-S1 0°C to +70°C LQFP 256

MSD106CHL-LF-Z1-S1 0°C to +70°C LQFP 256












The SRS TruSurround XTTM technology rights incorporated in the

MSD106CL are owned by SRS Labs, a U.S. Corporation and

licensed to MStar. Purchaser of MSD106CL must sign a license for

use of the chip and display of the SRS Labs trademarks. Any

products incorporating the MSD106CL must be sent to SRS Labs

for review. SRS TruSurround XT is protected under US and foreign

patents issued and/or pending. SRS TruSurround XT, SRS and (O)

symbol are trademarks of SRS Labs, Inc. in the United States and

selected foreign countries. Neither the purchase of the MSD106CL,

nor the corresponding sale of audio enhancement equipment

conveys the right to sell commercialized recordings made with any

SRS technology. SRS Labs requires all set makers to comply with

all rules and regulations as outlined in the SRS Trademark Usage

Manual separately provided.

MARKING INFORMATION MSD106CL

Operation Code BDate Code (YYWW)

Lot NumberOperation Code A

Part Number

DISCLAIMER MSTAR SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO RESPONSIBILITY IS ASSUMED BY MSTAR SEMICONDUCTOR ARISING OUT OF THE APPLICATION OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

REVISION HISTORY Document Description Date

MSD106CL_pb_v01 Initial release Oct 2007

Electrostatic charges accumulate on both test equipment and human body and can discharge without detection. MSD106CL comes with ESD protection circuitry; however, the device may be permanently damaged when subjected to high energy discharges. The device should be handled with proper ESD precautions to prevent malfunction and performance degradation.




MECHANICAL DIMENSIONS

Millimeter Inch Symbol

Min. Nom. Max. Min. Nom. Max.

A - - 1.6 - - 0.063

A1 0.05 - - 0.002 - -

A2 1.35 1.40 1.45 0.053 0.055 0.057

D 30.00 1.181

D1 28.00 1.102

D2 - - 10.0 - - 0.394

E 30.00 1.181

E1 28.00 1.102

E2 - - 10.0 - - 0.394

Millimeter Inch Symbol

Min. Nom. Max. Min. Nom. Max.

θ 0° - 7° 0° - 7°

θ1 0° - - 0° - -

θ2 12° Ref 12° Ref

b 0.11 0.16 0.21 0.004 0.006 0.008

c 0.12 - 0.20 0.005 - 0.008

e 0.40 TYP. 0.0157 TYP.

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 Ref 0.039 Ref

S 0.20 - - 0.008 - -

θ2

E E1

Gauge Plane0.25mm

θ

θ1

Seating Plane

R1R2

D

D1

L1

A1A2A

c

S

D2

E2

E-Pad(at back of IC)

b eL

February 2006

Ordering Information

DJCE6353 882077 64 Pin LQFP TraysWJCE6353 882206 64 Pin LQFP* TraysDJCE6353 S L9EN 882128 64 Pin LQFP Tape and ReelWJCE6353 S L9G5 882170 64 Pin LQFP* Tape and Reel

*Pb Free Matte Tin

CE6353Nordig Unified DVB-T COFDM Terrestrial Demodulator forPC-TV and Hand-held Digital TV (DTV) Data Sheet

Features• Compliant with ETSI 300 744 DVB-T, Unified

Nordig and DTG performance specifications • High performance with fast fully blind acquisition

and tracking capability • Low power consumption: less than 0.32 W, and

eco-friendly standby and sleep modes • Digital filtering of adjacent channels • Single 8 MHz SAW filter for 6, 7 & 8 MHz OFDM • Superior single frequency network performance • Fast AGC to track out signal fades • Good Doppler tracking capability• Enhanced frequency capture range to include

triple offsets• External 4 MHz clock or single low-cost

20.48 MHz crystal, tolerance up to +/-200 ppm• Automatic mode (2 K/8 K), guard and spectral

inversion detection• Very low driver software overhead due to on-chip

state-machine control• Novel RF level detect facility via a separate ADC

1Intel CorporationIntel and the Intel logo are registered trademarks of Intel Corporation*Other names and brands may be claimed as the property of others.

Figure 1 - B

• Pre and post Viterbi-decoder bit error rates, and uncorrectable block count

D55752-001 or its subsidiaries in the United States and other countries.

Copyright © 2006 Intel Corporation. All rights reserved.

lock Diagram

CE6353 Data Sheet

Applications• Digital terrestrial set-top boxes• Integrated digital televisions• Personal video recorders• PC-TV receivers• Portable applications

DescriptionThe CE6353 is a superior fourth generation fully compliant ETSI ETS300 744 COFDM demodulator that exceeds,with margin, the performance requirements of all known DVB-T digital terrestrial television standards, includingUnified Nordig and DTG.

A high performance 10 bit on-chip ADC is used to sample the 44 or 36 MHz IF analog signal. Advanced digitalfiltering of the upper and lower channel enables a single 8 MHz channel SAW filter to be used for 6, 7 and 8 MHzOFDM signal reception. All sampling and other internal clocks are derived from a single 20.48 MHz crystal or a 4MHz clock input, the tolerance of which may be relaxed as much as 200 ppm.

The CE6353 has a wide frequency capture range able to automatically compensate for the combined offsetintroduced by the tuner xtal and broadcaster triple frequency offsets.

An on-chip state machine controls all acquisition and tracking operations of the CE6353 as well as controlling thetuner via a 2-wire bus. Any frequency range can be automatically scanned for digital TV channels. This mechanismensures minimal interaction, maximum flexibility and fast acquisition - very low software overhead.

Also included in the design is a 7-bit ADC to detect the RF signal strength and thereby efficiently control the tunerRF AGC.

Users have access to all the relevant signal quality information, including input signal power level, signal-to-noiseratio, pre-Viterbi BER, post-Viterbi BER, and the uncorrectable block counts. The error rate monitoring periods areprogrammable over a wide range.

The device is packaged in a 10 x 10 mm 64-pin LQFP and is very low power.

2Intel Corporation

CE6353 Data Sheet

Table of Contents

3Intel Corporation

1.0 Pin & Package Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1 Pin Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.2 Pin Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.3 IF to Baseband Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.4 Adjacent Channel Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.5 Interpolation and Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.6 Carrier Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.7 Symbol Timing Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.8 Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.9 Common Phase Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.10 Channel Equalization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.11 Impulse Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.12 Transmission Parameter Signalling (TPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.13 De-Mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.14 Symbol and Bit De-Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.15 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.16 MPEG Frame Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.17 De-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.18 Reed-Solomon Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.19 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.20 MPEG Transport Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.1 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.1 Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.1.2 Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.1.3 Examples of 2-Wire Bus Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.1.4 Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 MPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.2.1 Data Output Header Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.2.2 MPEG Data Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.2.3 MPEG Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.2.4 MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.2.5 MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224.4 Crystal Specification and External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4.1 Selection of External Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.4.1.1 Loop Gain Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.4.1.2 List of Equation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.4.1.3 Calculating Crystal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.4.1.4 Capacitor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.4.1.5 Oscillator/Clock Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.0 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CE6353 Data Sheet

List of Figures

4Intel Corporation

Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Figure 2 - Pin Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 3 - OFDM Demodulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 4 - FEC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 5 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 6 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 7 - MPEG Output Data Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 8 - MPEG Timing - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 9 - MPEG Timing - MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 10 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 11 - External Clocking via AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 12 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CE6353 Data Sheet

List of Tables

5Intel Corporation

Table 1 - Pin Names - numeric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 2 - Pin Names - alphabetical order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 3 - Timing of 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CE6353 Data Sheet

1.0 Pin & Package Details

1.1 Pin Outline

Figure 2 - Pin Outline

6Intel Corporation

CE6353 Data Sheet

1.2 Pin Allocation

Pin Function Pin Function Pin Function Pin Function

1 Vss 17 SADD1 33 Vdd 49 MDO0

2 Vdd 18 SADD0 34 RFLEV 50 MDO1

3 Vss 19 CVdd 35 CLK2/GPP0 51 MDO2

4 CLK1 20 Vss 36 DATA2/GPP1 52 MDO3

5 DATA1 21 PLLVdd 37 CVdd 53 MDO4

6 IRQ 22 PLLGND 38 Vss 54 Vdd

7 CVdd 23 XTI 39 CVdd 55 Vss

8 Vss 24 XTO 40 Vss 56 MDO5

9 RESET 25 Vss 41 AGC2/GPP2 57 MDO6

10 SLEEP 26 PLLTEST 42 AGC1 58 MDO7

11 STATUS 27 OSCMODE 43 GPP3 59 CVdd

12 28 AVdd 44 SMTEST 60 Vss

13 Vdd 29 AGnd 45 Vdd 61 MOCLK

14 Vss 30 VIN 46 Vss 62 BKERR

15 31 VIN 47 MOSTRT 63 MICLK

16 32 AGnd 48 MOVAL 64 CVdd

Table 1 - Pin Names - numeric

Function Pin Function Pin Function Pin Function Pin

AGC1 42 GPP3 43 PLLTEST 26 Vdd 54

AGC2/GPP2 41 IRQ 6 PLLVdd 21 VIN 30

AGnd 29 MDO0 49 RESET 9 VIN 31

AGnd 32 MDO1 50 RFLEV 34 Vss 1

AVdd 28 MDO2 51 SADD0 18 Vss 3

BKERR 62 MDO3 52 SADD1 17 Vss 8

CLK1 4 MDO4 53 N/C 16 Vss 14

CLK2/GPP0 35 MDO5 56 N/C 15 Vss 20

CVdd 7 MDO6 57 N/C 12 Vss 25

CVdd 19 MDO7 58 SLEEP 10 Vss 38

CVdd 37 MICLK 63 SMTEST 44 Vss 40

CVdd 39 MOCLK 61 STATUS 11 Vss 46

Table 2 - Pin Names - alphabetical order

7Intel Corporation

CE6353 Data Sheet

1.3 Pin Description

CVdd 59 MOSTRT 47 Vdd 2 Vss 55

CVdd 64 MOVAL 48 Vdd 13 Vss 60

DATA1 5 OSCMODE 27 Vdd 33 XTI 23

DATA2/GPP1 36 PLLGND 22 Vdd 45 XTO 24

Pin Description Table

Pin No Name Pin Description I/O Type V mA

MPEG pins

47 MOSTRT MPEG packet start O

CMOS Tristate

3.3 1

48 MOVAL MPEG data valid O 3.3 1

49-53, 56-58 MDO(0:4)/MDO(5:7) MPEG data bus O 3.3 1

61 MOCLK MPEG clock out O 3.3 1

62 BKERR Block error O 3.3 1

63 MICLK MPEG clock in ICMOS

3.3

11 STATUS Status output O 3.3 1

6 IRQ Interrupt output O Open drain 5 6

Control pins

4 CLK1 Serial clock I CMOS 5

5 DATA1 Serial data I/O Open drain 5 6

23 XTI Low phase noise oscillator I

CMOS

24 XTO O

10 SLEEP Device power down I 3.3

12, 15-18 SADD(4:0) Serial address set I 3.3

44 SMTEST Production test (only set low) I 3.3

35 CLK2/GPP0 Serial clock tuner I/O

Open drain

5 6

36 DATA2/GPP1 Serial data tuner I/O 5 6

42 AGC1 Primary AGC O 5 6

41 AGC2/GPP2 Secondary AGC I/O 5 6

43 GPP(3) General purpose I/O I/O 5 6

9 RESET Device reset I CMOS 5

27 OSCMODE Crystal oscillator mode I CMOS 3.3

26 PLLTEST PLL analog test O (tristated)

Table 2 - Pin Names - alphabetical order (continued)

8Intel Corporation

CE6353 Data Sheet

Analog inputs

30 VIN positive input I

31 VIN negative input I

34 RFLEV RF level I

Supply pins

21 PLLVdd PLL supply S 1.8

22 PLLGnd S 0

7, 19, 37, 39, 59, 64 CVdd Core logic power S 1.8

2, 13, 45, 54, Vdd I/O ring power S 3.3

1, 3, 8, 14, 20, 25, 38, 40, 46, 55, 60 Vss Core and I/O ground S 0

28 AVdd ADC analog supply S 1.8

29, 32 AGnd S 0

33 Vdd 2nd ADC supply S 3.3

Pin Description Table (continued)

Pin No Name Pin Description I/O Type V mA

9Intel Corporation

CE6353 Data Sheet

2.0 Functional DescriptionA functional block diagram of the CE6353 OFDM demodulator is shown in Figure 3. This accepts an IF analogsignal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing andfrequency synchronization operations are all digital and there are no analog control loops except the AGC. Thefrequency capture range is large enough for all practical applications. This demodulator has novel algorithms tocombat impulse noise as well as co-channel and adjacent channel interference. If the modulation is hierarchical,the OFDM outputs both high and low priority data streams. Only one of these streams is FEC-decoded, but the FECcan be switched from one stream to another with minimal interruption to the transport stream.

Figure 3 - OFDM Demodulator Diagram

The FEC module shown in Figure 4 consists of a concatenated convolutional (Viterbi) and Reed-Solomon decoderseparated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions toprovide the best performance over a wide range of channel conditions. The trace-back depth of 128 ensuresminimum loss of performance due to inevitable survivor truncation, especially at high code rates. Both the Viterbiand Reed-Solomon decoders are equipped with bit-error monitors. The former provides the bit error rate (BER) atthe OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collectingintervals of these are programmable over a very wide range.

10Intel Corporation

CE6353 Data Sheet

Figure 4 - FEC Block Diagram

The FSM controller shown in Figure 3 controls both the demodulator and the FEC. It also drives the 2-wire bus tothe tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of thereceived signal. It can also be used to scan any defined frequency range searching for OFDM channels. Thismechanism provides the fast channel scan and acquisition performance, whilst requiring minimal softwareoverhead in the host driver.

The algorithms and architectures used in the CE6353 have been optimized to minimize power consumption.

2.1 Analog-to-Digital Converter

The CE6353 has a high performance 10-bit analog-to-digital converter (ADC) which can sample a 6, 7 or 8 MHzbandwidth OFDM signal, with its spectrum centred at:

• 36.17 MHz IF

• 43.75 MHz IF

• 5 - 10 MHz near-zero IF

An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The PLL is highlyprogrammable allowing a wide choice of sampling frequencies to suit any IF frequency, and all signal bandwidths.

2.2 Automatic Gain Control

An AGC module compares the absolute value of the digitized signal with a programmable reference. The errorsignal is filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, whichhas to be RC low-pass filtered to obtain the voltage to control the amplifier.

The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADCclipping and a small value results in excessive quantization noise. Hence the optimum value has been determinedassuming the input signal amplitude to be Gaussian distributed. The latter is justified by applying the central limittheorem in statistics to the OFDM signal, which consists of a large number of randomly modulated carriers. Thisreference or target value may have to be lowered slightly for some applications. Slope control bits have beenprovided for the AGCs and these have to be set correctly depending on the gain-versus-voltage slope of the gaincontrol amplifiers.

11Intel Corporation

CE6353 Data Sheet

The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking.The AGC is free running during OFDM channel changes and locks to the new channel while the tuner lock is beingestablished. This is one of the features of CE6353 used to minimize acquisition time. A robust AGC lockmechanism is provided and the other parts of the CE6353 begin to acquire only after the AGC has locked.

2.3 IF to Baseband Conversion

Sampling a 36.17 MHz IF signal at 45 MHz results in a spectrally inverted OFDM signal centred atapproximately 8.9 MHz. The first step of the demodulation process is to convert this signal to a complex (in-phaseand quadrature) signal in baseband. A correction for spectral inversion is implemented during this conversionprocess. Note also that the CE6353 has control mechanisms to search automatically for an unknown spectralinversion status.

2.4 Adjacent Channel Filtering

Adjacent channels, in particular the Nicam digital sound signal associated with analog channels, are filtered prior tothe FFT.

2.5 Interpolation and Clock Synchronization

CE6353 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC samples thesignal at a fixed rate, for example, 45.056 MHz. Conversion of the 45.056 MHz signal to the OFDM sample rate isachieved using the time-varying interpolator. The OFDM sample rate is 64/7 MHz for 8 MHz and this is scaled byfactors 6/8 and 7/8 for 6 and 7 MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate isprogrammed in a CE6353 register (defaults are for 45 MHz sampling and 8 MHz OFDM). The clock recovery phaselocked loop in the CE6353 compensates for inaccuracies in this ratio due to uncertainties of the frequency of thesampling clock.

2.6 Carrier Frequency Synchronization

There can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and partly due tobroadcast frequency shifts, typically 1/6 MHz. These are tracked out digitally, up to 1 MHz in 2 K and 8 K modes,without the need for an analog frequency control (AFC) loop.

The default frequency capture range has been set to ±286 kHz in the 2 K and 8 K mode. However, these valuescan be increased, if necessary, by programming an on-chip register (see 7.4.1). It is recommended that a largercapture range be used for channel scan in order to find channels with broadcast frequency shifts, without having toadjust the tuner. After the OFDM module has locked (the AFC will have been previously disabled), the frequencyoffset can be read from an on-chip register.

2.7 Symbol Timing Synchronization

This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize inter-symbol interference in the presence of multi-path distortion. Furthermore, this trigger point is continuously updatedto dynamically adapt to time-variations in the transmission channel.

2.8 Fast Fourier Transform

The FFT module uses the trigger information from the timing synchronization module to set the start point for anFFT. It then uses either a 2 K or 8 K FFT to transform the data from the time domain to the frequency domain. Anextremely hardware-efficient and highly accurate algorithm has been used for this purpose.

12Intel Corporation

CE6353 Data Sheet

2.9 Common Phase Error Correction

This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect ofthe tuner phase noise on system performance.

2.10 Channel Equalization

This consists of two parts. The first part involves estimating the channel frequency response from pilot information.Efficient algorithms have been used to track time-varying channels with a minimum of hardware.

The second part involves applying a correction to the data carriers based on the estimated frequency response ofthe channel. This module also generates dynamic channel state information (CSI) for every carrier in every symbol.

2.11 Impulse Filtering

CE6353 contains several mechanisms to reduce the impact of impulse noise on system performance.

2.12 Transmission Parameter Signalling (TPS)

An OFDM frame consists of 68 symbols and a superframe is made up of four such frames. There is a set of TPScarriers in every symbol and all these carry one bit of TPS. These bits, when combined, include information aboutthe transmission mode, guard ratio, constellation, hierarchy and code rate, as defined in ETS 300 744. In addition,the first eight bits of the cell identifier are contained in even frames and the second eight bits of the cell identifier arein odd frames. The TPS module extracts all the TPS data, and presents these to the host processor in a structuredmanner.

2.13 De-Mapper

This module generates soft decisions for demodulated bits using the channel-equalized in-phase and quadraturecomponents of the data carriers as well as per-carrier channel state information (CSI). The de-mapping algorithmdepends on the constellation (QPSK, 16QAM or 64QAM) and the hierarchy (α = 0, 1, 2 or 4). Soft decisions for bothlow- and high-priority data streams are generated.

2.14 Symbol and Bit De-Interleaving

The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The de-interleaver modules consist largely of memory to invert these interleaving functions and present the soft decisionsto the FEC in the original order.

13Intel Corporation

CE6353 Data Sheet

2.15 Viterbi Decoder

The Viterbi decoder accepts the soft decision data from the OFDM demodulator and outputs a decoded bit-stream.The decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the branchmetrics and passes these to a 64-state path-metric updating unit, which in turn outputs a 64-bit word to the survivormemory. The Viterbi decoded bits are obtained by tracing back the survivor paths in this memory. A trace-backdepth of 128 is used to minimize any loss in performance, especially at high code rates.

The decoder re-encodes the decoded bits and compares these with received data (delayed) to compute bit errorsat its input, on the assumption that the Viterbi output BER is significantly lower than its input BER.

2.16 MPEG Frame Aligner

The Viterbi decoded bit stream is aligned into 204-byte frames. A robust synchronization algorithm is used toensure correct lock and to prevent loss of lock due to noise impulses.

2.17 De-interleaver

Errors at the Viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over anumber of 204-byte frames to give the Reed-Solomon decoder a better chance of correcting these. The de-interleaver is a memory unit which implements the inverse of the convolutional interleaving function introduced bythe transmitter.

2.18 Reed-Solomon Decoder

Every 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of asystematic (255,239) Reed-Solomon code. The corresponding (204,188) Reed-Solomon decoder is capable ofcorrecting up to eight byte errors in a 204-byte frame. It may also detect frames with more than eight byte errors.

In addition to efficiently performing this decoding function, the Reed-Solomon decoder in CE6353 keeps a count ofthe number of bit errors corrected over a programmable period and the number of uncorrectable blocks. Thisinformation can be used to compute the post-Viterbi BER.

2.19 De-scrambler

The de-scrambler de-randomizes the Reed-Solomon decoded data by generating the exclusive-OR of this with apseudo-random bit sequence (PRBS). This outputs 188-byte MPEG transport packets. The TEI bit of the packetheader may be set if required to indicate uncorrectable packets.

2.20 MPEG Transport Interface

MPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to presentthe MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guardratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the CE6353with a clock provided by the user.

14Intel Corporation

CE6353 Data Sheet

3.0 Interfaces

3.1 2-Wire Bus

3.1.1 Host

The primary 2-wire bus serial interface uses pins:

• DATA1 (pin 5) serial data, the most significant bit is sent first.

• CLK1 (pin 4) serial clock.

The 2-wire bus address is determined by applying VDD or VSS to the SADD[4:0] pins.

In TNIM evaluation applications, the 2-wire bus address is 0001 111 R/W with the pins connected as follows:

When the CE6353 is powered up, the RESET pin 9 should be held low for at least 50 ms after VDD has reachednormal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire busaddress. ADDR[0] is the R/W bit.

The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receivemode, the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADDregister takes an 8-bit value that determines which of 256 possible register addresses is written to by the followingbyte. Not all addresses are valid and many are reserved registers that must not be changed from their defaultvalues. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to accessthe reserved registers accidentally.

Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip addressis not recognized, the CE6353 will ignore all activity until a valid chip address is received. The 2-wire bus STARTcommand does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to aparticular read register with a write command, followed immediately with a read data command. If required, thiscould next be followed with a write command to continue from the latest address. RADD would not be sent in thiscase. Finally, a STOP command should be sent to free the bus.

When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read outis the contents of register 00.

3.1.2 Tuner

The CE6353 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. See registerGPP_CTL address 0x8C.

Master control mode is selected by setting register SCAN_CTL (0x62) [b3] = 1.

The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2.

ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1]

Not programmable SADD[1] SADD[0]

VSS VSS VSS VDD VDD VDD VDD

15Intel Corporation

CE6353 Data Sheet

3.1.3 Examples of 2-Wire Bus Messages

KEY: S Start condition W Write (= 0)

P Stop condition R Read (= 1)

A Acknowledge NA NOT Acknowledge

Italics CE6353 output RADD Register Address

Write operation - as a slave receiver:

Read operation - CE6353 as a slave transmitter:

Write/read operation with repeated start - CE6353 as a slave transmitter:

3.1.4 Primary 2-Wire Bus Timing

Figure 5 - Primary 2-Wire Bus Timing

Where: S = Start

Sr = Restart, i.e., start without stopping first.

P = Stop.

S DEVICE W A RADD A DATA A DATA A P

ADDRESS (n) (reg n) (reg n+1)

S DEVICE R A DATA A DATA A DATA NA P

ADDRESS (reg 0) (reg 1) (reg 2)

S DEVICE W A RADD A S DEVICE R A DATA A DATA NA P

ADDRESS (n) ADDRESS (reg n) (reg n+1)

P S

Sr P

LOWttR

tHD;STA HD;DATt

t F

HIGHt tSU;DAT SU;STAt

DATA1

CLK1

t BUFF

t SU;STO

16Intel Corporation

CE6353 Data Sheet

Parameter SymbolValue

UnitMin. Max.

CLK clock frequency (Primary) fCLK 0 400 1

1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.

kHz

Bus free time between a STOP and START condition. tBUFF 200 ns

Hold time (repeated) START condition. tHD;STA 200 ns

LOW period of CLK clock. tLOW 1300 ns

HIGH period of CLK clock. tHIGH 600 ns

Set-up time for a repeated START condition. tSU;STA 200 ns

Data hold time (when input). tHD;DAT 100 ns

Data set-up time tSU;DAT 100 ns

Rise time of both CLK and DATA signals. tR note 2

2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.

ns

Fall time of both CLK and DATA signals, (100 pF to ground). tF 20 ns

Set-up time for a STOP condition. tSU;STO 200 ns

Table 3 - Timing of 2-Wire Bus

17Intel Corporation

CE6353 Data Sheet

3.2 MPEG

3.2.1 Data Output Header Format

Figure 6 - DVB Transport Packet Header Byte

After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.

Additionally when the TEI_En bit in the OP_CTRL_0 register (0x5A) is set high (default), the TEI bit of anyuncorrectable packet will automatically be set to ‘1’. If TEI_En bit is low then TEI bit will not be changed (but notethat if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high atoutput).

TEI

0 1 0 0 0 1 1 1 1st byte

2nd byte

Transport Packet Header 4 bytes

184 Transport packet bytes

188 byte packet output

MDO[7] MDO[0]

18Intel Corporation

CE6353 Data Sheet

3.2.2 MPEG Data Output Signals

The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement inthe packet synchronization byte position is limited to ±1 output clock period. MOCLK will be a continuously runningclock once symbol lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 7 withMOCLKINV = ‘1’, the default state, see register 0x50.

All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK(MOCLKINV = 1) to present stable data and signals on the positive edge of the clock.

A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low duringthe inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte ofa packet and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packetwhere uncorrectable bytes are detected and will remain low until the last byte has been clocked out.

Figure 7 - MPEG Output Data Waveforms

3.2.3 MPEG Output Timing

Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 80oC, Output load = 10pF.

Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -10oC, Output load = 10pF.

MOCLK frequency = 45.06 MHz.

MDO7:0

MOCLKINV=1MOCLK

MOSTRT

MOVAL

BKERR

Tp Ti

1st byte packet n 188 byte packet n 1st byte packet n+1

19Intel Corporation

CE6353 Data Sheet

3.2.4 MOCLKINV = 1

Figure 8 - MPEG Timing - MOCLKINV = 1

3.2.5 MOCLKINV = 0

MDOSWAP = 0

The hold time is better when MOCLKINV = 1, therefore this should be used if possible.

Figure 9 - MPEG Timing - MOCLKINV = 0

Parameter Delay conditions

UnitsMaximum Minimum

Data output delay tD 3.0 1.0

nsSetup Time tSU 7.0 10.0

Hold Time tH 7.0 10.0

Parameter Delay conditions

UnitsMaximum Minimum

Data output delay tD 3.0 1.0

nsSetup Time tSU 18.0 20.0

Hold Time tH 1.0 0.2

tD

tSU

MOCLK

MDOMOSTRTMOVAL

BKERRB

tHBKERR

tD

tSU

MOCLK

MDOMOSTRTMOVAL

BKERRB

tH

BKERR

20Intel Corporation

CE6353 Data Sheet

4.0 Electrical Characteristics

4.1 Recommended Operating Conditions

4.2 Absolute Maximum Ratings

Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied.

Parameter Symbol Min. Typ. Max. Units

Power supply voltage: periphery VDD 3.0 3.3 3.6 V

core CVDD 1.62 1.8 1.98 V

Power supply current: periphery 1

1. Current from the 3.3 V supply will be mainly dependent on the external loads.

IDDP 1 mA

core IDDC 170 mA 2

2. Current given is for optimum performance, lower current is possible with reduced performance.

Input clock frequency 3

3. The min/max frequencies given are those supported by the oscillator cell. Required system frequencies are as defined in the designmanual. Frequencies outside these limits are acceptable with an external clock signal.

XTI 16.00 20.48 25.00 MHz

CLK1 primary serial clock frequency 4

4. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.

fCLK 400 kHz

Ambient operating temperature -10 80 °C

Maximum Operating Conditions

Parameter Symbol Min. Max. Unit

Power supply VDD -0.3 +3.6 V

CVDD -0.3 +2.0 V

Voltage on input pins (5 V rated) VI -0.3 5.5 V

Voltage on input pins (3.3 V rated) VI -0.3 VDD + 0.3 V

Voltage on output pins (5 V rated) VO -0.3 5.5 V

Voltage on output pins (3.3 V rated) VO -0.3 VDD + 0.3 V

Storage temperature TSTG -55 150 °C

Operating ambient temperature TOP -10 80 °C

Junction temperature TJ 125 °C

21Intel Corporation

CE6353 Data Sheet

4.3 DC Electrical Characteristics

4.4 Crystal Specification and External Clocking

Parallel resonant fundamental frequency (preferred) 20.4800 MHzTolerance over operating temperature range ± 150 ppmTolerance overall ± 200 ppmTypical load capacitance 27 pFDrive level 0.4 mW maxEquivalent series resistance <25 Ω

DC Electrical Characteristics

Parameter Conditions Pins Symbol Min. Typ. Max. UnitOperating voltage

periphery VDD 3.0 3.3 3.6 V

core CVDD 1.62 1.8 1.98 VSupply current 1

1. Current given is for optimum performance, lower current is possible with reduced performance.

1.62>CVDD>1.98 IDDCORE 170 mASupply current sleep mode 300 μAOutputsOutput levels IOH 2mA

3.0>VDD>3.6MDO(7:0), MOVAL, MOSTRT, MOCLK, STATUS, BKERR

VOH 2.4 V

IOL 2mA3.0>VDD>3.6

VOL 0.4 V

IOL 6mA3.0>VDD>3.6

GPP(3:0), DATA1, AGC1, AGC2, IRQ

VOL 0.4 V

Output capacitance Not including track MDO(7:0), MOVAL, MOSTRT, MOCLK, STATUS, BKERR

3.0 pF

GPP(3:0), DATA1, AGC1, AGC2,IRQ

3.6 pF

Output leakage (tri-state) 1 μAInputsInput levels 3.0>VDD>3.6

-0.5 ≥ Vin ≥ VDD+0.5V

MICLK, SADD(4:0)SLEEP, OSCMODE

VIH 2.0 V

Input levels 3.0>VDD>3.6-0.5 ≥ Vin ≥ +5.5V

GPP(3:0), CLK1, DATA1, RESET

VIH 2.0 V

Input levels 3.0>VDD>3.6

Capacitances do not include track

All inputs VIL 0.8 VInput leakage Current SLEEP, SMTEST,

MICLK, CLK1, OSCMODE

±1 μAInput capacitance 1.8 pF

Input capacitance SADD(4:0), DATA1, GPP(3:0)

3.6 pF

22Intel Corporation

CE6353 Data Sheet

Figure 10 - Crystal Oscillator Circuit

4.4.1 Selection of External Components

The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain isgreater than unity. Correct selection of the two capacitors is very important and the following method isrecommended to obtain values for C1 and C2.

4.4.1.1 Loop Gain Equation

Although oscillation may still occur if the loop gain is just above 1, a loop gain of between 5 and 25 is optimum toensure that oscillations will occur across all variations in temperature, process and supply voltage, and that thecircuit will exhibit good start-up characteristics.

Equation 1 -

Equation 2 -

4.4.1.2 List of Equation Parameters

A total loop gain (between 5 and 25)

Cin C1 + Cpar

Cout C2 + Cpar

Cpar parasitic capacitance associated with each oscillator pin (XTI and XTO). It consists of track capacitances, package capacitance and cell input capacitance. Normally Cpar ≈ 4pF.

Zo 9.143 kΩ - output impedance of amplifier at 1.8 V operation - typical

gm 8.736 mA/V - transconductance of amplifier at 1.8 V operation -typical

Rf 2.3 MΩ - internal feedback resistor

ESR maximum equivalent series resistance of crystal - given by crystal manufacturer (Ω)

f fundamental frequency of crystal (Hz)

XTI XT0

XTI

C2

OSCMODE

C1

- A = Cout.gm

Cin

Cout + Cin

Rf.Cin+

1Zin

-11Zo

+

- Zin = 1(2.π.f.Cout)2.ESR

23Intel Corporation

CE6353 Data Sheet

4.4.1.3 Calculating Crystal Power Dissipation

To calculate the power dissipated in a crystal the following equation can be used.

Equation 3 -

Pc = power dissipated in crystal at resonant frequency (W)

Vpp = maximum peak to peak output swing of amplifier is 1.8 V for all CVDD

Zin = crystal network impedance (see Equation 2)

4.4.1.4 Capacitor Values

Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated withEquation 4 below.

Equation 4 -

Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.

Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that theresulting crystal load capacitance CL (see Equation 5) is close to the crystal manufacturers recommended CL(standard values for CL are 15 pF, 20 pF and 30 pF). The crystal will then operate very near its specified frequency.

Equation 5 -

Cpar12 = parasitic capacitance between the XTI and XTO pins. It consists of the IC package’s pin-to-pincapacitance (including any socket used) and the printed circuit board’s track-to-track capacitance.

Cpar12 ≈ 2pF.

If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer’srecommended CL may be acceptable. Larger values of CL tend to reduce the influence of circuit variations andtolerances on frequency stability. Smaller values of CL tend to reduce startup time and crystal power dissipation.Care must however be taken that CL does not fall outside the crystal pulling range or the circuit may fail to start upaltogether. It is also possible to quote CL to the crystal manufacturer who can then cut a crystal to order which willresonate, under the specified load conditions, at the desired frequency.

Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this isnot feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gaincondition is still satisfied. This must be done using Equation 1.

Pc = 8.Zin

Vpp2

Cin = Cout = gmA

2Rf

1Zo

1(2.π.f)2.ESR when: C1 = C2 = Cout - Cpar

- - .

- CL = Cout . CinCout + Cin

+ Cpar12

Note: 2 >C2C1

> 0.5

24Intel Corporation

CE6353 Data Sheet

4.4.1.5 Oscillator/Clock Application Notes

• On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible. Other signal tracks must not be allowed to cross through this area. The component tracks should preferably be ringed by a ground track connected to the chip ground (0 V) on adjacent pins either side of the crystal pins. It is also advisable to provide a ground plane for the circuit to reduce noise.

• External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0V and CVDD) and current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the cell’s amplitude clamping circuit.

• An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To limit the current taken from the signal source a resistor should be placed between the clock source and XTI. The recommended value for this series resistor is 470 Ω for a clock signal switching between 0 V and CVDD. The current the clock source needs to source/sink is then <1.9 mA. The XTO pin must be left unconnected in this configuration.

• AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty cycle of the OSCOUT signal cannot be guaranteed in such a configuration.

• AC coupling of a single ended external clock to XTI, with OSCMODE = 1, is possible. It is recommended that the circuit shown in Figure 11 be used to correctly bias the oscillator inputs: The common-mode voltage VCM for XTI and XTO, (set by the 36 kΩ and 22 kΩ resistors) must be 800 mV < VCM < CVDD and the amplitude Vpp of the clock signal must be >100 mV.

Figure 11 - External Clocking via AC Coupling

• External, differential clock signals may be applied to XTI and XTO if OSCMODE = 1. The common-mode voltage VCM for the differential clock signals must be 800 mV < VCM < CVDD, and the peak-to-peak signal amplitude Vpp must be >100 mV. It is recommended that differential clock signals have VCM = 1.0V. For Vpp > 400 mV a resistor of >390 Ω in series with XTI or XTO may be required to limit the current taken from or supplied to the clock sources.

External clock10nF

XTI

100k

10nF 22k

36k

XTO Vdd OSCMODE

25Intel Corporation

CE6353 Data Sheet

26Intel Corporation

5.0 Application Circuit

Figure 12 - Typical Application Circuit

Preliminary PLL-SPLIT VIF/SIF

R2A10407SPPLL VIF/SIF TV Tuner

Rev2.0.3Aug.08.2006

DESCRIPTION

R2S10407SP is a semiconductor integrated circuit consisting of PLL split-carrier VIF/SIFsignal processing system compliant with PAL. Multi.

Features

*VIF frequency corresponds to 38.9MHz.*SIF frequency corresponds to M/N,B/G,I,D/K and SECAM L,L'.*Reference frequency is recommended 4.0MHz, and 4.433619MHz to Pin 15*Built-in SIF Trap and SIF band-pass Filter.*I2CBUS control.

Pin Arrangement

10

11

12

Audio / SIF Output

IF AGC FILTER1

R2A

10407SP

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

VIF IN1VIF IN2

PORTSIF MIX F/B

DE-EMPHASISAUDIO F/B

VIDEO OUTEQ F/B

GND

RF AGC DELAY

GNDSIF INAFC FILTERAFT OUTAPC FILTERVccSCLSDAIF AGC FILTER2REF.INPUTRF AGC OUTVCO F/B

Rev.2.0.3 Aug.08.2006 1

Block Diagram

Aud

io /

SIF

Out

put

IF A

GC

FIL

TER

1

SIF

MIX

F/B

DE

-EM

PH

AS

IS

1 2 3 4 5 6 7 8 10

20 19 18 17 16 15 14 13

1211

21222324

9

VIF

IN1

VIF

IN2

PO

RT

AU

DIO

F/B

VID

EO

OU

T

EQ

F/B

RF

AG

C D

ELA

Y

GN

D

GN

D

SIF

IN

AFC

FIL

TER

AFT

OU

T

AP

C F

ILTE

R

Vcc

SC

L

SD

A

IF A

GC

FIL

TER

2

RE

F.IN

PU

T

RF

AG

C O

UT

VC

O F

/B

VIDEODET

APC

TRAP

RFAGCAFT

Audio SIF

QIFAMP

BPF

LIM

SIFConv erter

INV SECAM-L

SECAM-L

FMDET

EQAMP

Sy ncSEPAFC

VIFAMP

VCO2

VIFAGC

VCO

QIF AGC

QIF DET

BUS Receiv er

AF AMPOthers

HORCD

Aud

io /

SIF

Out

put

IF A

GC

FIL

TER

1

SIF

MIX

F/B

DE

-EM

PH

AS

IS

1 2 3 4 5 6 7 8 10

20 19 18 17 16 15 14 13

1211

21222324

9

VIF

IN1

VIF

IN2

PO

RT

AU

DIO

F/B

VID

EO

OU

T

EQ

F/B

RF

AG

C D

ELA

Y

GN

D

GN

D

SIF

IN

AFC

FIL

TER

AFT

OU

T

AP

C F

ILTE

R

Vcc

SC

L

SD

A

IF A

GC

FIL

TER

2

RE

F.IN

PU

T

RF

AG

C O

UT

VC

O F

/B

VIDEODET

APC

TRAP

RFAGCAFT

Audio SIF

QIFAMP

BPF

LIM

SIFConv erter

INV SECAM-L

SECAM-L

FMDET

EQAMP

Sy ncSEPAFC

VIFAMP

VCO2

VIFAGC

VCO

QIF AGC

QIF DET

BUS Receiv er

AF AMPOthers

HORCD

Rev.2.0.3 Aug.08.2006 2

Absolute Maximum Ratings (25 oC, unless otherwise noted)Parameter Symbol Ratings Unit

Supply Voltage Vcc 6 V

PORT Output Voltage Vpmax 6 VPORT Input Current Ipmax 2.5 mAOperating Temperature Topr1 -20~75 oCStorage Temperature Tstg -40~125 oC

Thermal Derating (Maximum rating)

-20 728 4370 728 437

25 728 43775 437 43775 0 437150 0

Recommended Operating Condition (25 oC, unless otherwise noted)Pin No. Unit

19 V19 V15 MHzReference Frequency 4.00 or 4.433619

Supply Voltage 4.6~5.25Functional Supply Voltage 5.00

Parameter Recommended voltage

TBD

Conditions of this ratings.(1)70x70mm2 1.6mmt (1layer board)(2)Board material = Glass epoxy (FR-4)(3)Cupper share of board = 50%(4)Wind velocity = 0m/secIt changes with the material of mountingboard, the Cupper share, etc.

Total PowerDissipation

-

Pd mW

-

Note

Pin3Pin3

TBD

TBD

0

100

200

300

400

500

600

700

800

-25 0 25 50 75 100 125 150

Ambient Temperature Ta (oC)

Pow

er D

issi

patio

n Pd

(mW

)

Mounting in standard circuit board

Rev.2.0.3 Aug.08.2006 3

Application Circuit example

1 2 3 4 5 6 7 8 10

20 19 18 17 16 15 14 13

1211

21222324

RF A

GC

OU

T

0.01

uF

4MH

z

2.7K

0.01

uF

Video out

AFT

out

0.1u

F

47uF

Vcc1

Audio/SIF out

0.47

uF

SCL SD

A

9

POR

T1

VIF SAW

SIF SAW

0.01

uF

0.22

uF

0.22

uF56

1000

pF

0.1u

F

+

0.01

u

1u6.

8K

0.1u

F

Dig

ital G

ND

Anal

og G

ND

VIDEODET

APC

TRAP

RFAGCAFT

Audio SIF

QIFAMP

BPF

LIM

SIFConv erter

INV SECAM-L

SECAM-L

FMDET

EQAMP

Sy ncSEPAFC

VIFAMP

VCO2

VIFAGC

VCO

QIF AGC

QIF DET

BUS Receiv er

AF AMPOthers

HORCD

0.01

u

39K

30K

1 2 3 4 5 6 7 8 10

20 19 18 17 16 15 14 13

1211

21222324

RF A

GC

OU

T

0.01

uF

4MH

z

2.7K

0.01

uF

Video out

AFT

out

0.1u

F

47uF

Vcc1

Audio/SIF out

0.47

uF

SCL SD

A

9

POR

T1

VIF SAW

SIF SAW

0.01

uF

0.22

uF

0.22

uF56

1000

pF

0.22

uF56

1000

pF

0.1u

F

+

0.01

u

1u6.

8K

0.1u

F

Dig

ital G

ND

Anal

og G

ND

VIDEODET

APC

TRAP

RFAGCAFT

Audio SIF

QIFAMP

BPF

LIM

SIFConv erter

INV SECAM-L

SECAM-L

FMDET

EQAMP

Sy ncSEPAFC

VIFAMP

VCO2

VIFAGC

VCO

QIF AGC

QIF DET

BUS Receiv er

AF AMPOthers

HORCD

0.01

u

39K

30K

Rev.2.0.3 Aug.08.2006 4

Pin Function

Function Equivalent CircuitPinNo.

6

5

1

2

3

Pin Name

VIF Input1

VIF Input2

4

De-emphasis

SIF mixF/B

Port

Audio F/B

Port output terminal.The pull-up resistor is connected fromthe terminal with the power supply.Hi/Low of the output can be selectedby the I2C bus data. set the pull-upresistor value to the maximum inflowcurrent to become 2mA or less.

VIF input terminal.IF signal after SAW filter is input.It is a balance-type input.

Converter VCO Feedback terminal.The feedback control is to keep theinternal VCO of the uniform free-running frequency.

It is consist LPF with internal resistanceand attaching 0.01uF..That time constant is set by SIFfrequency.M/N ---75usecOthers ---50usecAt Secam L mode, it is activate SIFAGCfilter.

AF Bypass terminal. It is connected toone of the input of a differentialamplifier, external capacitor providesAC filtering. When resistor is connectedin series with capacitor, it is possible tolower the amplitude of the audio output.

1.2K

1.2K

1

19

2

24

1.2K

1.2K

11

1919

22

2424

3

19

9

33

1919

99

15K4

19

24

15K44

1919

2424

5

19

MOS SW

24

MOS SW

55

1919

MOS SW

2424

MOS SW

53.7K

53.7K

10.5K

10.5K

19

6

24

MOSSW

7p

53.7K

53.7K

10.5K

10.5K

1919

66

2424

MOSSW

7p

Rev.2.0.3 Aug.08.2006 5

Function

Ground terminal for Logic, Ref,Amplifierand input circuit.

IF AGC filter terminal 1.External capacitor affects AGC speed.

IF AGC filter terminal 2.Built-in 2.5K ohm, it is possible to dobletime constant.

10

7

11

16

Video Output

9

8

PinNo.

12

Audio/SIFOutput

EQ F/B

Digital GND

IF AGCFilter2

Equivalent Circuit

Video out terminal.

Equalizer feedback terminal.It is possible to change the ACresponse of the video signal byattaching L,C,R to this terminal.

Audio output and SIF output terminal.Select by I2C bus data.

RF AGC delay terminal.The RF AGC Delay point is possibleto change by the voltage of this pin.Internal voltageare selected by I2Cbus data. Refer to I2C BUS settingdata..

RF AGCDelay point

Pin Name

IF AGCFilter1

19

7

1mA

100

24

1919

7

1mA

100

2424

19

8

24

1919

8

2424

999

200

10

19

24

200

1010

1919

2424

11

19

MOS SW

24

1111

1919

MOS SW

2424

12

19

24

MOS SW

10K2.5K16

1212

1919

2424

MOS SW

10K2.5K1616

Rev.2.0.3 Aug.08.2006 6

Function Equivalent Circuit

SCL input terminal.

14

18

17

15

13

SDA

SCL

PinNo.

RF AGCOutput

VCO F/B

Pin Name

Ref SignalInput(ADS)

VIF VCO Feedback terminal.The feedback control is to keep theinternal VCO of the uniform free-running frequency.

SDA input terminal.Bus data protocol is conformed to I2CBUS. (400Kbps.)

RF AGC output terminalIt is current drive type.

It is possible to select external input orX'tal oscilator by the bus data. Whentheexternal input mode, Slave addressis select by the pull-down resistance of2.7K ohm.Resistornone: 42(1000010)pulldown:43

13

19

24

8K8K1313

1919

2424

8K8K

100

350uA

19

14

24

MOS SW

350uA100

350uA

1919

1414

2424

MOS SW

350uA

15

19

9

1K

1K 300

300

3p

1515

1919

99

1K

1K 300

300

3p

17

19

5K5K

ACK

9

1717

1919

5K5K

ACK

99

18

19

5K5K

9

1818

1919

5K5K

99

Rev.2.0.3 Aug.08.2006 7

Function

Power supply terminal

GND terminal.

AFC filter terminal.

SIF input terminal.SIF signal after SAW filter is input.

APC filter terminal.

AFT output terminal.Because of pulse-like signal output,Smoothing capacitor is connectedexternally. Output is muting at weakinput or un-lock status. Mute functionis selected by bus data.

Equivalent Circuit

20

19

24

PinNo.

23

21

22

Pin Name

Vcc

SIF Input

APC Filter

AFT Output

AFC Filter

Analog GND

191919

18K

18K20

19

24

18K

18K2020

1919

2424

21

19

24

350K

350K

2121

1919

2424

350K

350K

22

19

24

48K

6K

6K

2222

1919

2424

48K

6K

6K

2K

2K

23

19

24

2K

2K

2323

1919

2424

242424

Rev.2.0.3 Aug.08.2006 8

I2C BUS Setting Data

Bidirectional bus communication control can be performed. It consists of WRITE mode which receivesvarious data,and READ mode which transmits data. Recognition in WRITE mode and READ mode isperformed by specification of the last bit on Address Byte (R/W bit). When the setup of a R/W bit is "0", it is set as WRITE mode and, in the case of "1", is set as READ mode. Furthermore, it has the addressin which two programs are possible. It enables this to use two devices on the same I2 C bus.Moreover, two programmable addresses are possible. Therefore, two devices become usable on I2 C bus. A setup of an address is chosen by the voltage impressed to an address setting terminal (ADS:15 pin).If the address Byte in agreement is received, a data line will be set to "L" between knowledge, and at the time of WRITE mode, if Data Byte is received, SDA line between knowledge will be set to "L."

(1) WRITE mode The information of 3 bytes for circuit operation required for slave address, sub address and data byte.Three kind of data byte is selected by sub address.After the third byte is input, the setting of the bus data becomes effective.When the stop condition is input, before 3 byte input data on the way becomes invalid.

Timing Chart

Slave addressS6 S5 S4 S3 S2 S1 S0

Address 1 1 0 0 0 0 1 0Address 2 1 0 0 0 0 1 1*When using the X'tal oscillator of built-in, the slave address is only "Adress1".

Write mode data formatStart A A A Stop

R/W0

MSB LSBS6 S5 S4 S3 S2 S1 S0 R/W=0A7 A6 A5 A4 A3 A2 A1 A0B7 B6 B5 B4 B3 B2 B1 B0

Sub address MSB LSBA7 A6 A5 A4 A3 A2 A1 A0× × × × × 0 0 0× × × × × 0 0 1× × × × × 0 1 0× × × × × 0 1 1

Mode3Mode4

Mode2

14pin

Address Byte

Data ByteData

B7~B0

Address Byteslave address

S6~S0

Sub address ByteSub address

DC-openpull-down at 2.7Kohm

A7~A0

Sub address ByteData Byte

Mode1

Read into latch

address sub-address DATASDA

SCL

Rev.2.0.3 Aug.08.2006 9

Data ByteB7 B6 B5 B4 B3 B2 B1 B0 INITIAL

XTALOSC

REF443

SIFOUT24

FM GAINDOWN

POSMOD PORT1 - OVER

MOD0 1 0 0 0 0 0 1 41H

AFTMUTE_H

RF AGCBUS

1 1 0 0 1 1 0 0 CCH- AUDIO

OUTDE-

EMPHASISAUDIOMUTE

AGCSPD

0 0 1 1 1 1 0 1 3DH- - - - - - - -

0 0 0 0 0 0 0 0 00H

< Mode1 >Ref Signal Oscilator

B701

Ref Signal FrequencyB601

Pin10 Audio/SIF selectB501

Audio OUT GainB401

Video ModurationB301

PIN3 Port Output(Low Active)B201

Not UsedB10

Over Modulation FunctionB001

"1" is not allowed

Positive

OFFON

Mode4

4.433619MHz4.00MHz

AudioSIF

0dB-14dB

External

Mode2

Mode3

AFT MUTEFUNCTION

Mode1

RF AGC DELAY SET UP

SIF MODE SELECT

X'tal OSC

Negative

OFFON

Rev.2.0.3 Aug.08.2006 10

< Mode2 >AFT Mute Function Select

B7 B60 00 11 01 1

AFT Mute VoltageB501

RF AGC Delay Control SelectB401

RF AGC Delay AdjB3 B2 B1 B00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

When B4 of mode2 is "1" , RF AGC Delay point is possible to adjust by B3~B0 of mode2.

< Mode3 >SIF Mode Select

B7 B6 B50 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

Not UsedB41

5.74MHzSECAM L

"0" is not allowed

4.5MHz5.5MHz6.0MHz6.5MHz

+1+2+3

Sound Carrier Freq.

-3-2-10

-7-6-5-4

-11-10-9-8

Bus Data Control

RF AGC Delay Control

Delay Point-12

Mute ON Only Un-Lock statusMute ON Only week signal input

High(about Vcc)

Input Voltage of RF AGC Delay Pin11 Control

SECAM L'(reverse AFT)SECAM L'(not reverse AFT)

AFT Mute FunctionMute OFF

AFT Mute VoltageCenter (about 0.5*Vcc)

When Un-lock status or Dynamic AGC operation status,Mute ON.

Rev.2.0.3 Aug.08.2006 11

Audio OUTB301

De-emphasisB201

*Time constant is connected with SIF. ([email protected],[email protected]&6.0&6.5MHz,OFF@SECAM)

Audio Mute FunctionB101

IFAGC Speed Control FunctionB001

< Mode4 >Always input the following data

B7 B6 B5 B4 B3 B2 B1 B00 0 0 0 0 0 0 0

(2)READ ModeAt the time of READ mode, AFT output state is outputted to a master device.

( READ mode data format )Start A A Stop

R/W1

MSB LSBS6 S5 S4 S3 S2 S1 S0 R/W=1C7 C6 C5 C4 C3 C2 C1 C0

Data Byte

AFTC7 C6 C50 0 00 0 10 1 00 1 11 0 0

Not used

Address Byte Data Byte

OFF

OFFON

ON

fast

OFF

ON

slow

slave address dataS6~S0 C7~C0

Address ByteData Byte

AFT output0 to 0.2*Vcc

0.2*Vcc to 0.4*Vcc0.4*Vcc to 0.6*Vcc0.6*Vcc to 0.8*Vcc0.8*Vcc to 1.0*Vcc

C4~C0 not usedX -

Rev.2.0.3 Aug.08.2006 12

Electrical CharacteristicsGeneral (Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)

SWCondition Min Typ Max

1 Vcc Current Icc Pin19 - - B/G SW19=2 TBD 60 TBD 1

2 Ref. SignalInput Level Fref Pin15 Pin14

4MHzsinewave

- 50 200 400 mVpp

VIF Section <NTSC/PAL> (Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)


3 Video out1 Vodet TP7 Pin1,2 1 B/G 1.68 2.10 2.52 Vpp

4 Sync Tip level1 Vsync1 TP7 Pin1,2 1 B/G 1.0 1.35 1.7 V 2

5 Video S/N1 VoS/N1 TP7 Pin1,2 3 B/G 45 50 - dB 3

6 Input sensitivity1 VinMIN1 TP7 Pin1,2 4 B/G - 35 45 dBuV 4

7 Max.IF Input1 VinMAX1 TP7 Pin1,2 6 B/G 100 105 - dBuV 5

8 Capture range U1 CR-U1 TP7 Pin1,2 7 B/G TBD TBD - MHz 6

9 Capture range L1 CR-L1 TP7 Pin1,2 7 B/G TBD TBD - MHz 7

10 D/G DG TP7 Pin1,2 1 B/G - 2 5 %

11 D/P DP TP7 Pin1,2 1 B/G - 2 5 deg

12 Inter modulation IM TP7 Pin1,2 9 B/G 27 35 - dB 8

13 RF AGCHigh voltage RFagcH TP14 Pin1,2 10 B/G Vcc

-0.5Vcc-0.2 - V

14 RF AGCLow voltage RFagcL TP14 Pin1,2 11 B/G - 0.2 0.5 V

15 RF AGC delaypoint RFDP TP14 Pin1,2 12 B/G 85 90 95 dBuV 9

16 AFT Sensitivity μ TP21 Pin1,2 13 B/G 10 26 40 mV/KHz 10

17 AFT High voltage AFTH TP21 Pin1,2 14 B/G Vcc-0.5

Vcc-0.2 - V 10

18 AFT Low voltage AFTL TP21 Pin1,2 15 B/G - 0.2 0.5 V 10

19 AFT Mute voltage AFTM TP21 - - B/G Vcc/2-0.4 Vcc/2 Vcc/2

+0.4 V

20 AFT High-Mutevoltage AFTHM TP21 - - B/G Vcc

-0.5Vcc-0.2 - V

21 AFT Center voltage Vaft TP21 Pin1,2 3 B/G Vcc/2-0.45 Vcc/2 Vcc/2

+0.45 V

22Video out [email protected] (M/N)

VF40 TP7 Pin1,2 16 M/N -10 -5 -2 dB 11

23Video out [email protected] (M/N)

VF45 TP7 Pin1,2 16 M/N - -30 -25 dB 11

24Video out [email protected](B/G)

VF443 TP7 Pin1,2 16 B/G -5 0 5 dB 12

Note#Unit

Note#Unit

TestPoint

LimitsInputSignal

InputSignal

InputPoint

InputPoint

Limits

Mode

ModeTestPoint

No Parameter Symbol

No Parameter Symbol

Rev.2.0.3 Aug.08.2006 13



VF55 TP7 Pin1,2 16 B/G - -25 -20 dB 12


VF574 TP7 Pin1,2 16 B/G - -18 -13 dB 12

27Video out [email protected](I)

VF60 TP7 Pin1,2 16 I - -20 -15 dB 13

28Video out [email protected](D/K)

VF65 TP7 Pin1,2 16 D/K - -20 -15 dB 14

29 VIF VCO free runfrequency Fvcof TP21 - - B/G SW21=

2 -500 0 +500 KHz 15

VIF Section <SECAM-L> (Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)


30 Video out2 Vodet2 TP7 Pin1,2 2 L 1.68 2.10 2.52 Vpp

31 Sync Tip level2 Vsync2 TP7 Pin1,2 2 L 1.0 1.35 1.7 V 2

32 Input sensitivity2 VinMIN2 TP7 Pin1,2 5 L - 35 45 dBuV 4

33 Capture range U2 CR-U TP7 Pin1,2 8 L TBD TBD - MHz 6

34 Capture range L2 CR-L TP7 Pin1,2 8 L TBD TBD - MHz 7

SIF Section <NTSC/PAL> (Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)


35 AF output level(M/N) VoAF1 TP10 Pin1,2,

Pin23 17,3 M/N 0.6 1.0 1.4 Vpp

36 AF output level(B/G,I,D/K) VoAF2 TP10 Pin1,2,

Pin23 18,3 B/G, I,D/K 0.6 1.0 1.4 Vpp

37 AF output THD(M/N) THDAF1 TP10 Pin1,2,

Pin23 17,3 M/N - 0.5 1.0 %

38 AF output THD(B/G,I,D/K) THDAF2 TP10 Pin1,2,

Pin23 18,3 B/G, I,D/K - 0.5 1.0 %

39 Audio S/N (M/N) AF S/N1 TP10 Pin1,2,Pin23 19,3 M/N 54 60 - dB 16

40 Audio S/N(B/G,I,D/K) AF S/N2 TP10 Pin1,2,

Pin23 20,3 B/G, I,D/K 54 60 - dB 16

41 Limitingsensitivity (M/N) LIM1 TP10 Pin1,2,

Pin23 21,22,3 M/N - 20 30 dBuV 17

42Limitingsensitivity(B/G,I,D/K)

LIM2 TP10 Pin1,2,Pin23 23,24,3 B/G, I,

D/K - 20 30 dBuV 17

43 SIF output level(M/N) SIFG1 TP10 Pin1,2,

Pin23 19,3 M/N 100 105 110 dBuV 18

44 SIF output level(B/G,I,D/K) SIFG2 TP10 Pin1,2,

Pin23 20,3 B/G, I,D/K 100 105 110 dBuV 18

45 BPF frequency@+/- 300KHz BWBPF TBD Pin1,2,

Pin23 29,3 B/G SW14=2 - -20 -15 dB 19

UnitTestPoint

InputPoint

InputSignal Mode Note#Symbol

Note#Limits UnitTest

PointInput

SignalInputPoint

Limits

No Parameter

No Parameter

Symbol

Mode

Mode

Limits Unit Note#No Parameter Symbol TestPoint

InputPoint

InputSignal

Rev.2.0.3 Aug.08.2006 14

SIF Section <SECAM-L> (Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1) SW=1)


46 AF output DCvoltage AFDC TP10 Pin1,2,

Pin23 20,3 L TBD TBD TBD V 20

47 AF output level(L) VoAF3 TP10 Pin1,2,

Pin23 25,3 L 0.6 1.0 1.4 Vpp

48 AF output level(L') VoAF4 TP10 Pin1,2,

Pin23 27,28 L' 0.6 1.0 1.4 Vpp

49 AF output THD(L) THDAF3 TP10 Pin1,2,

Pin23 25,3 L - 0.5 1.0 %

50 AF output THD(L') THDAF4 TP10 Pin1,2,

Pin23 27,28 L' - 0.5 1.0 %

51 Video S/N (L) AFS/N3 TP10 Pin1,2,Pin23 20,3 L TBD TBD - dB 21

52 SIF Inputsensitivity (L) LIM3 TP10 Pin1,2,

Pin23 26,3 L - TBD TBD dBuV 22

53 SIF Max.IF Input SinMAX TP10 Pin1,2,Pin23 26,3 L TBD TBD - dBuV 23

Others (Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1)

Min Typ Max

54 PORT Output LowVoltage V PORTL TP3 - 0 - 0.4 V 24

55 PORT OutputLeak Current I PORTL TP3 - -10 - 10 μA 25

ModeLimitsTest

PointInputPoint

InputSignal

SW3=2Io2=2mA

No Parameter Symbol

No Parameter Symbol Note#TestPoint

Limits UnitInputPoint SW Condition

Unit Note#

Rev.2.0.3 Aug.08.2006 15

Data Entry Section (Unless Otherwise Specified : Ta=25 degree, Vcc=5.0V, Pin14, Vi=200mVp-p, SW=1) SW=1)

Min Typ Max

56 High Level InputVoltage ViH TP17

TP18 2.3 - Vcc V

57 Low Level InputVoltage ViL TP17

TP18 0 - 0.7 V

58 High Level InputCurrent IiH TP17

TP18 -10 - 10 μA

59 Low Level InputCurrent IiL TP17

TP18 -10 - 10 μA

60 Low Level OutputVoltage VoSL TP17 - - 0.4 V

61 SCL ClockFrequency fSCL TP18 0 - 440 KHz

62 Bus Free Time tBUF TP17 1300 - - nsec

63 Start Hold Time tHD STA TP17 600 - - nsec

64 SCL Low HoldTime t LOW TP18 1300 - - nsec

65 SCL High HoldTime t HIGH TP18 600 - - nsec

66 Start Setup Time tSU STA TP17TP18 600 - - nsec

67 Data Hold Time tHD DAT TP17TP18 0 - - nsec

68 Data Setup Time tSU DAT TP17TP18 100 - - nsec

69 Rise Time tR TP17TP18 - - 300 nsec

70 Fall Time tF TP17TP18 - - 300 nsec

71 Setup Time t SUSTO TP17TP18 600 - - nsec

Data Timing Chart

TestPointNo Parameter Symbol

Limits Unit Note#SW Condition

SW17=2 or SW18=2Vo=5.0V

SW17=2 or SW18=2Vo=0V

SW17=2 , SW17a=2Io3=3mA (Sync Current)

SDA

SCL

tLOW tR

tHDSTA tHDDAT tHIGH tSUDAT tSUSTA tSUSTO

tF tHDSTA

[STOP]condition

[START]condition

[START]condition

[STOP]condition

tBUF

Rev.2.0.3 Aug.08.2006 16

Test circuit

0.47

u

0.1u

0.01

u

51

0.01

u

VIFSignal

TP7

TP14

RefSignal

51

+

TP10

0.01

u

0.1u

SW17a

Vcc

0.01

u

0.1u

2 1

A

+

+

0.01

u 1u6.

8K

0.22

u

2 1

SW20

Vcc

0.1u

TP21

2 1

A

SW19

+

56

2 151

0.01

u

Vcc

TP3

SW

31

4.7K

2Io

2=2m

A

Vcc

TP12

+1 2

V12

TP17 0.01

u

SDA

1 2

SW18 SW17

12

Io3=3mA Vo

A

1

I2C BUS

1

1

A

1

47u

TP18SCL

2 SW15

2.7K

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

VIDEODET

APC

TRAP

RFAGCAFT

Audio SIF

QIFAMP

BPF

LIM

SIFConv erter

INV SECAM-L

SECAM-L

FMDET

EQAMP

Sy ncSEPAFC

VIFAMP

VCO2

VIFAGC

VCO

QIF AGC

QIF DET

BUS Receiv er

AF AMPOthers

HORCD

0.47

u

0.1u

0.01

u

51

0.01

u

VIFSignal

TP7

TP14

RefSignal

51

+

TP10

0.01

u

0.1u

SW17a

Vcc

0.01

u

0.1u

2 1

A

+

+

0.01

u 1u6.

8K

0.22

u

2 1

SW20

Vcc

0.1u

TP21

2 1

A

SW19

+

56

2 151

0.01

u

Vcc

TP3

SW

31

4.7K

2Io

2=2m

A

Vcc

TP12

+1 2

V12

TP17 0.01

u

SDA

1 2

SW18 SW17

12

Io3=3mA Vo

A

1

I2C BUS

1

1

A

1

47u

TP18SCL

2 SW15

2.7K

2.7K

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

VIDEODET

APC

TRAP

RFAGCAFT

Audio SIF

QIFAMP

BPF

LIM

SIFConv erter

INV SECAM-L

SECAM-L

FMDET

EQAMP

Sy ncSEPAFC

VIFAMP

VCO2

VIFAGC

VCO

QIF AGC

QIF DET

BUS Receiv er

AF AMPOthers

HORCD

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

VIDEODET

APC

TRAP

RFAGCAFT

Audio SIF

QIFAMP

BPF

LIM

SIFConv erter

INV SECAM-L

SECAM-L

FMDET

EQAMP

Sy ncSEPAFC

VIFAMP

VCO2

VIFAGC

VCO

QIF AGC

QIF DET

BUS Receiv er

AF AMPOthers

HORCD

Rev.2.0.3 Aug.08.2006 17

Input SignalSG

fo=38.9MHz Sync Tip Level=90dBuV B/G systemNegative 90% TV modulation 10 step waveformfo=38.9MHz White Peak Level=90dBuV L systemPositive 95% TV modulation 10 step waveform

3 fo=38.9MHz Vi=Variable CWfo=38.9MHz Sync Tip Level=Variable B/G systemNegative 90% TV modulation 10 step waveformfo=38.9MHz White Peak Level=Variable L systemPositive 95% TV modulation 10 step waveform

6 fo=38.9MHz Vi=Variable fm=20KHz AM=16.0%fo=Freq. Variable Sync Tip Level=90dBuV B/G systemNegative 90% TV modulation 10 step waveformfo=Freq. Variable White Peak Level=90dBuV L systemPositive 95% TV modulation 10 step waveformf1=38.9MHz Vi=90dBuV CWf2=34.47MHz Vi=80dBuV CWfo=33.4MHz Vi=80dBuV CW

10 fo=38.9MHz Vi=70dBuV CW11 fo=38.9MHz Vi=110dBuV CW12 fo=38.9MHz Vi=Variable CW13 fo=Freq. Variable Vi=90dBuV CW14 fo=38.9MHz-0.5MHz Vi=90dBuV CW15 fo=38.9MHz+0.5MHz Vi=90dBuV CW

f1=38.9MHz Vi=90dBuV CWf2=Freq. Variable Vi=80dBuV CW

17 fo=34.4MHz Vi=80dBuV fm=1KHz +/- 25KHz dev18 fo=33.4(32.9, 32.4)MHz Vi=80dBuV fm=1KHz +/- 50KHz dev19 fo=34.4MHz Vi=80dBuV CW20 fo=33.4(32.9, 32.4)MHz Vi=80dBuV CW21 fo=34.4MHz Vi=Variable fm=1KHz +/- 25KHz dev22 fo=34.4MHz Vi=Variable CW23 fo=33.4(32.9, 32.4)MHz Vi=Variable fm=1KHz +/- 50KHz dev24 fo=33.4(32.9, 32.4)MHz Vi=Variable CW25 fo=32.4MHz Vi=80dBuV fm=1KHz AM=54%26 fo=32.4MHz Vi=Variable fm=1KHz AM=54%27 fo=33.9MHz Vi=90dBuV CW28 fo=40.4MHz Vi=80dBuV fm=1KHz AM=54%29 f0=33.4±0.3MHz Vi=80dBuV CW

16 Mixed signal

9 Mixed signal

5

7

8

Termination with 50 ohm

1

2

4

Rev.2.0.3 Aug.08.2006 18

Note*VIF,SIF Input frequency

*Out put SIF frequency, Note It isn't limiting in the band inside the IC.

VIF IN SIF IN

D/K (6.5MHz) 38.9MHz 32.4MHz

MODE

32.9MHzI (6.0MHz)

M/N (4.5MHz)B/G (5.5MHz)

SECAM L'38.9MHzSECAM L 32.4MHz38.9MHz

ID/K

frequency4.5MHz5.5MHz6.0MHz

Audio systemM/NB/G

34.4MHz33.4MHz

38.9MHz

6.5MHz

38.9MHz

40.4MHz

38.9MHz

Note

It isn't limiting inthe band inside

the IC.

Rev.2.0.3 Aug.08.2006 19

Note

Note1 Vcc Current:Icc1. Set SIF mode to B/G(5.5MHz).2. Measure the current that flow into Vcc(Pin19).

This current is named Vcc Current.

Note2 Sync Tip Voltage : Vsync1, Vsync21 Input SG1@B/G or SG2@SECAM-L to VIF IN(Pin1,Pin2).2 The Vsync1 and Vsync2 are the minimum DC level of the output waveform

defined Video output(TP7).

Note3 Video S/N:VoS/N11. Input SG3 to VIF IN (Pin1,Pin2) and measure the Video Output (TP7) noise in r.m.s.

through a 5MHz (-3dB) L.P.F.2. The Video S/N is calculated by following.

Vo S/N=20xlog (dB)

Note4 Input sensitivity : Vin MIN1,VinMIN21. Input SG4@B/G or SG5@SECAM-L to VIF IN(Pin1,Pin2), and then gradually

reduce Vi and measure the input level when the 20KHz component of Video Output (TP7), reaches -3dBuV from Vodet level.

2. This input level is named Input sensitibity.

Note5 Maximum allowable input : VinMAX11. Input SG6 (Vi=90dBu) to VIF IN(Pin1,Pin2) , and measure the level of the 20KHz

component of Video Output(TP7).2. Gradually increase the Vi of SG6 and measure the input level

when the output reaches -3dB.3. This input level is named Maximum allowable input.

0.7 X VodetNOISE

(Vpp)(rms)

Vsync1(Vsync2)

TP7

0V

Rev.2.0.3 Aug.08.2006 20

Note6 Capture range U : CR-U1, CR-U21. Input SG7@B/G or SG8@SECAM-L to VIF IN(Pin1,Pin2),and then

Increase the frequency of SG7 or SG8 until the VCO is out of locked-oscillation.2. And decrease the frequency of SG7(SG8) and measure the frequency fU

when the VCO is locked.3. The Capture range U is calculated by following.

CR-U1 = fU-38.9CR-U2 = fU-38.9

Note7 Capture range L : CR-L1, CR-L21. Input SG7@B/G or SG8@SECAM-L to VIF IN(Pin1,Pin2),and then

decrease the frequency of SG7 or SG8 until the VCO is out of locked-oscillation.2. And increase the frequency of SG7(SG8) and measure the frequency fL

when the VCO is locked.3. The Capture range L is calculated by following.

CR-L1 = 38.9-fLCR-L2 = 38.9-fL

Note8 Inter modulation : IM1. Set SIF IN(Pin23) to 5.5MHz.(I2C BUS : Mode3 B7=0,B6=0,B5=1)2. Input SG9 to VIF IN(Pin1,Pin2),and measure Video Output (TP7) with an oscilloscope.3. Set SW12 to 2,and then adjust V12 so that the minimum DC level of the output

waveform is Vsync1.4. Measure TP7 with a spectrum analyzer. The inter modulation is defined as a difference

between 1.07MHz and 4.43MHz frequency components.

Note9 RF AGC delay point : RFDP1. Input SG12 to VIF IN(Pin1,Pin2) and gradually reduce level and then measure2. the input level when RF AGC Output(TP14) reaches 1/2Vcc, as shown below.

This level is named RF AGC delay point.3. AT that time, the set point of RE AGC (I2C BUS) is initial state.

(MHz)

(MHz)

TP14Volt.

SG12 Level(dBuV)RFDP

RFagcLRFagcH

1/2Vcc

Rev.2.0.3 Aug.08.2006 21

Note10 AFT sensitivity : μ , Maximum AFT voltage:AFTH, Minimum AFT voltage:AFTL1. Input SG13 to VIF IN(Pin1,Pin2), and set the frequency of SG13 so that the voltage of

AFT Output (TP21) is 3 volt. This frequency is named f(3).2. Set the frequency of SG13 so that the AFT Output voltage is 2 volt.

This frequency is named f(2).3. The AFT sensitivity is calculated by following.

μ= (mV/KHz)

4. IN the graph shown below, maximum and minimum DC voltage are AFTH and AFTL, respectively.

Note11 Video out Freq. Respons M/N (4.0MHz,4.5MHz) : VF40,VF451. Set SIF mode select to 4.5MHz.(I2C BUS : Mode3 B7=0,B6=0,B5=0)2. Measure the 1MHz level of Video Output (TP7) with a spectrum analyzer

when SG16 (f2=37.9MHz) is input to VIF IN(Pin1,Pin2). This level is named F(1.0M).At that time, measure the voltage at TP11, and then fix V11 at that voltage.(SW12=2)

3. SG16(f2=34.9MHz),measure the level t of 4.0MHz of Video Output (TP7).This level is named F(4.0M).

4. SG16(f2=34.4MHz),measure the level of 4.5MHz of Video Output (TP7).This level is named F(4.5M).

5. The Video out Freq. Respons @4.0MHz(M/N),and Video out Freq. Respons @4.5MHz(M/N) is calculated by following.

VF40 = F(4.0M) - F(1.0M) (dB)VF45 = F(4.5M) - F(1.0M) (dB)

1000f(2) - f(3)

(mV)(KHz)

TP7F(1.0M)F(4.0M)

F(4.5M)

1.0 4.0 4.5(MHz)

VF40 VF45

TP21Volt.

f(MHz)

AFTH

AFTL

3V

2V

f(3) f(2)

Rev.2.0.3 Aug.08.2006 22

Note12 Video out Freq. Respons B/G (4.43MHz,5.5MHz,5.74MHz) : VF443,VF55,VF5741. Set SIF mode select to 5.5MHz.(I2C BUS : Mode3 B7=0,B6=0,B5=1)2. Measure the 1MHz level of Video Output (TP7) with a spectrum analyzer





6. The Video out Freq. Respons @4.43MHz (B/G), Video out Freq. Respons @5.5MHz (B/G) and Video out Freq. Respons @5.74 (B/G) is calculated by following.

VF443 = F(4.43M) - F(1.0M) (dB)VF55 = F(5.5M) - F(1.0M) (dB)VF574 = F(5.74M) - F(1.0M) (dB)

Note13 Video out Freq. Respons I (6.0MHz) : VF601. Set SIF mode select to 6.0MHz.(I2C BUS : Mode3 B7=0,B6=1,B5=0)2. Measure the 1MHz level of Video Output (TP7) with a spectrum analyzer


3. Adjust SG16(f2=32.9MHz),measure the level of 6.0MHz of Video Output (TP7).This level is named F(6.0M).

4. The Video out Freq. Respons @6.0MHz (I) is calculated by following.

VF60 = F(6.0M) - F(1.0M) (dB)

TP7

F(1.0M)F(4.43M)

F(5.5M)

1.0 5.5 (MHz)

VF55 VF574

4.43 5.74

F(5.74M)

VF443

VF60

TP7

F(1.0M)

F(6.0M)

1.0 6.0 (MHz)

Rev.2.0.3 Aug.08.2006 23

Note14 Video out Freq. Respons D/K (6.5MHz) : VF651. Set SIF mode to 6.5MHz.2. Measure the 1MHz level of Video Output (TP7) with a spectrum analyzer



4. The Video out Freq. Respons @6.5MHz (D/K) is calculated by following.

VF65 = F(6.5M) - F(1.0M) (dB)

Note15 VIF VCO freerun freq. : Fvcof1. Input the following the bus data, and makes the free run measurement mode.

2. Set SW21 to 2, measure the freq. Output to TP21. This freq is named Faft.3. VCO free run freq is calculated by following.

In the case of standard signal frequency = 4.00MHzFvcof = Faft (MHz) - 4.00 (MHz) * 2 * 1000 [KHz]

In the case of standard signal frequency = 4.433619MHzFvcof = Faft (MHz) - 4.433619 (MHz) * 2 * 1000 [KHz]

4. Do apower once in off the free run measurement comletes.or input the following the bus data, and cancels the free run measurement mode.

Sub address ByteData Byte 0

XX X00 0 0 0

0 1

0 0

XX

Data Byte

1 0Address Byte

0 0

0 01

1 0 0 0

0 10X

1 10 0

Sub address Byte00 0 1 X1 0 0Address Byte

X X X X 0X

TP7

F(1.0M)

F(6.5M)

1.0 6.5 (MHz)

VF65

Rev.2.0.3 Aug.08.2006 24

Note16 Audio S/N: AF S/N1, AF S/N21. Set De-emphasis to 75us@M/N or 50us@B/G(SUB),I,D/K.2. Input SG3 to VIF IN(Pin1,Pin2), SG19@M/N or SG20`B/G(SUB),I,D/K

to SIF IN(Pin23), and measure the output noise level of Audio Output (TP10) with FLAT-r.m.s. This level is named Vn1(Vn2).

3. The Audio S/N(AF S/N1,AF S/N2) is calculated by following.

AF S/N1=20xlog (dB)

AF S/N1=20xlog (dB)

Note17 Limiting sensitivity : LIM1, LIN21. Set De-emphasis to 75use@M/N or 50us@B/G(SUB),I,D/K. 2. Input SG3 to VIF IN(Pin1,Pin2).3. Input SG21@M/N or SG23@B/G(SUB),I,D/K to SIF IN(Pin23),

and measure the 1KHz component level of Audio Output(TP10) with FLAT-r.m.s.4. Input SG22@M/N or SG24@B/G(SUB),I,D/K to SIF IN(Pin23),

and measure the 1KHz component level of Audio Output(TP10) with FLAT-r.m.s.5. The Limiting sensitivity(LIM1,LIM2) is defined as the input level when the difference

between each 1KHz components of Audio Output (TP10) is 30dB,respectively, as shown below.

Note18 SIF output level : SIFG1, SIFG21. Input SG3 to VIF IN(Pin1,Pin2), and SG19@M/N or SG20@B/G(SUB),I,D/K

to SIF IN(Pin23), and measure the 4.5~ 6.5MHz component level of TP10.2. Attention, at this time, the SIF signal must not pass internal BPF.

VoAF1Vn1

(mVrms)(mVrms)

TP10(rms)

SIF IN(dBuV)LIM1(LIM2)

TP10 while SG21 (SG23) is input.

TP10 while SG22(SG24) is input.

30dB

VoAF1Vn1

(mVrms)(mVrms)

Rev.2.0.3 Aug.08.2006 25

Note19 BPF Freq. Respons @ +/-300KHz : BWBPF1. Set SIF mode to B/G.2. Input the BUS of follwing, so that set to the mode measures BPF Freq.

3. Input SG3 to VIF IN(Pin1,Pin2), SG29 to SIF IN(Pin23) ,and then measure the 600(+/-300)KHz component of TP14 .

4. Do apower once in off the BPF frequency response measurement comletes.or input the following the bus data, and cancels the BPF frequency response measurement mode.

Note 20 Audio output DC voltage : AFDC1. Set SIF mode to SECAM-L.2. Input SG3 to VIF IN(Pin1,Pin2), SG20(f0=32.4MHz) to SIF IN(Pin23) .3. Measure the DC voltage of Audio output(TP10) .

Note 21 Audio S/N (L) : AFS/N31. Set SIF mode to SECAM-L.2. Input SG3 to VIF IN(Pin1,Pin2), SG20(f0=32.4) to SIF IN(Pin23).3. Measure the output noise level of Audio Output (TP10) with FLAT-r.m.s.

This level is named Vn3.4. The Audio S/N(L) is calculated by following.

AF S/N3 = 20log (dB)

X X X XData Byte

Address ByteSub address Byte

00 0 1 X1 0 0

0

Address ByteSub address Byte

Data Byte0 0

0 1 0 0 1 0 0

1 X 0X X X X X 1

0 0 0 01

0 0 0 0 11 0 00 0 0

X

600

BWBPF

f0 (KHz)900300

TP14VF0

V300

VoAF3Vn3

(mVrms)(mVrms)

Rev.2.0.3 Aug.08.2006 26

Note22 SIF Input sensitivity (L) : LIM31. Set SIF mode to SECAM-L.2. Input SG3 to VIF IN(Pin1,Pin2) , SG26(Vi=80dBuV) to SIF IN(Pin23) ,

and then gradually reduce Vi and measure the input level when the 1KHz component of Audio Output (TP10), reaches -3dBuV from VoAF3 level.

3. This input level is named SIF input sensitibity(L).

Note23 SIF Maximum allowable input : SinMAX1. Set SIF mode SECAM-L.2. Input SG3 to VIF IN(Pin1,Pin2) , SG26(Vi=80dBuV) to SIF IN(Pin23) ,

and then gradually increase Vi and measure the input level when the 1KHz component of Audio Output (TP10), reaches -3dBuV from VoAF3 level.

3. This input level is named SIF maximum allowable input.

Note24 Port output low voltage : VPROTL1. Set PORT Out be on. (I2C BUS : Model1 B2=1)2. Set SW3 to 2 so that Io1=2mA, and measure the output level of TP3.

This is named PORT Output Low Voltage

Rev.2.0.3 Aug.08.2006 27

EC9410 2A 380KHZ 20V PWM Buck DC/DC Converter

E-CMOS Corp. (www.ecmos.com.tw) Page 1 of 10 2007/04/10

General Description The EC9410 is a 380 KHz fixed frequency monolithic step down switch mode regulator with a built in internal Power MOSFET. It achieves 2A continuous output current over a wide input supply range with excellent load and line regulation. The device includes a voltage reference, oscillation circuit, error amplifier, internal PMOS and etc. The PWM control circuit is able to adjust the duty ratio linearly from 0 to 100%. An enable function, an over current protection function and a short c ircui t protection function are built inside. An internal compensation block is built in to minimize external component count. The EC9410 serves as ideal power supply units for portable devices. Function Block

Features 2A Constant Output Current 140mΩ RDSON Internal Power PMOSFET

Switch Up to 95% Efficiency Fixed 380KHz Frequency Wide 3.6V to 20V Input Voltage Range Output Adjustable from 1.222V to 18V Built in Frequency Compensation Built in Thermal Shutdown Function Built in Current Limit Function SOP8 Package is Available The minimum dropout up to 0.3V

Applications

Portable DVD

LCD Monitor / TV

Battery Charger

ADSL Modem

Telecom / Networking Equipment



Pin Assignments

Pin Number Pin Name Description

1,6,8 NC Not Connect

2 Vin

Supply Voltage Input Pin. EC9410 operates from a 3.6V to 20VDC voltage. Bypass Vin to GND with a suitably large capacitor to eliminate noise on the input.

3 SW Power Switch Output Pin. SW is the switch node that supplies power to the output.

4 GND

Ground Pin. Care must be taken in layout. This pin should be placed outside of the Schottky Diode to output capacitor ground path to prevent switching current spikes from inducing voltage noise into EC9410.

5 FB

Feedback Pin. Through an external resistor divider network, FB senses the output voltage and regulates it. The feedback threshold voltage is 1.222V.

7 EN

Enable Pin. EN is a digital input that turns the regulator on or off .Drive EN pin high to turn on the regulator, drive it low to turn it off.

Ordering/ Marking Information

Package type Part Number Marking Marking Information

SOP8 EC9410N-F EC9410-F

YYWW XXXXXXXX

F is Lead free package YY is the year of production. 06 means the

product is manufactured in year of 2006. WW is the week of production. 25 means the

product is manufactured in the 25th week. XXXXXXXX is Lot number.

EC9410 N - F

Package: N = SOP8

Circuit TypeF: Lead-Free

Pin Description



Absolute Maximum Ratings

Parameter Symbol Value Unit Input Voltage VIN -0.3 to 20 V

Feedback Pin Voltage VFB -0.3 to Vin V

Enable Pin Voltage VEN -0.3 to 12 V

Switch Pin Voltage VSW -0.3 to Vin V

Power Dissipation PD Internally limited mW

Operating Junction Temperature TJ 150 ºC

Storage Temperature TSTG -65 to 150 ºC

Lead Temperature (Soldering, 10 sec) TLead 260 ºC

ESD (HBM) VESD 2000 V

Note1: Stresses greater than those listed under Maximum Ratings may cause permanent damage

to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended Operating Conditions


Input Voltage VIN 3.6 20 V

Operating Junction temperature TJ -40 125 ºC

Operating Ambient Temperature TA -40 85 ºC



Electrical Characteristics VCC = 12V, Ta = 25 unless other wise specified.

Parameters Symbol Test Condition Min. Typ. Max. Unit

Input voltage VIN - 3.6 - 20 V

Shutdown Supply Current ISTBY VEN=0V - 30 90 uA

Supply Current ICC VEN=2V, VFB=1.3V - 3.6 4 mA

Feedback Voltage VFB VIN = 3.6V to 23V 1.21 1.222 1.26 V

Feedback Bias Current IFB VFB=1.3V - 0.1 0.5 uA

Switch Current Limit ILIM - - 3 4 A

Oscillator Frequency

FOSC -

320

380

440

KHz

Frequency of Current Limit or Short Circuit Protection

FOSC1 VFB=0V - 42 - KHz

EN Pin Threshold

VEN -

0.7

1.2

1.7

V

IH VEN=2.5V - -0.1 -1 uA EN Pin Input Leakage Current

IL VEN=0.5V - -3 -10 uA

Internal PMOS RDSON RDSON

VIN≤=12V,VFB=0V VEN=12V, Iout=2A -

140 - mΩ

Max. Duty Cycle DMAX VFB=0V, ISW=0.1A - 100 - %

Efficiency

η

VIN=12V,Vout=5V Iout=2A

-

92

-

%

Thermal Shutdown TOTSD - - 165 - ºC



Typical Performance Characteristics

Switching Frequency vs. Temperature VFB vs. Temperature

Icc vs. Temperature Efficiency vs. Load (Vin=10V)



Typical Application Circuit

Typical Application Circuit @ 5V/2A

Typical Application Circuit @ 3.3V/2A

EC9410

EC9410



Typical Application Circuit (Continued) Typical Application Circuit (with ceramic output capacitor) @ 5V/2A Typical Application Circuit (with ceramic output capacitor) @ 3.3V/2A

EC9410

EC9410



Schottky Rectifier Selection Guide

EC9410 Lists some rectifier manufacturers.

2A Load Current Vin (Max) Part Number Vendor

B220 Diodes, Inc.

SK23 Pan Jit International 20V

SR22 Pan Jit International Output Voltage VS R1, R2 Resistor Selection Guide (Vout = (1+R1/R2)*1.222V)

EC9410 Vout VS. R1, R2 Select Table

Vout R1 R2

1.8V 3.9K 8.2K

2.5V 3.2K 3K

3.3V 6.2K 3.6K

5V 6.2K 2K

9V 13K 2K

12V 16K 1.8K



Function Description VIN This is the positive input supply for the IC switching regulator. A suitable input bypass capacitor must be present at this pin to minimize voltage transients and to supply the switching currents needed by the regulator Gnd Circuit ground. SW Internal switch. The voltage at this pin switches between (VIN – VGS) and approximately – 0.5V, with a duty cycle of approximately VOUT / VIN. To minimize coupling to sensitive circuitry, the PC board copper area connected to this pin should be kept a minimum. FB Senses the regulated output voltage to complete the feedback loop. EN Allows the switching regulator circuit to be shutdown using logic level signals thus dropping the total input supply current to approximately 30uA. Pulling this pin below a threshold voltage of approximately 0.7 V turns the regulator down, and pulling this pin above 1.3V (up to a maximum of 12V) shuts the regulator on. For automatic starup condition, can be implemented by the addition of a resistive voltage divider from VIN to GND. Thermal Considerations The SOP8 package needs a heat sink under most conditions. The size of the heat sink depends on the input voltage, the output voltage, the load current and the ambient temperature. The EC9410 junction temperature rises above ambient temperature for a 2A load and different input and output voltages. The data for these curves was taken with the EC9410 (SOP8 package) operating as a buck-switching regulator in an ambient temperature of 25 ºC (still air). These temperature rise numbers are all approximate and there are many factors that can affect these temperatures. Higher ambient temperatures require more heat sinking. For the best thermal performance, wide copper traces and generous amounts of printed circuit board copper should be used in the board layout.(Once exception to this is the output (switch) pin, which should not have large areas of copper.) Large areas of copper provide the best transfer of heat (lower thermal resistance) to the surrounding air, and moving air lowers the thermal resistance even further. Package thermal resistance and junction temperature rise numbers are all approximate, and there are many factors that will affect these numbers. Some of these factors include board size, shape, thickness, position, location, andeven board temperature. Other factors are, trace width, total printed circuit copper area, copper thickness, single or double-sided, multi-layer board and the amount of solder on the board. The effectiveness of the PC board to dissipate heat also depends on the size, quantity and spacing of other components on the board, as well as whether the surrounding air is still or moving. Furthermore, some of these components such as the catch diode will add heat to the PC board and the heat can vary as the input voltage changes. For the inductor, depending on the physical size, type of core material and the DC resistance, it could either act as a heat sink taking heat away from the board, or it could add heat to the board.



OUTLINE DRAWING FOR SOP-8

EC9483 EC9483

3A 380KHZ 28V PWM Buck DC/DC Converter


General Description

The EC9483 is a 380 KHz fixed frequency monolithic step down switch mode regulator with a built in internal Power MOSFET. It achieves 3A continuous output current over a wide input supply range with excellent load and line regulation. The device includes a voltage reference, oscillation circuit, error amplifier, internal PMOS and etc. The PWM control circuit is able to adjust the duty ratio linearly from 0 to 100%. An enable function, an over current protection function and a short c ircui t protection function are built inside. An internal compensation block is built in to minimize external component count. The EC9483 serves as ideal power supply units for portable devices.

Function Block

Features 3A Constant Output Current 140mΩ RDSON Internal Power PMOSFET

Switch Up to 95% Efficiency Fixed 380KHz Frequency Wide 3.6V to 28V Input Voltage Range Output Adjustable from 1.222V to 26V Built in Frequency Compensation Built in Thermal Shutdown Function Built in Current Limit Function SOP8 Package is Available The minimum dropout up to 0.3V

Applications

Portable DVD LCD Monitor / TV Battery Charger ADSL Modem Telecom / Networking Equipment

EC9483 EC9483



Pin Assignments

Pin Number Pin Name Description

1,6,8 NC Not Connect

2 Vin

Supply Voltage Input Pin. EC9483 operates from a 3.6V to 28V DC voltage. Bypass Vin to GND with a suitably large capacitor to eliminate noise on the input.

3 SW Power Switch Output Pin. SW is the switch node that supplies power to the output.

4 GND

Ground Pin. Care must be taken in layout. This pin should be placed outside of the Schottky Diode to output capacitor ground path to prevent switching current spikes from inducing voltage noise into EC9483.

5 FB

Feedback Pin. Through an external resistor divider network, FB senses the output voltage and regulates it. The feedback threshold voltage is 1.222V.

7 EN

Enable Pin. EN is a digital input that turns the regulator on or off. Drive EN pin high to turn on the device, drive it low to turn it off.

Package type Part Number Marking Marking Information

SOP8 EC9483N-F

EC9483-F

YYWW XXXXXXXX

F is Lead free package. YY is the year of production. 06 means the

product is manufactured in year of 2006. WW is the week of production. 25 means the

product is manufactured in the 25th week. XXXXXXXX is Lot number.

EC9483 N - F

Package: N = SOP8

C ircuit Type F: Lead-Free

Ordering/ Marking Information

Pin Description

EC9483 EC9483



Absolute Maximum Ratings

Parameter Symbol Value Unit Input Voltage VIN -0.3 to 28 V

Feedback Pin Voltage VFB -0.3 to Vin V

Enable Pin Voltage VEN -0.3 to 12 V

Switch Pin Voltage VSW -0.3 to Vin V

Power Dissipation PD Internally limited mW

Operating Junction Temperature TJ 150 ºC

Storage Temperature TSTG -65 to 150 ºC

Lead Temperature (Soldering, 10 sec) TLEAD 260 ºC

ESD (HBM) VESD 2000 V

Note1: Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended Operating Conditions


Input Voltage VIN 3.6 28 V

Operating Junction temperature TJ -40 125 ºC

Operating Ambient Temperature TA -40 85 ºC

EC9483 EC9483



Electrical Characteristics VCC = 12V, Ta = 25 unless other wise specified.

Parameters Symbol Test Condition Min. Typ. Max. Unit

Input voltage VIN - 3.6 - 28 V

Shutdown Supply Current ISTBY VEN=0V - 30 90 Ua

Supply Current ICC VEN=2V, VFB=1.3V - 3.6 4 mA

Feedback Voltage VFB VIN = 3.6V to 23V 1.21 1.222 1.26 V

Feedback Bias Current IFB VFB=1.3V - 0.1 0.5 uA

Switch Current Limit ILIM - - 4 5 A

Oscillator Frequency

FOSC -

320

380

440

KHz

Frequency of Current Limit or Short Circuit Protection

FOSC1

VFB=0V - 42 - KHz

EN Pin Threshold

VEN -

0.7

1.2

1.7

V

IH VEN=2.5V - -0.1 -1 uA EN Pin Input Leakage Current

IL VEN=0.5V - -3 -10 uA

Internal PMOS RDSON RDSON

VIN≤=12V,VFB=0V VEN=12V, Iout=3A - 80 - mΩ

Max. Duty Cycle DMAX VFB=0V, ISW=0.1A - 100 - %

Efficiency

η

VIN=12V,Vout=5V Iout=3A

-

92

-

%

Thermal Shutdown TOTSD - - 165 - ºC

EC9483 EC9483




Switching Frequency vs. Temperature VFB vs. Temperature

Icc vs. Temperature Efficiency vs. Load (Vin=10V)

EC9483 EC9483



Typical Application Circuit

Typical Application Circuit @ 5V/3A

Typical Application Circuit @ 3.3V/3A

EC9483

EC9483

EC9483 EC9483



Typical Application Circuit (Continued) Typical Application Circuit (with ceramic output capacitor) @ 5V/3A Typical Application Circuit (with ceramic output capacitor) @ 3.3V/3A

EC9483

EC9483

EC9483 EC9483



Schottky Rectifier Selection Guide EC9483 Lists some rectifier manufacturers.

3A Load Current Vin (Max)

Part Number Vendor

B320 Diodes, Inc.

SK33 Diodes, Inc. 20V

SS32 General Semiconductor

B330 Diodes, Inc.

B340L Diodes, Inc.

MBRD330 On Semiconductor

SK33 Diodes, Inc.

30V

SS33 General Semiconductor Output Voltage VS R1, R2 Resistor Selection Guide (Vout = (1+R1/R2)*1.222V)

EC9483 Vout VS. R1, R2 Select Table

Vout R1 R2

1.8V 3.9K 8.2K

2.5V 3.2K 3K

3.3V 6.2K 3.6K

5V 6.2K 2K

9V 13K 2K

12V 16K 1.8K

EC9483 EC9483



Function Description VIN This is the positive input supply for the IC switching regulator. A suitable input bypass capacitor must be present at this pin to minimize voltage transients and to supply the switching currents needed by the regulator GND Circuit ground. SW Internal switch. The voltage at this pin switches between (VIN – VGS) and approximately – 0.5V, with a duty cycle of approximately VOUT / VIN. To minimize coupling to sensitive circuitry, the PC board copper area connected to this pin should be kept a minimum. FB Senses the regulated output voltage to complete the feedback loop. EN Allows the switching regulator circuit to be shutdown using logic level signals thus dropping the total input supply current to approximately 30uA. Pulling this pin below a threshold voltage of approximately 1.3 V turns the regulator down, and pulling this pin above 1.3V (up to a maximum of 12V) shuts the regulator on. Forautomatic starup condition can be implemented by the addition of a resistive voltage divider from VIN to GND. Thermal Considerations The SOP8 package needs a heat sink under most conditions. The size of the heat sink depends on the input voltage, the output voltage, the load current and the ambient temperature. The EC9483 junction temperature rises above ambient temperature for a 3A load and different input and output voltages. The data for these curves was taken with the EC9483 (SOP8 package) operating as a buck-switching regulator in an ambient temperature of 25 ºC (still air). These temperature rise numbers are all approximate and there are many factors that can affect these temperatures. Higher ambient temperatures require more heat sinking. For the best thermal performance, wide copper traces and generous amounts of printed circuit board copper should be used in the board layout.(Once exception to this is the output (switch) pin, which should not have large areas of copper.) Large areas of copper provide the best transfer of heat (lower thermal resistance) to the surrounding air, and moving air lowers the thermal resistance even further. Package thermal resistance and junction temperature rise numbers are all approximate, and there are many factors that will affect these numbers. Some of these factors include board size, shape, thickness, position, location, and even board temperature. Other factors are, trace width, total printed circuit copper area, copper thickness, single or double-sided, multi-layer board and the amount of solder on the board. The effectiveness of the PC board to dissipate heat also depends on the size, quantity and spacing of other components on the board, as well as whether the surrounding air is still or moving. Furthermore, some of these components such as the catch diode will add heat to the PC board and the heat can vary as the input voltage changes. For the inductor, depending on the physical size, type of core material and the DC resistance, it could either act as a heat sink taking heat away from the board, or it could add heat to the board.

EC9483 EC9483



OUTLINE DRAWING FOR SOP8

DATA SHEET

Product specificationSupersedes data of 1995 Dec 15File under Integrated Circuits, IC01

1998 Apr 28

INTEGRATED CIRCUITS

TDA1517; TDA1517P2 × 6 W stereo power amplifier

1998 Apr 28 2

Philips Semiconductors Product specification

2 × 6 W stereo power amplifier TDA1517; TDA1517P

FEATURES

• Requires very few external components

• High output power

• Fixed gain

• Good ripple rejection

• Mute/standby switch

• AC and DC short-circuit safe to ground and VP

• Thermally protected

• Reverse polarity safe

• Capability to handle high energy on outputs (VP = 0 V)

• No switch-on/switch-off plop

• Electrostatic discharge protection.

GENERAL DESCRIPTION

The TDA1517 is an integrated class-B dual outputamplifier in a plastic single in-line medium power packagewith fin (SIL9MPF) and a plastic heat-dissipating dualin-line package (HDIP18). The device is primarilydeveloped for multi-media applications.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VP supply voltage 6.0 14.4 18.0 V

IORM repetitive peak output current − − 2.5 A

Iq(tot) total quiescent current − 40 80 mA

Isb standby current − 0.1 100 µA

Isw switch-on current − − 40 µA

|ZI| input impedance 50 − − kΩPo output power RL = 4 Ω; THD = 0.5% − 5 − W

RL = 4 Ω; THD = 10% − 6 − W

SVRR supply voltage ripple rejection fi = 100 Hz to 10 kHz 48 − − dB

αcs channel separation 40 − − dB

Gv closed loop voltage gain 19 20 21 dB

Vno(rms) noise output voltage (RMS value) − 50 − µV

Tc crystal temperature − − 150 °C

TYPENUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA1517 SIL9MPF plastic single in-line medium power package with fin; 9 leads SOT110-1

TDA1517P HDIP18 plastic heat-dissipating dual in-line package; 18 leads SOT398-1

1998 Apr 28 3



BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

mute/stand-byswitch input

MLC351

output 1

15 kΩ

15 kΩ

x 1

VA

stand-byswitch

VP

muteswitch

stand-byreferencevoltage

18 kΩ

18 kΩ

2kΩ

60kΩ

mute switch Cm

power stage

4

8

mute switch

VA

VA

Cm

2kΩ

60kΩ

power stage

6

2 7 5

SGND

signalground

PGND

output 2

non-invertinginput 1

non-invertinginput 2

9

supply voltageripple rejection

output

3

1

TDA1517

mutereferencevoltage

inputreference

voltage

VP

powerground(substrate)

1998 Apr 28 4



PINNING

SYMBOL PIN DESCRIPTION

−INV1 1 non-inverting input 1

SGND 2 signal ground

SVRR 3 supply voltage ripple rejection output

OUT1 4 output 1

PGND 5 power ground

OUT2 6 output 2

VP 7 supply voltage

M/SS 8 mute/standby switch input

−INV2 9 non-inverting input 2

Fig.2 Pin configuration for SOT110-1.

ndbook, halfpage

MLC352

1

2

3

4

5

6

7

8

9

PV

OUT2

SGND

INV1

INV2

TDA1517

OUT1

M/SS

SVRR

PGND

Fig.3 Pin configuration for SOT398-1.

Pins 10 to 18 should be connected to GND or floating.

ndbook, halfpage

MLC353

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

PV

OUT2

SGND

INV1

INV2

TDA1517P

OUT1

M/SS

SVRR

PGND

FUNCTIONAL DESCRIPTION

The TDA1517 contains two identical amplifiers withdifferential input stages. The gain of each amplifier is fixedat 20 dB. A special feature of the device is themute/standby switch which has the following features:

• Low standby current (<100 µA)

• Low mute/standby switching current(low cost supply switch)

• Mute condition.

1998 Apr 28 5



LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL RESISTANCE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VP supply voltage − 18 V

VP(sc) AC and DC short-circuit safe voltage − 18 V

VP(r) reverse polarity − 6 V

ERGO energy handling capability at outputs VP = 0 V − 200 mJ

IOSM non-repetitive peak output current − 4 A

IORM repetitive peak output current − 2.5 A

Ptot total power dissipation see Fig.4 − 15 W

Tstg storage temperature −55 +150 °CTamb operating ambient temperature −40 +85 °CTc crystal temperature − 150 °C

SYMBOL TYPE NUMBER PARAMETER VALUE UNIT

Rth j-c TDA1517 thermal resistance from junction to case 8 K/W

Rth j-p TDA1517P thermal resistance from junction to pins 15 K/W

Rth j-a TDA1517; TDA1517P thermal resistance from junction to ambient 50 K/W

Fig.4 Power derating curve.

(1) Rth j-c = 8 K/W.

(2) Rth j-p = 15 K/W.

handbook, halfpage

25 0 50 150

12

0

MLC354

100T ( C)

oamb

P(W)

18

6

(1)

(2)

1998 Apr 28 6



DC CHARACTERISTICSVP = 14.4 V; Tamb = 25 °C; measured in Fig.6; unless otherwise specified.

Note

1. The circuit is DC adjusted at VP = 6 to 18 V and AC operating at VP = 8.5 to 18 V.


Supply

VP supply voltage note 1 6.0 14.4 18.0 V

Iq(tot) total quiescent current − 40 80 mA

VO DC output voltage − 6.95 − V

Mute/standby switch

V8 switch-on voltage level see Fig.5 8.5 − − V

Mute condition

VO output signal in mute position VI(max) = 1 V; fi = 20 Hz to 15 kHz − − 2 mV

Standby condition

Isb DC current in standby condition − − 100 µA

Vsw switch-on current − 12 40 µA

1998 Apr 28 7



AC CHARACTERISTICSVP = 14.4 V; RL = 4 Ω; f = 1 kHz; Tamb = 25 °C; measured in Fig.6; unless otherwise specified.

Notes

1. Output power is measured directly at the output pins of the IC.

2. Frequency response externally fixed.

3. Ripple rejection measured at the output with a source impedance of 0 Ω, maximum ripple amplitude of 2 V (p-p) anda frequency between 100 Hz and 10 kHz.

4. Noise voltage measured in a bandwidth of 20 Hz to 20 kHz.

5. Noise output voltage independent of Rs (VI = 0 V).


Po output power THD = 0.5%; note 1 4 5 − W

THD = 10%; note 1 5.5 6.0 − W

THD total harmonic distortion Po = 1 W − 0.1 − %

flr low frequency roll-off at −3 dB; note 2 − 45 − Hz

fhr high frequency roll-off at −1 dB 20 − − kHz

Gv closed loop voltage gain 19 20 21 dB

SVRR supply voltage ripple rejection note 3

on 48 − − dB

mute 48 − − dB

standby 80 − − dB

|Zi| input impedance 50 60 75 kΩVno noise output voltage

on Rs = 0 Ω; note 4 − 50 − µV

on Rs = 10 Ω; note 4 − 70 100 µV

mute note 5 − 50 − µV

αcs channel separation Rs = 10 Ω 40 − − dB

|∆Gv| channel unbalance − 0.1 1 dB

1998 Apr 28 8



Fig.5 Standby, mute and on conditions.

handbook, halfpage

8.5

0

MLC355

V

18

6.4

3.3

2

11(V)

ON (I = 40 mA)P

mute (I = 40 mA)P

standby (I 100 µA)P

APPLICATION INFORMATION

Fig.6 Application circuit diagram.

handbook, full pagewidth

MLC356

100 nF

PV

TDA1517

8 7

standby switch

220 nFinput 1

1000 µF 1000 µF

inputreference

voltage

2 5

signalground

powerground

1 9220 nF

input 2

4 6

3

2200µF

internal1/2 VP

100µF

60 kΩ60 kΩ 20 dB 20 dB

1998 Apr 28 9



PACKAGE OUTLINES

UNIT AA

max.2 A3 b1 D1b2b c D(1) E(1) Z

max.

(1)e L P P1 q1 q2q

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 18.517.8 3.7

8.78.0

A4

15.815.4

1.401.14

0.670.50

1.401.14

0.480.38

21.821.4

21.420.7

6.486.20

3.43.2

2.54 1.05.95.7

4.44.2

3.93.4

15.114.9

Q

1.751.55

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

2.752.50

SOT110-192-11-1795-02-25

0 5 10 mm

scale

0.25

w

D

E

A

A

c

A2

3

A4

q 1

q 2

L

Q

w M

b

b1b2

D1

P

q

1

Z e

1 9

P

seat

ing

plan

e

pin 1 index

SIL9MPF: plastic single in-line medium power package with fin; 9 leads SOT110-1

1998 Apr 28 10



UNIT Amax.

1 2 b1(1) (1) (1)

b2 c D E e M ZHL

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT398-194-04-1395-01-25

A min.

A max. b

max.wMEe1

1.401.14

0.670.50

0.470.38

21.8521.35

6.56.2

3.93.1 0.252.54 7.62

8.328.02

8.77.7 1.04.7 0.51 3.7

inches 0.060.04

0.030.02

0.020.01

1.050.75

0.040.03

0.870.84

0.260.24

0.150.12 0.010.10 0.30

0.330.32

0.340.30 0.040.19 0.02 0.15

MH

c

(e )1

ME

w Mb1

b2

e

A

A1

A2

L

seat

ing

plan

e

Z

D

E

18

1

10

9

b

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

HDIP18: plastic heat-dissipating dual in-line package; 18 leads SOT398-1

1998 Apr 28 11



SOLDERING

Introduction

There is no soldering method that is ideal for all ICpackages. Wave soldering is often preferred whenthrough-hole and surface mounted components are mixedon one printed-circuit board. However, wave soldering isnot always suitable for surface mounted ICs, or forprinted-circuits with high population densities. In thesesituations reflow soldering is often used.

This text gives a very brief insight to a complex technology.A more in-depth account of soldering ICs can be found inour “Data Handbook IC26; Integrated Circuit Packages”(order code 9398 652 90011).

Soldering by dipping or by wave

The maximum permissible temperature of the solder is260 °C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contacttime of successive solder waves must not exceed5 seconds.

The device may be mounted up to the seating plane, butthe temperature of the plastic body must not exceed thespecified maximum storage temperature (Tstg max). If theprinted-circuit board has been pre-heated, forced coolingmay be necessary immediately after soldering to keep thetemperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to thelead(s) of the package, below the seating plane or notmore than 2 mm above it. If the temperature of thesoldering iron bit is less than 300 °C it may remain incontact for up to 10 seconds. If the bit temperature isbetween 300 and 400 °C, contact may be up to 5 seconds.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of theseproducts can reasonably be expected to result in personal injury. Philips customers using or selling these products foruse in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from suchimproper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one ormore of the limiting values may cause permanent damage to the device. These are stress ratings only and operationof the device at these or at any other conditions above those given in the Characteristics sections of the specificationis not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

UTC LD1117/A LINEAR INTEGRATED CIRCUIT

UTC UNISONIC TECHNOLOGIES CO., LTD. 1

QW-R102-006,H

LOW DROP FIXED AND ADJUSTABLE POSITIVE VOLTAGE REGULATORS DESCRIPTION The UTC LD1117/A is a LOW DROP Voltage Regulator able to provide up to 0.8/1.0A of Output Current, available even in adjustable version (Vref=1.25V). Concerning fixed versions, are offered the following Output Voltages: 1.8V, 2.5V, 2.85V, 3.0V, 3.3V and 5.0V. The 2.85V type is ideal for SCSI-2 lines active termination. The device is supplied in: SOT-223, TO-252, TO-263, TO-263-3, SOP-8 and TO-220. The SOT-223, TO-263, TO-263-3 and TO-252 surface mount packages optimize the thermal characteristics even offering a relevant space saving effect. High efficiency is assured by NPN pass transistor. In fact in the case, unlike than PNP one, the Quiescent Current flows mostly into the load. Only a very common 10µF minimum capacitor is needed for stability. On chip trimming allows the regulator to reach a very tight output voltage tolerance, within ±1% at 25°C. The ADJUSTABLE LD1117/A is pin to pin compatible with the other standard Adjustable voltage regulators maintaining the better performances in terms of Drop and Tolerance.

FEATURES *Low dropout voltage (1V Typ.) *2.85V device performances are suitable for SCSI-2 active termination

*Output current up to 0.8/1.0A *Fixed output voltage of: 1.8V,2.5V, 2,85V, 3.0V, 3.3V, 5.0V *Adjustable version availability (Vref=1.25V) *Internal current and thermal limit *Available in ±1%(at 25°C) and 2% in all temperature range *Supply voltage rejection: 75dB (TYP) *Temperature range: 0°C to 125°C

SOP-8SOT-223

123

1

TO-220 TO-252

TO-2631

1

1

TO-263-3

SOP-8 1: GND; 2,3,6,7: Vout; 4: Vin; 5,8: NC



QW-R102-006,H

MARKING INFORMATION

PACKAGE VOLTAGE CODE

PIN CODE PIN 1 PIN 2 PIN 3 MARKING

A GND OUT IN

B OUT GND IN

C GND IN OUT

SOT-223

D IN GND OUT 1 2 3

LD1117

VOLTAGECODE

DATECODE

PIN CODECURRENTCODE

A GND OUT IN

B OUT GND IN

C GND IN OUT

TO-220 TO-252 TO-263

TO-263-3

1 8 : 1 . 8 V 2 5 : 2 . 5 V 2 8 : 2 . 8 5 V 3 0 : 3 . 0 V 3 3 : 3 . 3 V 5 0 : 5 . 0 V AD:ADJ

D IN GND OUT 1 2 3

UTC LD1117

VOLTAGECODE

DATECODE

PIN CODE

CURRENTCODE

Note: The current code “A” means output current up to 1.0A, while without “A” means output current up to 0.8A.



QW-R102-006,H

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL VALUE UNIT DC Input Voltage VIN 15 V Power Dissipation Ptot 12 W Storage temperature Tstg -65 ~ +150 °C Operating Junction Temperature

Top 0 ~ +125 °C

Note: Absolute Maximum Ratings are those value beyond which damage to the device may occur. Functional operation under there condition is not implied. Over the above suggested Max Power Dissipation a Short Circuit could definitively damage the device. THERMAL DATA

PARAMETER SYMBOL VALUE UNIT Thermal Resistance Junction-case SOT-223 SOP-8 TO-252 TO-220

TO-263

Rth-case 15 20 8 3 3

°C/W °C/W °C/W °C/W °C/W

Thermal Resistance Junction-ambient TO-220

Rthj-amb 50

°C/W



QW-R102-006,H

APPLICATION CIRCUIT

LD1117/A

UTC LD1117/A-1.8 ELECTRICAL CHARACTERISTICS (refer to the test circuits, Tj=0 to 125°C, Co=10µF unless otherwise specified)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Output Voltage Vo Vin=3.8V, Io=10mA, Tj=25°C 1.780 1.800 1.820 V Output Voltage Vo Io=0 to 800/1000mA, Vin=3.3 to 8V 1.760 1.840 V Line Regulation ∆Vo Vin=3.3 to 8V, Io=0mA 1 6 mV Load Regulation ∆Vo Vin=3.3V, Io=0 to 800/1000mA 1 10 mV Temperature stability ∆Vo 0.5 % Long Term Stability ∆Vo 1000 hrs, Tj=125°C 0.3 % Operating Input Voltage Vin Io=100mA 10 V Quiescent Current Id Vin≤8V 5 10 mA Output Current Io Vin=6.8V, Tj=25°C 800 950 1200 mA Output Noise Voltage eN B=10Hz to 10KHz, Tj=25°C 100 µV Supply Voltage Rejection

SVR Io=40mA, f=120Hz, Tj=25°C, Vin=5.5V, Vripple=1Vpp

60 75 dB

Dropout Voltage Vd Io=100mA Io=500mA Io=800mA Io=1000mA

1.00 1.05 1.10 1.15

1.10 1.15 1.20 1.25

V V V V

Thermal Regulation Ta=25°C, 30ms Pulse 0.01 0.10 %/W UTC LD1117/A-2.5 ELECTRICAL CHARACTERISTICS (refer to the test circuits, Tj=0 to 125°C, Co=10µF unless otherwise specified)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Output Voltage Vo Vin=4.5V, Io=10mA, Tj=25°C ±1%

±2% 2.4752.450

2.500 2.500

2.525 2.550

V V

Output Voltage Vo Io=0 to 800/1000mA, ±2% Vin=3.9 to 10V ±4%

2.4502.400

2.550 2.600

V V

Line Regulation ∆Vo Vin=3.9 to 10V, Io=0mA 1 6 mV Load Regulation ∆Vo Vin=3.9V, Io=0 to 800/1000mA 1 10 mV Temperature stability ∆Vo 0.5 % Long Term Stability ∆Vo 1000 hrs, Tj=125°C 0.3 % Operating Input Voltage Vin Io=100mA 15 V Quiescent Current Id Vin≤10V 5 10 mA Output Current Io Vin=7.5V, Tj=25°C 800 950 1200 mA



QW-R102-006,H

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Output Noise Voltage eN B=10Hz to 10KHz, Tj=25°C 100 µV Supply Voltage Rejection


60 75 dB


1.00 1.05 1.10 1.15

1.10 1.15 1.20 1.25

V V V V


PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Output Voltage Vo Vin=4.85V, Io=10mA, Tj=25°C 2.82 2.85 2.88 V Output Voltage Vo Io=0 to 800/1000mA,Vin=4.25 to 10V 2.79 2.91 V Line Regulation ∆Vo Vin=4.25 to 10V, Io=0mA 1 6 mV Load Regulation ∆Vo Vin=4.25V, Io=0 to 800/1000mA 1 10 mV Temperature stability ∆Vo 0.5 % Long Term Stability ∆Vo 1000 hrs, Tj=125°C 0.3 % Operating Input Voltage Vin Io=100mA 15 V Quiescent Current Id Vin≤10V 5 10 mA Output Current Io Vin=7.85V, Tj=25°C 800 950 1200 mA Output Noise Voltage eN B=10Hz to 10KHz, Tj=25°C 100 µV Supply Voltage Rejection


60 75 DB


1.00 1.05 1.10 1.15

1.10 1.15 1.20 1.25

V V V V


PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Output Voltage Vo Vin=5V, Io=10mA, Tj=25°C ±1%

±2% 2.97 2.94

3.00 3.00

3.03 3.06

V V


2.94 2.88

3.06 3.12

V V

Line Regulation ∆Vo Vin=4.5 to 12V, Io=0mA 1 6 mV Load Regulation ∆Vo Vin=4.5V, Io=0 to 800/1000mA 1 10 mV Temperature stability ∆Vo 0.5 % Long Term Stability ∆Vo 1000 hrs, Tj=125°C 0.3 % Operating Input Voltage Vin Io=100mA 15 V Quiescent Current Id Vin≤12V 5 10 mA Output Current Io Vin=8V, Tj=25°C 800 950 1200 mA Output Noise Voltage eN B=10Hz to 10KHz, Tj=25°C 100 µV Supply Voltage Rejection

SVR Io=40mA, f=120Hz, Tj=25°C, Vin=6V, Vripple=1Vpp

60 75 dB



QW-R102-006,H

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Dropout Voltage Vd Io=100mA

Io=500mA Io=800mA Io=1000mA

1.00 1.05 1.10 1.15

1.10 1.15 1.20 1.25

V V V V


PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Output Voltage Vo Vin=5.3V, Io=10mA, Tj=25°C ±1%

±2% 3.2673.235

3.300 3.300

3.333 3.365

V V


3.2353.160

3.365 3.440

V V

Line Regulation ∆Vo Vin=4.75 to 15V, Io=0mA 1 6 mV Load Regulation ∆Vo Vin=4.75V, Io=0 to 800/1000mA 1 10 mV Temperature stability ∆Vo 0.5 % Long Term Stability ∆Vo 1000 hrs, Tj=125°C 0.3 % Operating Input Voltage Vin Io=100mA 15 V Quiescent Current Id Vin≤15V 5 10 mA Output Current Io Vin=8.3V, Tj=25°C 800 950 1200 mA Output Noise Voltage eN B=10Hz to 10KHz, Tj=25°C 100 µV Supply Voltage Rejection


60 75 DB


1.00 1.05 1.10 1.15

1.10 1.15 1.20 1.25

V V V V


PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Output Voltage Vo Vin=7V, Io=10mA, Tj=25°C ±1%

±2% 4.95 4.90

5.00 5.00

5.05 5.10

V V

Output Voltage Vo Io=0 to 800/1000mA, ±2%Vin=6.5 to 15V ±4%

4.90 4.80

5.10 5.20

V V

Line Regulation ∆Vo Vin=6.5 to 15V, Io=0mA 1 10 mV Load Regulation ∆Vo Vin=6.5V, Io=0 to 800/1000mA 1 15 mV Temperature stability ∆Vo 0.5 % Long Term Stability ∆Vo 1000 hrs, Tj=125°C 0.3 % Operating Input Voltage Vin Io=100mA 15 V Quiescent Current Id Vin≤15V 5 10 mA Output Current Io Vin=10V, Tj=25°C 800 950 1200 mA Output Noise Voltage eN B=10Hz to 10KHz, Tj=25°C 100 µV Supply Voltage Rejection

SVR Io=40mA, f=120Hz, Tj=25°C, Vin=8V, Vripple=1Vpp

60 75 dB



QW-R102-006,H

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Dropout Voltage Vd Io=100mA

Io=500mA Io=800mA Io=1000mA

1.00 1.05 1.10 1.15

1.10 1.15 1.20 1.25

V V V V

Thermal Regulation Ta=25°C, 30ms Pulse 0.01 0.10 %/W UTC LD1117/A-ADJUSTABLE ELECTRICAL CHARACTERISTICS (refer to the test circuits, Tj=0 to 125°C, Co=10µF unless otherwise specified)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Reference Voltage Vref Vin-VO=2V, Io=10mA, Tj=25°C 1.238 1.25 1.262 V Reference Voltage Vref Io=10 to 800/1000mA, Vin-Vo=1.4 to

10V 1.225 1.275 V

Line Regulation ∆Vo Vin-Vo=1.5 to 13.75V, Io=10mA 0.035 0.200 % Load Regulation ∆Vo Vin-Vo=3V, Io=10 to 800/1000mA 0.10 0.400 % Temperature stability ∆Vo 0.50 % Long Term Stability ∆Vo 1000 hrs, Tj=125°C 0.3 % Operating Input Voltage Vin 15 V Adjustment Pin Current Iadj Vin≤15V 60 120 µA Adjustment Pin Current Change

∆Iadj Vin-Vo=1.4 to 10V, Io=10 to 800/1000mA

1 5 µA

Minimum Load Current Io(min) Vin=15V 2 5 mA Output Current Io Vin-Vo=5V, Tj=25°C 800 950 1200 mA Output Noise (%Vo) eN B=10Hz to 10KHz, Tj=25°C 0.003 % Supply Voltage Rejection

SVR Io=40mA, f=120Hz, Tj=25°C, Vin-Vo=3V, Vripple=1Vpp

60 75 dB


1.00 1.05 1.10 1.15

1.10 1.15 1.20 1.25

V V V V

Thermal Regulation Ta=25°C, 30ms Pulse 0.01 0.10 %/W TYPICAL APPLICATIONS

FIG.1 Negative Supply



QW-R102-006,H

FIG.2 Active Terminator for SCSI-2 BUS

FIG.3 Circuit for Increasing Output Voltage



QW-R102-006,H

FIG.4 Voltage Regulator With Reference

FIG.5 Battery Backed-up Regulated Supply



QW-R102-006,H

FEEDBACK PATH

FIG.6 Post-Regulated Dual Supply



QW-R102-006,H

LD1117/A ADJUSTABLE APPLICATION NOTE The LD1117/A ADJUSTABLE has a thermal stabilized 1.25±0.012V reference voltage between the OUT and ADJ pins. IADJ is 60µA typ. (120µA max.) and ∆IADJ is 1µA typ. (5µA max.). R1 is normally fixed to 120Ω. From figure 7 we obtain: VOUT=VREF+R2(IADJ + IR1)=VREF + R2(IADJ + VREF / R1)=VREF(1+R2/R1) + R2 x IADJ. In normal application R2 value is in the range of few Kohm,, so the R2 X IADJ product could not be considered in the VOUT calculation; then the above expression becomes: VOUT=VREF(1+R2/R1) In order to have the better load regulation it is important to realize a good Kelvin connection of R1 and R2 resistors. In particular R1 connection must be realized very close to OUT and ADJ pin, while R2 ground connection must be placed as near as possible to the negative Load pin. Ripple rejection can be improved by introducing a 10µF electrolytic capacitor placed in parallel to the R2 resistor (See Fig. 8)

FIG.7 Adjustable Output Voltage Application Circuit

FIG.8 Adjustable Output Voltage Application with improved Ripple Rejection.



QW-R102-006,H

TYPICAL CHARACTERISTICS

Fig.1 Reference Voltge vs.Temperature

Fig.2 Output Voltage vs.Temperautre

-75

Junction Temperature(°C)

refe

renc

e vo

ltage

(V)

Junction Temperature(°C)-75

Out

put V

olta

ge(V

)

3.20

Fig.3 Maximum Power Dissipation

25 65 105

4

6

8

10

Case Temperature(°C)

Pow

er (W

) TO-263 & TO-252

SOT-223

2

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

1.245

1.250

-50 -25 0 25 50 75 100 125 150 175

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

3.65

3.70

-50 -25 0 25 50 75 100 125 150 175

Vout=3.3V

Vout=3.6V

Note: LD1117 Only

VOUT SET WITH 1% RESISTORS

45 85 125

0

L1084TO-252, 263, 220

1

5A Adjustable Low Dropout Linear Regulator (LDO)

NIKO-SEM

MAY-31-2001

GENERAL DESCRIPTION The L1084 is a positive and low dropout three-terminal voltage regulator with 5A output current capability. This device is designed for use in low voltage applications that offers lower dropout voltage and faster transient response. This device is fully protected against over current faults, over temperature operation, reversed input polarity, reversed lead insertion, transient voltage spike …etc. On-Chips trimming the reference voltage to 1% and features the low dropout of maximum 1.45 volts. The L1084 Series regulators are available in the popular industry standard TO-220, TO-263 and TO-252 packages.

FEATURES Very easy to use, it requires only two

external resistors to set the output voltage Low dropout voltage:

1.2V typical at up to 5A Low ground current Fast transient response Current & thermal limiting Line regulation: 0.5% typical Load regulation: 0.5% typical TO-220, TO-263 and TO-252 packages

APPLICATIONS

High current microprocessor supplies Low voltage logic supply Powering VGA & sound card Portable instrumentation Constant current regulator Post regulator for switching power supply

TYPICAL APPLICATION

- Basic Adjustable Regulator Circuit -

+Cin10uF

R2

+ Cout10uF

R1

IN

ADJ

OUTL1084Vin

1. Cin needed if device is far from from filter capacitors.

Iadj

Vo = Vref (1+R2/R1) + Iadj x R2

Vout

Vref

2. Cout required for stability.

L1084TO-252, 263, 220

2


NIKO-SEM

MAY-31-2001

ABSOLUTE MAXIMUM RATINGS

Maximum Supply Voltage 7V Operating Junction Temperature Range 0 to 125 °C

Power Dissipation Internally Limited

Storage Temperature Range -40 to 150 °C

Thermal Resistance Junction to Case, θJC 2.5 °C/W Lead Temperature

(Soldering, 10 Seconds) 260 °C

Thermal Resistance Junction to Ambient, θJA TO-220 TO-263 TO-252

50 °C/W60 °C/W 70 °C/W

ELECTRICAL CHARACTERISTICS (Unless otherwise specified, TA = 25 °C.)

Parameter Symbol Test Conditions Typical Limits

Reference Voltage VREF VIN = 5V, IOUT = 10mA 1.25V 1.23VMin 1.27VMax

Dropout Voltage VD ΔVREF = 1%, IOUT = 5A 1.2V 1.45V Line Regulation REG(LINE) (VOUT + 1.5V) ≤ VIN ≤ 7V, IOUT = 10mA 0.5% 2% Load Regulation REG(LOAD) (VIN -VOUT) = 3V, 10mA ≤ IOUT ≤ 5A 0.5% 2.5% Minimum Load Current IO 1.5V ≤ (VIN -VOUT) ≤ 5.75V 10mA

Adjust Pin Current IADJ 55µA 100µA Current Limit ICL VIN - VOUT = 2V 7.5A 5.0A (Min)

RMS Output Noise VN 0.003% of VOUT

Ripple Rejection Ratio RA f = 120Hz, CADJ = 22µF for ADJ pin,

VIN = 5V, IOUT = 5A 72dB 60dB (Min)

DEVICE SELECTION GUIDE Device L1084D L1084S L1084S3 L1084T

Package TO-252 TO-263 (2-Lead) TO-263 (3-Lead) TO-220

Marking L1084D L1084S L1084S3 L1084T

L1084TO-252, 263, 220

3


NIKO-SEM

MAY-31-2001


Vout=3.3V,Vin=5V,Iout=105mA/5A

Cin=10μF,Cout=10μF

L1084TO-252, 263, 220

4


NIKO-SEM

MAY-31-2001

PIN CONFIGURATIONS

Pin # Function

1 Adjust

2 Output

3 Input Note: TAB is Output Pin

L1084TO-252, 263, 220

5


NIKO-SEM

MAY-31-2001

TO-263 (D2PAK) MECHANICAL DATA

mm mm

Dimension Min. Typ. Max.

DimensionMin. Typ. Max.

A 14.5 15 15.8 H 1.0 1.5 1.8

B 4.2 4.7 I 9.8 10.3

C 1.20 1.35 J 6.5

D 2.8 K 1.5

E 0.3 0.4 0.5 L 0.7 1.4

F -0.102 0.203 M 4.83 5.08 5.33

G 8.5 9 9.5 N

L1084TO-252, 263, 220

6


NIKO-SEM

MAY-31-2001

TO-263 (D2PAK) MECHANICAL DATA

mm mm



A 14.5 15 15.8 H 1.0 1.5 1.8

B 4.2 4.7 I 9.8 10.3

C 1.20 1.35 J 6.5

D 2.8 K 1.5

E 0.3 0.4 0.5 L 0.7 1.4

F -0.102 0.203 M 4.83 5.08 5.33

G 8.5 9 9.5 N

L1084TO-252, 263, 220

7


NIKO-SEM

MAY-31-2001

TO-220 (3-Lead) MECHANICAL DATA

mm mm



A 9.78 10.16 10.54 H 2.4 2.54 2.68

B 2.61 2.74 2.87 I 1.19 1.27 1.35

C 20 J 4.4 4.6 4.8

D 28.5 28.9 29.3 K 1.14 1.27 1.4

E 14.6 15.0 15.4 L 2.3 2.6 2.9

F 8.4 8.8 9.2 M 0.26 0.46 0.66

G 0.72 0.8 0.88 N 7°

L1084TO-252, 263, 220

8


NIKO-SEM

MAY-31-2001

TO-252 (DPAK) MECHANICAL DATA

mm mm



A 9.35 10.1 H 0.8

B 2.2 2.4 I 6.4 6.6

C 0.48 0.6 J 5.2 5.4

D 0.89 1.5 K 0.6 1

E 0.45 0.6 L 0.64 0.9

F 0.03 0.23 M 4.4 4.6

G 6 6.2 N

Two-wireSerial EEPROM1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

8K (1024 x 8)

16K (2048 x 8)

AT24C01AAT24C02(1)

AT24C04AT24C08AAT24C16A

0180Y–SEEPR–2/06

Note: 1. Not Recommended fornew design; Pleaserefer to 24C02Bdatasheet.

Features• Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)– 1.8 (VCC = 1.8V to 5.5V)

• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)

• Two-wire Serial Interface• Schmitt Trigger, Filtered Inputs for Noise Suppression• Bidirectional Data Transfer Protocol• 100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility• Write Protect Pin for Hardware Data Protection• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes• Partial Page Writes Allowed• Self-timed Write Cycle (5 ms max)• High-reliability

– Endurance: 1 Million Write Cycles– Data Retention: 100 Years

• Automotive Devices Available• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead

SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

DescriptionThe AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serialelectrically erasable and programmable read-only memory (EEPROM) organized as128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in manyindustrial and commercial applications where low-power and low-voltage operationare essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP, 8- lead JEDEC SOIC, 8- lead Ultra Thin Mini-MAP (MLP 2x3), 5- lead SOT23(AT24C01A/AT24C02/AT24C04), 8-lead TSSOP, and 8-ball dBGA2 packages and isaccessed via a Two-wire serial interface. In addition, the entire family is available in2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

Table 1. Pin Configuration

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

GND Ground

VCC Power Supply

8-lead SOIC

1234

8765

A0A1A2

GND

VCCWPSCLSDA

8-lead PDIP

1234

8765

A0A1A2

GND

VCCWPSCLSDA

8-lead Ultra Thin Mini-MAP (MLP 2x3)

Bottom View

1234

8765

VCCWP

SCLSDA

A0A1A2GND

5-lead SOT23

1

2

3

5

4

SCL

GND

SDA

WP

VCC

8-ball dBGA2

Bottom View

VCCWP

SCLSDA

A0A1A2GND

1

2

3

4

8

7

6

5

8-lead TSSOP

1234

8765

A0A1A2

GND

VCCWPSCLSDA

1

Figure 1. Block Diagram

Absolute Maximum RatingsOperating Temperature..................................–55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pinwith Respect to Ground ....................................–1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

2 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into eachEEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin isopen-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are deviceaddress inputs that are hard wired for the AT24C01A and the AT24C02. As many aseight 1K/2K devices may be addressed on a single bus system (device addressing isdiscussed in detail under the Device Addressing section).

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4Kdevices may be addressed on a single bus system. The A0 pin is a no connect and canbe connected to ground.

The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8Kdevices may be addressed on a single bus system. The A0 and A1 pins are no connectsand can be connected to ground.

The AT24C16A does not use the device address pins, which limits the number ofdevices on a single bus to one. The A0, A1 and A2 pins are no connects and can beconnected to ground.

WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin thatprovides hardware data protection. The Write Protect pin allows normal Read/Writeoperations when connected to ground (GND). When the Write Protect pin is connectedto VCC, the write protection feature is enabled and operates as shown in Table 2.

Table 2. Write Protect

Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,the 1K requires a 7-bit data word address for random word addressing.

AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,the 2K requires an 8-bit data word address for random word addressing.

AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,the 4K requires a 9-bit data word address for random word addressing.

AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,the 8K requires a 10-bit data word address for random word addressing.

AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 byteseach, the 16K requires an 11-bit data word address for random word addressing.

WP PinStatus

Part of the Array Protected

24C01A 24C02 24C04 24C08A 24C16A

At VCCFull (1K) Array

Full (2K) Array

Full (4K) Array

Full (8K)

ArrayFull (16K) Array

At GND Normal Read/Write Operations

30180Y–SEEPR–2/06

Note: 1. This parameter is characterized and is not 100% tested.

Note: 1. VIL min and VIH max are reference only and are not tested.

Table 3. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V

Symbol Test Condition Max Units Conditions

CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V

CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Table 4. DC CharacteristicsApplicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V(unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 1.8 5.5 V



ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA

ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA

ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 µA




ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA

ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA

VIL Input Low Level(1) –0.6 VCC x 0.3 V

VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V

VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

4 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

Note: 1. This parameter is characterized.

Table 5. AC CharacteristicsApplicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +2.7V to +5.5V,CL = 1 TTL Gate and 100 pF (unless otherwise noted)

Symbol Parameter

1.8-volt 2.7, 5.0-volt

UnitsMin Max Min Max

fSCL Clock Frequency, SCL 100 400 kHz

tLOW Clock Pulse Width Low 4.7 1.2 µs

tHIGH Clock Pulse Width High 4.0 0.6 µs

tI Noise Suppression Time(1) 100 50 ns

tAA Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs

tBUFTime the bus must be free before a new transmission can start(1) 4.7 1.2 µs

tHD.STA Start Hold Time 4.0 0.6 µs

tSU.STA Start Setup Time 4.7 0.6 µs

tHD.DAT Data In Hold Time 0 0 µs

tSU.DAT Data In Setup Time 200 100 ns

tR Inputs Rise Time(1) 1.0 0.3 µs

tF Inputs Fall Time(1) 300 300 ns

tSU.STO Stop Setup Time 4.7 0.6 µs

tDH Data Out Hold Time 100 50 ns

tWR Write Cycle Time 5 5 ms

Endurance(1) 5.0V, 25°C, Byte Mode 1M 1MWrite

Cycles

50180Y–SEEPR–2/06

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (seeFigure 4 on page 7). Data changes during SCL high periods will indicate a start or stopcondition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start conditionwhich must precede any other command (see Figure 5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby powermode (see Figure 5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from theEEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it hasreceived each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby modewhich is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and thecompletion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

6 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

Bus Timing

Figure 2. SCL: Serial Clock, SDA: Serial Data I/O®

Write Cycle Timing

Figure 3. SCL: Serial Clock, SDA: Serial Data I/O

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 4. Data Validity

twr(1)

STOPCONDITION

STARTCONDITION

WORDn

ACK8th BIT

SCL

SDA

70180Y–SEEPR–2/06

Figure 5. Start and Stop Definition

Figure 6. Output Acknowledge

8 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

Device Addressing The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address wordfollowing a start condition to enable the chip for a read or write operation (refer to Figure7).

The device address word consists of a mandatory one, zero sequence for the first fourmost significant bits as shown. This is common to all the EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.These 3 bits must compare to their corresponding hard-wired input pins.

The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being amemory page address bit. The two device address bits must compare to their corre-sponding hard-wired input pins. The A0 pin is no connect.

The 8K EEPROM only uses the A2 device address bit with the next 2 bits being formemory page addressing. The A2 bit must compare to its corresponding hard-wiredinput pin. The A1 and A0 pins are no connect.

The 16K does not use any device address bits but instead the 3 bits are used for mem-ory page addressing. These page addressing bits on the 4K, 8K and 16K devicesshould be considered the most significant bits of the data word address which follows.The A0, A1 and A2 pins are no connect.

The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare isnot made, the chip will return to a standby state.

Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following thedevice address word and acknowledgment. Upon receipt of this address, the EEPROMwill again respond with a zero and then clock in the first 8-bit data word. Followingreceipt of the 8-bit data word, the EEPROM will output a zero and the addressingdevice, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally timed write cycle, tWR, to thenonvolatile memory. All inputs are disabled during this write cycle and the EEPROM willnot respond until the write is complete (see Figure 8 on page 11).

PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8Kand 16K devices are capable of 16-byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not senda stop condition after the first data word is clocked in. Instead, after the EEPROMacknowledges receipt of the first data word, the microcontroller can transmit up to seven(1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zeroafter each data word received. The microcontroller must terminate the page writesequence with a stop condition (see Figure 9 on page 11).

The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internallyincremented following the receipt of each data word. The higher data word address bitsare not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at thebeginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) datawords are transmitted to the EEPROM, the data word address will “roll over” and previ-ous data will be overwritten.

90180Y–SEEPR–2/06

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and theEEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending astart condition followed by the device address word. The read/write bit is representative of theoperation desired. Only if the internal write cycle has completed will the EEPROM respondwith a zero allowing the read or write sequence to continue.

Read Operations

Read operations are initiated the same way as write operations with the exception that theread/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the lastaddress accessed during the last read or write operation, incremented by one. This addressstays valid between operations as long as the chip power is maintained. The address “rollover” during read is from the last byte of the last memory page to the first byte of the first page.The address “roll over” during write is from the last byte of the current page to the first byte ofthe same page.

Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. Themicrocontroller does not respond with an input zero but does generate a following stop condi-tion (see Figure 10 on page 12).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the dataword address. Once the device address word and data word address are clocked in andacknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with theread/write select bit high. The EEPROM acknowledges the device address and serially clocksout the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (see Figure 11 on page 12).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with anacknowledge. As long as the EEPROM receives an acknowledge, it will continue to incrementthe data word address and serially clock out sequential data words. When the memoryaddress limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respondwith a zero but does generate a following stop condition (see Figure 12 on page 12).

10 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

Figure 7. Device Address

Figure 8. Byte Write

Figure 9. Page Write

(* = DON’T CARE bit for 1K)

8K

16K

MSB

110180Y–SEEPR–2/06

Figure 10. Current Address Read

Figure 11. Random Read

(* = DON’T CARE bit for 1K)

Figure 12. Sequential Read

12 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2. “U” designates Green Package + RoHS compliant.3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please

contact Serial EEPROM Marketing.

AT24C01A Ordering Information(1) Ordering Code Package Operation Range

AT24C01A-10PU-2.7(2)

AT24C01A-10PU-1.8(2)

AT24C01A-10SU-2.7(2)

AT24C01A-10SU-1.8(2)

AT24C01A-10TU-2.7(2)

AT24C01A-10TU-1.8(2)

AT24C01A-10TSU-1.8(2)

AT24C01AU3-10UU-1.8(2)

AT24C01AY1-10YU-1.8(2) (Not recommended for new design)AT24C01AY6-10YH-1.8(3)

8P3

8P38S1

8S1

8A2

8A25TS1

8U31

8Y18Y6

Lead-free/Halogen-free/Industrial Temperature

(–40°C to 85°C)

AT24C01A-W1.8-11(4) Die Sale Industrial Temperature

(–40°C to 85°C)

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)

8Y6 8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)

5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)

8U3-1 8-ball, die Ball Grid Away Package (dBGA2)

Options

–2.7 Low-voltage (2.7V to 5.5V)


130180Y–SEEPR–2/06

Notes: 1. This device is not recommended for new design. Please refer to AT24C02B datasheet. For 2.7V devices used in the 4.5V to5.5V range, please refer to performance values in the AC and DC characteristics table.

2. “U” designates Green Package + RoHS compliant.3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact

Serial EEPROM Marketing.

AT24C02 Ordering Information(1)

Ordering Code Package Operation Range

AT24C02-10PU-2.7(2)

AT24C02-10PU-1.8(2)

AT24C02N-10SU-2.7(2)

AT24C02N-10SU-1.8(2)

AT24C02-10TU-2.7(2)

AT24C02-10TU-1.8(2)

AT24C02Y1-10YU-1.8(2)

AT24C02-10TSU-1.8(2)

AT24C02U3-10UU-1.8(2)

8P38P38S1

8S18A2

8A28Y15TS18U3-1


(–40°C to 85°C)

AT24C02-W2.7-11(3) Die Sale Industrial Temperature

(–40°C to 85°C)

Package Type







Options



14 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A



AT24C04 Ordering Information(1)


AT24C04-10PU-2.7(2)

AT24C04-10PU-1.8(2)

AT24C04N-10SU-2.7(2)

AT24C04N-10SU-1.8(2)

AT24C04-10TU-2.7(2)

AT24C04-10TU-1.8(2)

AT24C04Y1-10YU-1.8(2) (Not recommended for new design)AT24C04Y6-10YH-1.8(3)

AT24C04-10TSU-1.8(2)

AT24C04U3-10UU-1.8(2)

8P38P38S18S18A28A28Y1

8Y6

5TS18U3-1


(–40°C to 85°C)

AT24C04-W1.8-11(4) Die Sale Industrial Temperature

(–40°C to 85°C)

Package Type








Options



150180Y–SEEPR–2/06



AT24C08A Ordering Information(1) Ordering Code Package Operation Range

AT24C08A-10PU-2.7(2)

AT24C08A-10PU-1.8(2)

AT24C08AN-10SU-2.7(2)

AT24C08AN-10SU-1.8(2)

AT24C08A-10TU-2.7(2)

AT24C08A-10TU-1.8(2)

AT24C08AY1-10YU-1.8(2) (Not recommended for new design)

AT24C08AY6-10YH-1.8(3)

AT24C08AU2-10UU-1.8(2

8P3

8P38S1

8S1

8A2

8A28Y1

8Y6

8U2-1


(−40°C to 85°C)

AT24C08A-W1.8-11(4) Die Sale Industrial Temperature(–40°C to 85°C)

Package Type

8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)





8U2-1 8-ball, die Ball Grid Array Package (dBGA2)

Options

−2.7 Low Voltage (2.7V to 5.5V)


16 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A



AT24C16A Ordering Information(1)


AT24C16A-10PU-2.7(2)

AT24C16A-10PU-1.8(2)

AT24C16AN-10SU-2.7(2)

AT24C16AN-10SU-1.8(2)

AT24C16A-10TU-2.7(2)

AT24C16A-10TU-1.8(2)

AT24C16AY1-10YU-1.8(2) (Not recommended for new design)

AT24C16AY6-10YH-1.8(3)

AT24C16AU2-10UU-1.8(2)

8P3

8P38S1

8S1

8A2

8A28Y1

8Y6

8U2-1


(−40°C to 85°C)

AT24C16A-W1.8-11(3) Die SaleIndustrial Temperature

(−40°C to 85°C)

Package Type

8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)


8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)



8U2-1 8-ball, die Ball Grid Array Package (dBGA2)

Options



170180Y–SEEPR–2/06

Packaging Information

8P3 – PDIP

2325 Orchard ParkwaySan Jose, CA 95131

TITLE DRAWING NO.

R

REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP)

01/09/02

8P3 B

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

COMMON DIMENSIONS(Unit of Measure = inches)

SYMBOL MIN NOM MAX NOTE

D

D1

E

E1

e

Lb2

b

A2 A

1

N

eAc

b34 PLCS

A – – 0.210 2

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

D1 0.005 – – 3

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

Top View

Side View

End View

18 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

8S1 – JEDEC SOIC

1150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906

TITLE DRAWING NO.

R

REV.

Note:

10/7/03

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC)

8S1 B

COMMON DIMENSIONS(Unit of Measure = mm)


A1 0.10 – 0.25

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

A 1.35 – 1.75

b 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.00

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

∅ 0˚ – 8˚

∅

Top ViewEnd View

Side View

e B

D

A

A1

N

E

1

C

E1

L

190180Y–SEEPR–2/06

8A2 – TSSOP


TITLE DRAWING NO.

R

REV.

5/30/02



D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A – – 1.20

A2 0.80 1.00 1.05

b 0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

8A2 B

Side View

End ViewTop View

A2

A

L

L1

D

123

E1

N

b

Pin 1 indicatorthis corner

E

e

20 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

8Y1 – MAP

A – – 0.90

A1 0.00 – 0.05

D 4.70 4.90 5.10

E 2.80 3.00 3.20

D1 0.85 1.00 1.15

E1 0.85 1.00 1.15

b 0.25 0.30 0.35

e 0.65 TYP

L 0.50 0.60 0.70

PIN 1 INDEX AREA

D

E

A

A1 b

8 7 6

e

5

L

D1

E1

PIN 1 INDEX AREA

1 2 3 4

A

Top View End View Bottom View

Side View


TITLE DRAWING NO.

R

REV. 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 C8Y1

2/28/03



210180Y–SEEPR–2/06

8Y6 − Mini-MAP (MLP 2x3 mm)

2325 Orchard Parkway San Jose, CA 95131

TITLE DRAWING NO.

R

REV. 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN) ,(MLP 2x3)

C8Y6

8/26/05

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,tolerances, datums, etc.

2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If theterminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.



D 2.00 BSC

E 3.00 BSC

D2 1.40 1.50 1.60

E2 - - 1.40

A - - 0.60

A1 0.0 0.02 0.05

A2 - - 0.55

A3 0.20 REF

L 0.20 0.30 0.40

e 0.50 BSC

b 0.20 0.25 0.30 2

A2

b(8X)

Pin 1 ID

Pin 1IndexArea

A1

A3

D

E

A

L (8X)

e (6X)

1.50 REF.

D2

E2

22 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

5TS1 – SOT23


TITLE DRAWING NO.

R

REV.

PO5TS1 A

6/25/03



5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SHRINK SOT)

A – – 1.10

A1 0.00 – 0.10

A2 0.70 0.90 1.00

c 0.08 – 0.20 4

D 2.90 BSC 2, 3

E 2.80 BSC 2, 3

E1 1.60 BSC 2, 3

L1 0.60 REF

e 0.95 BSC

e1 1.90 BSC

b 0.30 – 0.50 4, 5

NOTES: 1. This drawing is for general information only. Refer to JEDEC DrawingMO-193, Variation AB, for additional information.

2. Dimension D does not include mold flash, protrusions, or gate burrs.Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end.Dimension E1 does not include interlead flash or protrusion. Interleadflash or protrusion shall not exceed 0.15 mm per side.

3. The package top may be smaller than the package bottom. DimensionsD and E1 are determined at the outermost extremes of the plastic bodyexclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, butincluding any mismatch between the top and bottom of the plastic body.

4. These dimensions apply to the flat section of the lead between 0.08 mmand 0.15 mm from the lead tip.

5. Dimension "b" does not include Dambar protrusion. Allowable Dambarprotrusion shall be 0.08 mm total in excess of the "b" dimension atmaximum material condition. The Dambar cannot be located on the lowerradius of the foot. Minimum space between protrusion and an adjacent leadshall not be less than 0.07 mm.

5 4

2

L1

L

C

End View

C

AA2

A1

b

e

SeatingPlane

D

Side View

e1

E1

31

Top View

E

230180Y–SEEPR–2/06

8U2 – dBGA2


TITLE DRAWING NO.

R

REV. 8U2, 8-ball 0.75 pitch, Die Ball Grid ArrayPackage (dBGA) AT24C512 (AT19870)

02/04/02

8U2 A



D 5.10

D1 1.43 TYP

E 3.25

E1 1.25 TYP

e 0.75 TYP

d 0.75 TYP

A 0.90 REF

A1 0.49 0.52 0.55

A2 0.35 0.38 0.41

Øb 0.47 0.50 0.53

d

e

D

E

A2

A

4

3

2

18

7

6

5

E1

D1

A1

-Z-

ZM80.0

YXZM51.0

Øb

#

#

##

Pin 1 Markthis corner

Notes: 1. These drawings are for general information only. No JEDEC Drawing to refer to for additional information.2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum Z.

Top View

Side ViewBottom View

24 AT24C01A/02/04/08A/16A0180Y–SEEPR–2/06

AT24C01A/02/04/08A/16A

8U3-1 – dBGA2


TITLE DRAWING NO.

R

REV.

PO8U3-1 A

6/24/03



8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Die Ball Grid Array Package (dBGA2)

A 0.71 0.81 0.91

A1 0.10 0.15 0.20

A2 0.40 0.45 0.50

b 0.20 0.25 0.30

D 1.50 BSC

E 2.00 BSC

e 0.50 BSC

e1 0.25 REF

d 1.00 BSC

d1 0.25 REF

1. Dimension “b” is measured at the maximum solder ball diameter.

This drawing is for general information only.

Bottom View8 SOLDER BALLS

bD

E

Top View

PIN 1 BALL PAD CORNER

A

Side View

A2

A1

4

5

PIN 1 BALL PAD CORNER

31

e

2

678

d

(e1)

(d1)

1.

250180Y–SEEPR–2/06

Printed on recycled paper.

0180Y–SEEPR–2/06

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to anyintellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORYWARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULARPURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUTOF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes norepresentations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specificationsand product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically providedotherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for useas components in applications intended to support or sustain life.

Atmel Corporation Atmel Operations

2325 Orchard ParkwaySan Jose, CA 95131, USATel: 1(408) 441-0311Fax: 1(408) 487-2600

Regional Headquarters

EuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 FribourgSwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500

AsiaRoom 1219Chinachem Golden Plaza77 Mody Road TsimshatsuiEast KowloonHong KongTel: (852) 2721-9778Fax: (852) 2722-1369

Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581

Memory2325 Orchard ParkwaySan Jose, CA 95131, USATel: 1(408) 441-0311Fax: 1(408) 436-4314

Microcontrollers2325 Orchard ParkwaySan Jose, CA 95131, USATel: 1(408) 441-0311Fax: 1(408) 436-4314

La ChantrerieBP 7060244306 Nantes Cedex 3, FranceTel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60

ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, FranceTel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USATel: 1(719) 576-3300Fax: 1(719) 540-1759

Scottish Enterprise Technology ParkMaxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743

RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, GermanyTel: (49) 71-31-67-0Fax: (49) 71-31-67-2340

1150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USATel: 1(719) 576-3300Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF Datacom

Avenue de RochepleineBP 12338521 Saint-Egreve Cedex, FranceTel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80

Literature Requestswww.atmel.com/literature

© Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® and others, are registered trade-marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

W9425G6EH

4 M × 4 BANKS × 16 BITS DDR SDRAM

Publication Release Date:Apr. 11, 2008 - 1 - Revision A04

Table of Contents-

1. GENERAL DESCRIPTION............................................................................................................. 4 2. FEATURES .................................................................................................................................... 4 3. KEY PARAMETERS ...................................................................................................................... 5 4. PIN CONFIGURATION .................................................................................................................. 6 5. PIN DESCRIPTION........................................................................................................................ 7 6. BLOCK DIAGRAM ......................................................................................................................... 8 7. FUNCTIONAL DESCRIPTION....................................................................................................... 9

7.1 Power Up Sequence............................................................................................................ 9 7.2 Command Function ........................................................................................................... 10

7.2.1 Bank Activate Command ......................................................................................................10 7.2.2 Bank Precharge Command ..................................................................................................10 7.2.3 Precharge All Command ......................................................................................................10 7.2.4 Write Command ...................................................................................................................10 7.2.5 Write with Auto-precharge Command...................................................................................10 7.2.6 Read Command ...................................................................................................................10 7.2.7 Read with Auto-precharge Command ..................................................................................10 7.2.8 Mode Register Set Command ..............................................................................................11 7.2.9 Extended Mode Register Set Command ..............................................................................11 7.2.10 No-Operation Command ......................................................................................................11 7.2.11 Burst Read Stop Command..................................................................................................11 7.2.12 Device Deselect Command ..................................................................................................11 7.2.13 Auto Refresh Command .......................................................................................................11 7.2.14 Self Refresh Entry Command...............................................................................................12 7.2.15 Self Refresh Exit Command .................................................................................................12 7.2.16 Data Write Enable /Disable Command.................................................................................12

7.3 Read Operation ................................................................................................................. 12 7.4 Write Operation ................................................................................................................. 13 7.5 Precharge .......................................................................................................................... 13 7.6 Burst Termination .............................................................................................................. 13 7.7 Refresh Operation ............................................................................................................. 13 7.8 Power Down Mode ............................................................................................................ 14 7.9 Input Clock Frequency Change during Precharge Power Down Mode ............................ 14 7.10 Mode Register Operation .................................................................................................. 14

7.10.1 Burst Length field (A2 to A0) ................................................................................................14

W9425G6EH


7.10.2 Addressing Mode Select (A3)...............................................................................................15 7.10.3 CAS Latency field (A6 to A4)................................................................................................16 7.10.4 DLL Reset bit (A8) ................................................................................................................16 7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1) ........................................16 7.10.6 Extended Mode Register field ..............................................................................................16 7.10.7 Reserved field ......................................................................................................................16

8. OPERATION MODE .................................................................................................................... 17 8.1 Simplified Truth Table........................................................................................................ 17 8.2 Function Truth Table ......................................................................................................... 18 8.3 Function Truth Table for CKE............................................................................................ 21 8.4 Simplified Stated Diagram................................................................................................. 22

9. ELECTRICAL CHARACTERISTICS ............................................................................................ 23 9.1 Absolute Maximum Ratings............................................................................................... 23 9.2 Recommended DC Operating Conditions ......................................................................... 23 9.3 Capacitance....................................................................................................................... 24 9.4 Leakage and Output Buffer Characteristics ...................................................................... 24 9.5 DC Characteristics............................................................................................................. 25 9.6 AC Characteristics and Operating Condition..................................................................... 26 9.7 AC Test Conditions............................................................................................................ 28 9.8 AC Overshoot/Undershoot Specification for Address and Control Pins ........................... 30 9.9 Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins ............................ 31

10. TIMING WAVEFORMS ................................................................................................................ 32 10.1 Command Input Timing ..................................................................................................... 32 10.2 Timing of the CLK Signals ................................................................................................. 32 10.3 Read Timing (Burst Length = 4) ........................................................................................ 33 10.4 Write Timing (Burst Length = 4) ........................................................................................ 34 10.5 DM, DATA MASK (W9425G6EH) ..................................................................................... 35 10.6 Mode Register Set (MRS) Timing ..................................................................................... 36 10.7 Extend Mode Register Set (EMRS) Timing....................................................................... 37 10.8 Auto-precharge Timing (Read Cycle, CL = 2) ................................................................... 38 10.9 Auto-precharge Timing (Read cycle, CL = 2), continued .................................................. 39 10.10 Auto-precharge Timing (Write Cycle) ................................................................................ 40 10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) .............................................................. 41 10.12 Burst Read Stop (BL = 8) .................................................................................................. 41 10.13 Read Interrupted by Write & BST (BL = 8)........................................................................ 42 10.14 Read Interrupted by Precharge (BL = 8) ........................................................................... 42 10.15 Write Interrupted by Write (BL = 2, 4, 8) ........................................................................... 43

W9425G6EH


10.16 Write Interrupted by Read (CL = 2, BL = 8)....................................................................... 43 10.17 Write Interrupted by Read (CL = 3, BL = 4)....................................................................... 44 10.18 Write Interrupted by Precharge (BL = 8) ........................................................................... 44 10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 45 10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 45 10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 46 10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 46 10.23 Auto Refresh Cycle............................................................................................................ 47 10.24 Precharged/Active Power Down Mode Entry and Exit Timing .......................................... 47 10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................. 47 10.26 Self Refresh Entry and Exit Timing ................................................................................... 48

11. PACKAGE SPECIFICATION ....................................................................................................... 49 11.1 TSOP 66 lI – 400 mil ......................................................................................................... 49

12. REVISION HISTORY ................................................................................................................... 50

W9425G6EH


1. GENERAL DESCRIPTION W9425G6EH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. W9425G6EH delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the personal computer industrial standard, W9425G6EH is sorted into the following speed grades: -4/-5/-6 and -75. The -4 is compliant to the DDR500/CL3 specification. The -5 is compliant to the DDR400/CL3 specification. The -6 is compliant to the DDR333/CL2.5 specification. The -75 is compliant to the DDR266/CL2 specification.

All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Write and Read data are synchronized with the both edges of DQS (Data Strobe).

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9425G6EH is ideal for main memory in high performance applications.

2. FEATURES

• 2.5V ±0.2V Power Supply for DDR266/333/400

• 2.6V ±0.1V Power Supply for DDR500

• Up to 250 MHz Clock Frequency

• Double Data Rate architecture; two data transfers per clock cycle

• Differential clock inputs (CLK and CLK )

• DQS is edge-aligned with data for Read; center-aligned with data for Write

• CAS Latency: 2, 2.5 and 3

• Burst Length: 2, 4 and 8

• Auto Refresh and Self Refresh

• Precharged Power Down and Active Power Down

• Write Data Mask

• Write Latency = 1

• 7.8µS refresh interval (8K/64 mS refresh)

• Maximum burst refresh cycle: 8

• Interface: SSTL_2

• Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant

W9425G6EH


3. KEY PARAMETERS SYMBOL DESCRIPTION MIN./MAX. -4 -5 -6 -75

Min. - 7.5 nS 7.5 nS 7.5 nS CL = 2

Max. - 12 nS 12 nS 12 nS

Min. - 6 nS 6 nS 7.5 nS CL = 2.5

Max. - 12 nS 12 nS 12 nS

Min. 4 nS 5 nS 6 nS 7.5 nS

tCK Clock Cycle Time

CL = 3 Max. 10 nS 12 nS 12 nS 12 nS

tRAS Active to Precharge Command Period Min. 36 nS 40 nS 42 nS 45 nS

tRC Active to Ref/Active Command Period Min. 52 nS 55 nS 60 nS 67.5 nS

IDD0 Operating Current:

One Bank Active-Precharge Max. 110 mA 110 mA 110 mA 110 mA

IDD1 Operating Current:

One Bank Active-Read-Precharge Max. 150 mA 150 mA 150 mA 150 mA

IDD4R Burst Operation Read Current Max. 210 mA 180 mA 170 mA 160 mA

IDD4W Burst Operation Write Current Max. 210 mA 180 mA 170 mA 160 mA

IDD5 Auto Refresh Current Max. 190 mA 190 mA 190 mA 190 mA

IDD6 Self-Refresh Current Max. 3 mA 3 mA 3 mA 3 mA

W9425G6EH


4. PIN CONFIGURATION

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

NC

UDQS

CLK

CKE

A11

A9

A8

A7

A6

A5

A4

VSS

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

NC

VDDQ

BA0

BA1

A10/AP

A0

A1

A2

A3

CS

RAS

CAS

WE

28

29

30

31

32

33

39

38

37

36

35

34VDD

LDM

NC

LDQS

NC

VDD

NC

VSSQ

NC

A12

NC

CLK

UDM

VREF

W9425G6EH


5. PIN DESCRIPTION

PIN NUMBER PIN NAME FUNCTION DESCRIPTION

28 − 32, 35 − 42 A0 − A12 Address

Multiplexed pins for row and column address.

Row address: A0 − A12.

Column address: A0 − A8. (A10 is used for Auto-precharge)

26, 27 BA0, BA1 Bank Select Select bank to activate during row address latch time, or bank to read/write during column address latch time.

2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65

DQ0 − DQ15 Data Input/ Output The DQ0 – DQ15 input and output data are synchronized

with both edges of DQS.

16,51 LDQS, UDQS Data Strobe

DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edge-aligned with read data, Center-aligned with write data.

24 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues.

23, 22, 21 RAS ,

CAS , WE Command Inputs Command inputs (along with CS ) define the command

being entered.

20, 47 LDM, UDM Write Mask When DM is asserted “high” in burst write, the input data is masked. DM is synchronized with both edges of DQS.

45, 46 CLK, CLK

Differential Clock Inputs

All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK .

44 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered.

49 VREF Reference Voltage VREF is reference voltage for inputs.

1, 18, 33 VDD Power (+2.5V) Power for logic circuit inside DDR SDRAM.

34, 48, 66 VSS Ground Ground for logic circuit inside DDR SDRAM.

3, 9, 15, 55, 61 VDDQ Power (+2.5V) for I/O Buffer

Separated power from VDD, used for output buffer, to improve noise.

6, 12, 52, 58, 64 VSSQ Ground for I/O Buffer

Separated ground from VSS, used for output buffer, to improve noise.

14, 17, 19, 25, 43, 50, 53 NC No Connection No connection (NC pin should be connected to GND or

floating)

W9425G6EH


6. BLOCK DIAGRAM

CKE

A10

DLLCLOCK

BUFFER

COMMAND

DECODER

ADDRESSBUFFER

REFRESHCOUNTER

COLUMN

COUNTER

CONTROL

SIGNAL

GENERATOR

MODEREGISTER

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY BANK #2

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY BANK #0

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY BANK #3

DATA CONTROL

CIRCUIT

DQBUFFER

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY BANK #1

NOTE: The cell array configuration is 8912 * 512 * 16

RO

W D

ECO

DER

RO

W D

EC

OD

ER

RO

W D

EC

OD

ERR

OW

DEC

OD

ER

A0

A9A11A12

BA1BA0

CS

RAS

CAS

WE

CLK

CLK

DQ0

DQ15

PREFETCH REGISTER

LDMUDM

UDQSLDQS

W9425G6EH


7. FUNCTIONAL DESCRIPTION 7.1 Power Up Sequence

(1) Apply power and attempt to CKE at a low state ( ≤ 0.2V), all other inputs may be undefined 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF.

(2) Start Clock and maintain stable condition for 200 µS (min.). (3) After stable power and clock, apply NOP and take CKE high. (4) Issue precharge command for all banks of the device. (5) Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. (6) Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.

(An additional 200 cycles(min) of clock are required for DLL Lock before any executable command applied.)

(7) Issue precharge command for all banks of the device. (8) Issue two or more Auto Refresh commands. (9) Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.

2 Clock min. tRFC

MRS

CLK

Command ANYCMDAREFAREFPREAMRSEMRSPREA

CLK

tRFCtRPtRP

Enable DLL DLL reset with A8 = High Disable DLL reset with A8 = Low

200 Clock min.

2 Clock min. 2 Clock min.

Inputs maintain stable for 200 µS min.

Initialization sequence after power-up

W9425G6EH


7.2 Command Function 7.2.1 Bank Activate Command

(RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A12 = Row Address)

The Bank Activate command activates the bank designated by the BA (Bank address) signal. Row addresses are latched on A0 to A12 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed.

7.2.2 Bank Precharge Command

(RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don’t Care) The Bank Precharge command percharges the bank designated by BA. The precharged bank is switched from the active state to the idle state.

7.2.3 Precharge All Command

(RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Don’t Care, A10 = "H", A0 to A9, A11, A12 = Don’t Care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state.

7.2.4 Write Command

(RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A8 = Column Address)

The write command performs a Write operation to the bank designated by BA. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation.

7.2.5 Write with Auto-precharge Command

(RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "H", A0 to A8 = Column Address)

The Write with Auto-precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands.

7.2.6 Read Command

(RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "L", A0 to A8 = Column Address)

The Read command performs a Read operation to the bank designated by BA. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation.

7.2.7 Read with Auto-precharge Command

(RAS = "H", CAS = ”L”, WE = ”H”, BA0, BA1 = Bank, A10 = ”H”, A0 to A8 = Column Address)

The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation.

W9425G6EH


1) READA≥ tRAS (min) - (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command.

2) tRCD(min) ≤ READA < tRAS(min) - (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command.

7.2.8 Mode Register Set Command

(RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "L", A0 to A12 = Register Data)

The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after power-up are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes.

7.2.9 Extended Mode Register Set Command

(RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data)

The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). These additional functions include DLL enable/disable, output drive strength selection. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes.

7.2.10 No-Operation Command

(RAS = "H", CAS = "H", WE = "H")

The No-Operation command simply performs no operation (same command as Device Deselect).

7.2.11 Burst Read Stop Command

(RAS = "H", CAS = "H", WE = "L")

The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation.

7.2.12 Device Deselect Command

( CS = "H")

The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command.

7.2.13 Auto Refresh Command

(RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A12 = Don’t Care) AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS–BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO

W9425G6EH


REFRESH cycles at an average periodic interval of tREFI (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI.

7.2.14 Self Refresh Entry Command

(RAS = "L", CAS = "L", WE = "H", CKE = "L", BA0, BA1, A0 to A12 = Don’t Care)

The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is a SSTL_2 input, VREF must be maintained during SELF REFRESH.

7.2.15 Self Refresh Exit Command

(CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H")

The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. The use of SELF REFREH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra auto refresh command is recommended.

7.2.16 Data Write Enable /Disable Command (DM = "L/H" or LDM, UDM = "L/H") During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to DQ15.

7.3 Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS Latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto-precharge command is issued, the Precharge operation is performed automatically after the Read cycle then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation.

W9425G6EH


7.4 Write Operation Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising & falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto-precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto-precharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation.

7.5 Precharge There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state.

7.6 Burst Termination When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted "high" during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination.

7.7 Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 8192 times (rows) within 64mS. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enters issuing the Self Refresh command (CKE asserted "low") while all banks are in the idle state. The device is in Self Refresh mode for as long as CKE held "low". In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 µS and the last distributed Auto Refresh commands must be performed within 7.8 µS before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 µS. In Self Refresh mode, all input/output buffers are disabled,

W9425G6EH


resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation.

7.8 Power Down Mode Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode. When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking CKE "high" can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode.

7.9 Input Clock Frequency Change during Precharge Power Down Mode DDR SDRAM input clock frequency can be changed under following condition: DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency between minimum and maximum operating frequency specified for the particular speed grade. During an input clock frequency change, CKE must be held LOW. Once the input clock frequency is changed, a stable clock must be provided to DRAM before precharge power down mode may be exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM is ready to operate with new clock frequency.

7.10 Mode Register Operation The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and BA0, BA1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode). The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation.

7.10.1 Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4, and 8 words.

A2 A1 A0 BURST LENGTH 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 x x Reserved

W9425G6EH


7.10.2 Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words.

A3 ADDRESSING MODE

0 Sequential

1 Interleave

7.10.2.1. Addressing Sequence of Sequential Mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following.

Addressing Sequence of Sequential Mode

DATA ACCESS ADDRESS BURST LENGTH Data 0 n 2 words (address bits is A0) Data 1 n + 1 not carried from A0 to A1 Data 2 n + 2 4 words (address bit A0, A1) Data 3 n + 3 Not carried from A1 to A2 Data 4 n + 4 Data 5 n + 5 8 words (address bits A2, A1 and A0) Data 6 n + 6 Not carried from A2 to A3 Data 7 n + 7

7.10.2.2. Addressing Sequence for Interleave Mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following.

Addressing Sequence of Interleave Mode

DATA ACCESS ADDRESS BURST LENGTH Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 4 words

Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 8 words

Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0

W9425G6EH


7.10.3 CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depend on the frequency of CLK.

A6 A5 A4 CAS LATENCY 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved

7.10.4 DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.

7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1) These bits are used to select MRS/EMRS.

BA1 BA0 A12-A0 0 0 Regular MRS Cycle 0 1 Extended MRS Cycle 1 x Reserved

7.10.6 Extended Mode Register field 1) DLL Switch field (A0)

This bit is used to select DLL enable or disable

A0 DLL 0 Enable 1 Disable

2) Output Driver Size Control field (A1) This bit is used to select Output Driver Size, both Full strength and Half strength are based on JEDEC standard.

A1 OUTPUT DRIVER 0 Full Strength 1 Half Strength

7.10.7 Reserved field • Test mode entry bit (A7)

This bit is used to enter Test mode and must be set to "0" for normal operation. • Reserved bits (A9, A10, A11, A12)

These bits are reserved for future operations. They must be set to "0" for normal operation.

W9425G6EH


8. OPERATION MODE The following table shows the operation commands.

8.1 Simplified Truth Table

SYM. COMMAND DEVICE STATE CKEn-1 CKEn DM(4) BA0,

BA1 A10A12, A11,

A9-A0CS

RAS CAS WE

ACT Bank Active Idle(3) H X X V V V L L H H

PRE Bank Precharge Any(3) H X X V L X L L H L

PREA Precharge All Any H X X X H X L L H L

WRIT Write Active(3) H X X V L V L H L L

WRITA Write with Auto-precharge Active(3) H X X V H V L H L L

READ Read Active(3) H X X V L V L H L H

READA Read with Auto-precharge Active(3) H X X V H V L H L H

MRS Mode Register Set Idle H X X L, L C C L L L L

EMRS Extended Mode Register Set Idle H X X H, L V V L L L L

NOP No Operation Any H X X X X X L H H H

BST Burst Read Stop Active H X X X X X L H H L

DSL Device Deselect Any H X X X X X H X X X

AREF Auto Refresh Idle H H X X X X L L L H

SELF Self Refresh Entry Idle H L X X X X L L L H

H X X X SELEX Self Refresh Exit Idle (Self

Refresh) L H X X X X L H H X

H X X X PD Power Down

Mode Entry Idle/

Active(5) H L X X X X L H H X

H X X X PDEX Power Down

Mode Exit Any (Power

Down) L H X X X X L H H X

WDE Data Write Enable Active H X L X X X X X X X

WDD Data Write Disable Active H X H X X X X X X X

Notes: 1. V = Valid X = Don’t Care L = Low level H = High level 2. CKEn signal is input level when commands are issued.

CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BA0, BA1 signals. 4. LDM, UDM (W9425G6EH). 5. Power Down Mode can not entry in the burst cycle.

W9425G6EH


8.2 Function Truth Table (Note 1)

CURRENT STATE CS RAS CAS WE ADDRESS COMMAND ACTION NOTES

H X X X X DSL NOP

L H H X X NOP/BST NOP

L H L H BA, CA, A10 READ/READA ILLEGAL 3

L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BA, RA ACT Row activating

L L H L BA, A10 PRE/PREA NOP

L L L H X AREF/SELF Refresh or Self refresh 2

Idle

L L L L Op-Code MRS/EMRS Mode register accessing 2

H X X X X DSL NOP

L H H X X NOP/BST NOP

L H L H BA, CA, A10 READ/READA Begin read: Determine AP 4

L H L L BA, CA, A10 WRIT/WRITA Begin write: Determine AP 4

L L H H BA, RA ACT ILLEGAL 3

L L H L BA, A10 PRE/PREA Precharge 5

L L L H X AREF/SELF ILLEGAL

Row Active

L L L L Op-Code MRS/EMRS ILLEGAL

H X X X X DSL Continue burst to end

L H H H X NOP Continue burst to end

L H H L X BST Burst stop

L H L H BA, CA, A10 READ/READA Term burst, new read: Determine AP 6

L H L L BA, CA, A10 WRIT/WRITA ILLEGAL


L L H L BA, A10 PRE/PREA Term burst, precharging


Read




L H H L X BST ILLEGAL

L H L H BA, CA, A10 READ/READA Term burst, start read: Determine AP 6, 7

L H L L BA, CA, A10 WRIT/WRITA Term burst, start read: Determine AP 6


L L H L BA, A10 PRE/PREA Term burst, precharging 8


Write


W9425G6EH


Function Truth Table, continued





L H L H BA, CA, A10 READ/READA ILLEGAL



L L H L BA, A10 PRE/PREA ILLEGAL


Read with Auto-precharge





L H L H BA, CA, A10 READ/READA ILLEGAL

L H L L BA, CA, A10 WRIT/WRITA ILLEGAL


L L H L BA, A10 PRE/PREA ILLEGAL 3


Write with Auto-precharge


H X X X X DSL NOP-> Idle after tRP

L H H H X NOP NOP-> Idle after tRP





L L H L BA, A10 PRE/PREA Idle after tRP


Precharging


H X X X X DSL NOP-> Row active after tRCD

L H H H X NOP NOP-> Row active after tRCD







Row Activating


W9425G6EH


Function Truth Table, continued


H X X X X DSL NOP->Row active after tWR

L H H H X NOP NOP->Row active after tWR







Write Recovering


H X X X X DSL NOP->Enter precharge after tWR

L H H H X NOP NOP->Enter precharge after tWR







Write Recovering with Auto-precharge


H X X X X DSL NOP->Idle after tRC

L H H H X NOP NOP->Idle after tRC


L H L H X READ/WRIT ILLEGAL

L L H X X ACT/PRE/PREA ILLEGAL

Refreshing

L L L X X AREF/SELF/MRS/EMRS ILLEGAL

H X X X X DSL NOP->Row after tMRD

L H H H X NOP NOP->Row after tMRD


L H L X X READ/WRIT ILLEGAL

Mode Register Accessing

L L X X X ACT/PRE/PREA/AREF/SELF/MRS/EMRS ILLEGAL

Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the

state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisfy burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don’t satisfy tWR Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data

W9425G6EH


8.3 Function Truth Table for CKE CKE CURRENT

STATE n-1 n CS RAS CAS WE ADDRESS ACTION NOTES

H X X X X X X INVALID

L H H X X X X Exit Self Refresh->Idle after tXSNR

L H L H H X X Exit Self Refresh->Idle after tXSNR

L H L H L X X ILLEGAL

L H L L X X X ILLEGAL

Self Refresh

L L X X X X X Maintain Self Refresh

H X X X X X X INVALID

L H X X X X X Exit Power down->Idle after tIS Power Down

L L X X X X X Maintain power down mode

H H X X X X X Refer to Function Truth Table

H L H X X X X Enter Power down 2

H L L H H X X Enter Power down 2

H L L L L H X Self Refresh 1

H L L H L X X ILLEGAL

H L L L X X X ILLEGAL

All banks Idle

L X X X X X X Power down


H L H X X X X Enter Power down 3

H L L H H X X Enter Power down 3

H L L L L H X ILLEGAL

H L L H L X X ILLEGAL

H L L L X X X ILLEGAL

Row Active

L X X X X X X Power down

Any State Other Than Listed Above


Notes:

1. Self refresh can enter only from the all banks idle state.

2. Power Down occurs when all banks are idle; this mode is referred to as precharge power down.

3. Power Down occurs when there is a row active in any bank; this mode is referred to as active power down.

Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data

W9425G6EH


8.4 Simplified Stated Diagram

POWER APPLIED

Automatic Sequence

Command Sequence

Read A

Write Read

ROWACTIVE

POWERDOWN

IDLEMODE

REGISTERSET

AUTOREFRESH

SELFREFRESH

Read

Read A

Write

Write A

PRECHARGE

POWERON

MRS/EMRS AREF

SREF

SREFX

PD

PDEX

ACT

BST

ReadWrite

Write AWrite A

Read A

PRE

PRE

PRE

PRE

ACTIVEPOWERDOWN

PD

PDEX

Read

Read A

W9425G6EH


9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings

PARAMETER SYMBOL RATING UNIT

Input/Output Voltage VIN, VOUT -0.3 ~ VDDQ + 0.3 V

Power Supply Voltage VDD, VDDQ -0.3 ~ 3.6 V

Operating Temperature TOPR 0 ~ 70 °C

Storage Temperature TSTG -55 ~ 150 °C

Soldering Temperature (10s) TSOLDER 260 °C

Power Dissipation PD 1 W

Short Circuit Output Current IOUT 50 mA Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

9.2 Recommended DC Operating Conditions (TA = 0 to 70°C)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTESVDD Power Supply Voltage (for -5/-6/-75) 2.3 2.5 2.7 V 2

VDD Power Supply Voltage (for -4) 2.5 2.6 2.7 V 2

VDDQ I/O Buffer Supply Voltage (for -5/-6/-75) 2.3 2.5 2.7 V 2

VDDQ I/O Buffer Supply Voltage (for -4) 2.5 2.6 2.7 V 2

VREF Input reference Voltage 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2, 3

VTT Termination Voltage (System) VREF - 0.04 VREF VREF + 0.04 V 2, 8

VIH (DC) Input High Voltage (DC) VREF + 0.15 - VDDQ + 0.3 V 2

VIL (DC) Input Low Voltage (DC) -0.3 - VREF - 0.15 V 2

VICK (DC) Differential Clock DC Input Voltage -0.3 - VDDQ + 0.3 V 15

VID (DC) Input Differential Voltage. CLK and CLK inputs (DC)

0.36 - VDDQ + 0.6 V 13, 15

VIH (AC) Input High Voltage (AC) VREF + 0.31 - - V 2

VIL (AC) Input Low Voltage (AC) - - VREF - 0.31 V 2

VID (AC) Input Differential Voltage. CLK and CLK inputs (AC)

0.7 - VDDQ + 0.6 V 13, 15

VX (AC) Differential AC input Cross Point Voltage VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 12, 15

VISO (AC) Differential Clock AC Middle Point VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 14, 15

Notes: Undershoot Limit: VIL (min) = -1.5V with a pulse width < 5 nS Overshoot Limit: VIH (max) = VDDQ +1.5V with a pulse width < 5 nS VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state.

W9425G6EH


9.3 Capacitance (VDD = VDDQ = 2.5V ±0.2V, f = 1 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V)

SYMBOL PARAMETER MIN. MAX. DELTA (MAX.) UNIT

CIN Input Capacitance (except for CLK pins) 2.0 3.0 0.5 pF

CCLK Input Capacitance (CLK pins) 2.0 3.0 0.25 pF

CI/O DQ, DQS, DM Capacitance 4.0 5.0 0.5 pF

CNC NC Pin Capacitance - 1.5 - pF

Notes: These parameters are periodically sampled and not 100% tested.

The NC pins have additional capacitance for adjustment of the adjacent pin capacitance.

9.4 Leakage and Output Buffer Characteristics SYMBOL PARAMETER MIN. MAX. UNIT NOTES

II (L) Input Leakage Current

(0V < VIN < VDDQ, All other pins not under test = 0V)-2 2 µA

IO (L) Output Leakage Current

(Output disabled, 0V < VOUT < VDDQ) -5 5 µA

VOH Output High Voltage (under AC test load condition)

VTT +0.76 - V

VOL Output Low Voltage (under AC test load condition)

- VTT -0.76 V

IOH (DC) Output Minimum Source DC Current -15.2 - mA 4, 6

IOL (DC) Output Minimum Sink DC Current

Full Strength

15.2 - mA 4, 6

IOH (DC) Output Minimum Source DC Current -10.4 - mA 5

IOL (DC) Output Minimum Sink DC Current Half

Strength 10.4 - mA 5

W9425G6EH


9.5 DC Characteristics MAX.

SYM. PARAMETER -4 -5 -6 -75

UNIT NOTES

IDD0

Operating current: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle

110 110 110 110 7

IDD1 Operating current: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle.

150 150 150 150 7, 9

IDD2P Precharge Power Down standby current: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM

20 20 20 20

IDD2F Idle floating standby current: CS > VIH min; All Banks Idle; CKE > VIH min; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DQS and DM

45 45 45 40 7

IDD2N

Idle standby current: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM

45 45 45 40 7

IDD2Q Idle quiet standby current: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ, DQS and DM

40 40 40 35 7

IDD3P Active Power Down standby current: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min 20 20 20 20

IDD3N

Active standby current: CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle

70 70 70 65 7

IDD4R Operating current: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=3; tCK = tCK min; IOUT = 0mA

210 180 170 160 7, 9

IDD4W

Operating current: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle

210 180 170 160 7

IDD5 Auto Refresh current: tRC = tRFC min 190 190 190 190 7 IDD6 Self Refresh current: CKE < 0.2V 3 3 3 3

IDD7

Random Read current: 4 Banks Active Read with activate every 20nS, Auto-precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle

300 300 300 300

mA

W9425G6EH


9.6 AC Characteristics and Operating Condition (Notes: 10, 12)

-4 -5 SYM. PARAMETER

MIN. MAX. MIN. MAX. UNIT NOTES

tRC Active to Ref/Active Command Period 52 55 tRFC Ref to Ref/Active Command Period 60 70 tRAS Active to Precharge Command Period 36 70000 40 70000 tRCD Active to Read/Write Command Delay Time 16 15 tRAP Active to Read with Auto-precharge Enable 16 15

nS

tCCD Read/Write(a) to Read/Write(b) Command Period 1 1 tCK tRP Precharge to Active Command Period 16 15

tRRD Active(a) to Active(b) Command Period 8 10 tWR Write Recovery Time 15 15 tDAL Auto-precharge Write Recovery + Precharge Time -- -- 18

2 -- -- 7.5 12 2.5 -- -- 6 12 tCK CLK Cycle Time 3 4 10 5 12

tAC Data Access Time from CLK, CLK -0.7 0.7 -0.7 0.7

tDQSCK DQS Output Access Time from CLK, CLK -0.6 0.6 -0.6 0.6 16

tDQSQ Data Strobe Edge to Output Data Edge Skew 0.45 0.4

nS

tCH CLk High Level Width 0.45 0.55 0.45 0.55 tCL CLK Low Level Width 0.45 0.55 0.45 0.55

tCK 11

tHP CLK Half Period (minimum of actual tCH, tCL) min (tCL,tCH) Min,

(tCL,tCH)

tQH DQ Output Data Hold Time from DQS tHP -0.5 tHP

-0.5 nS

tRPRE DQS Read Preamble Time 0.9 1.1 0.9 1.1 tRPST DQS Read Postamble Time 0.4 0.6 0.4 0.6

tCK 11

tDS DQ and DM Setup Time 0.4 0.4 tDH DQ and DM Hold Time 0.4 0.4

tDIPW DQ and DM Input Pulse Width (for each input) 1.75 1.75 nS

tDQSH DQS Input High Pulse Width 0.35 0.35 tDQSL DQS Input Low Pulse Width 0.35 0.35 tDSS DQS Falling Edge to CLK Setup Time 0.2 0.2 tDSH DQS Falling Edge Hold Time from CLK 0.2 0.2

tCK 11

tWPRES Clock to DQS Write Preamble Set-up Time 0 0 nS tWPRE DQS Write Preamble Time 0.25 0.25 tWPST DQS Write Postamble Time 0.4 0.6 0.4 0.6 tDQSS Write Command to First DQS Latching Transition 0.85 1.15 0.72 1.25

tCK 11

tIS Input Setup Time (fast slew rate) 0.6 0.6 19, 21-23tIH Input Hold Time (fast slew rate) 0.6 0.6 19, 21-23tIS Input Setup Time (slow slew rate) 0.7 0.7 20-23tIH Input Hold Time (slow slew rate) 0.7 0.7 20-23

tIPW Control & Address Input Pulse Width (for each input) 2.2 2.2 tHZ Data-out High-impedance Time from CLK, CLK -0.7 0.7 -0.7 0.7

tLZ Data-out Low-impedance Time from CLK, CLK -0.7 0.7 -0.7 0.7 tT(SS) SSTL Input Transition 0.5 1.5 0.5 1.5

nS

tWTR Internal Write to Read Command Delay 1 2 tCK tXSNR Exit Self Refresh to non-Read Command 72 75 nS tXSRD Exit Self Refresh to Read Command 200 200 tCK tREFI Refresh Time (8k/64mS) 7.8 7.8 µS 17 tMRD Mode Register Set Cycle Time 8 10 nS

W9425G6EH


Continued

-6 -75 SYM. PARAMETER

MIN. MAX. MIN. MAX. UNIT NOTES

tRC Active to Ref/Active Command Period 60 67.5 tRFC Ref to Ref/Active Command Period 72 75 tRAS Active to Precharge Command Period 42 100000 45 100000 tRCD Active to Read/Write Command Delay Time 18 20 tRAP Active to Read with Auto-precharge Enable 15 15

nS

tCCD Read/Write(a) to Read/Write(b) Command Period 1 1 tCK tRP Precharge to Active Command Period 18 20

tRRD Active(a) to Active(b) Command Period 12 15 tWR Write Recovery Time 15 15 tDAL Auto-precharge Write Recovery + Precharge Time -- -- 18

2 7.5 12 7.5 12 2.5 6 12 7.5 12 tCK CLK Cycle Time 3 6 12 7.5 12

tAC Data Access Time from CLK, CLK -0.7 0.7 -0.75 0.75

tDQSCK DQS Output Access Time from CLK, CLK -0.6 0.6 -0.75 0.75 16

tDQSQ Data Strobe Edge to Output Data Edge Skew 0.45 0.5

nS

tCH CLk High Level Width 0.45 0.55 0.45 0.55 tCL CLK Low Level Width 0.45 0.55 0.45 0.55

tCK 11

tHP CLK Half Period (minimum of actual tCH, tCL) min (tCL,tCH) Min,

(tCL,tCH)

tQH DQ Output Data Hold Time from DQS tHP -0.55 tHP

-0.75 nS

tRPRE DQS Read Preamble Time 0.9 1.1 0.9 1.1 tRPST DQS Read Postamble Time 0.4 0.6 0.4 0.6

tCK 11

tDS DQ and DM Setup Time 0.45 0.5 tDH DQ and DM Hold Time 0.45 0.5

tDIPW DQ and DM Input Pulse Width (for each input) 1.75 1.75 nS

tDQSH DQS Input High Pulse Width 0.35 0.35 tDQSL DQS Input Low Pulse Width 0.35 0.35 tDSS DQS Falling Edge to CLK Setup Time 0.2 0.2 tDSH DQS Falling Edge Hold Time from CLK 0.2 0.2

tCK 11

tWPRES Clock to DQS Write Preamble Set-up Time 0 0 nS tWPRE DQS Write Preamble Time 0.25 0.25 tWPST DQS Write Postamble Time 0.4 0.6 0.4 tDQSS Write Command to First DQS Latching Transition 0.75 1.25 0.75 1.25

tCK 11

tIS Input Setup Time (fast slew rate) 0.75 0.9 19, 21-23tIH Input Hold Time (fast slew rate) 0.75 0.9 19, 21-23tIS Input Setup Time (slow slew rate) 0.8 1.0 20-23tIH Input Hold Time (slow slew rate) 0.8 1.0 20-23

tIPW Control & Address Input Pulse Width (for each input) 2.2 2.2

tHZ Data-out High-impedance Time from CLK, CLK -0.7 0.7 -0.75 0.75

tLZ Data-out Low-impedance Time from CLK, CLK -0.7 0.7 -0.75 0.75

tT(SS) SSTL Input Transition 0.5 1.5 0.5 1.5

nS

tWTR Internal Write to Read Command Delay 1 1 tCK tXSNR Exit Self Refresh to non-Read Command 72 75 nS tXSRD Exit Self Refresh to Read Command 200 200 tCK tREFI Refresh Time (8k/64mS) 7.8 7.8 µS 17 tMRD Mode Register Set Cycle Time 12 15 nS

W9425G6EH


9.7 AC Test Conditions PARAMETER SYMBOL VALUE UNIT

Input High Voltage (AC) VIH VREF + 0.31 V

Input Low Voltage (AC) VIL VREF - 0.31 V

Input Reference Voltage VREF 0.5 x VDDQ V

Termination Voltage VTT 0.5 x VDDQ V

Differential Clock Input Reference Voltage VR Vx (AC) V

Input Difference Voltage. CLK and CLK Inputs (AC) VID (AC) 1.5 V

Output Timing Measurement Reference Voltage VOTR 0.5 x VDDQ V

V SWING (MAX)

VDDQ

VSS

TT

VIH min (AC)

VREF

VIL max (AC)

SLEW = (VIH min (AC) - VILmax (AC)) / T

Output

50 Ω

VTT

Timing Reference Load

OutputV(out) 30pF

Notes:

(1) Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

(2) All voltages are referenced to VSS, VSSQ.( 2.6V±0.1V for DDR500)

(3) Peak to peak AC noise on VREF may not exceed ±2% VREF(DC).

(4) VOH = 1.95V, VOL = 0.35V

(5) VOH = 1.9V, VOL = 0.4V

(6) The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V.

(7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC.

(8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF.

(9) These parameters depend on the output loading. Specified values are obtained with the output open. (10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed

slope.

W9425G6EH


(11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., TDQSS = 0.75 × tCK, tCK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.)

(12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means VICK(CLK)+VICK( CLK )/2. (15) Refer to the figure below.

CLK

CLK

VSS

VICK

VX VXVX

VXVX

VICK

VICK VICKVID(AC)

VID(AC)

0 V Differential

VISO

VISO(min) VISO(max)

VSS

(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.

(17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

(18) tDAL = (tWR/tCK) + (tRP/tCK)

(19) For command/address input slew rate ≥1.0 V/nS.

(20) For command/address input slew rate ≥0.5 V/nS and <1.0 V/nS.

(21) For CLK & CLK slew rate ≥1.0 V/nS (single--ended).

(22) These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation.

(23) Slew Rate is measured between VOH(ac) and VOL(ac).

W9425G6EH


9.8 AC Overshoot/Undershoot Specification for Address and Control Pins SPECIFICATION

PARAMETER DDR500 DDR400 DDR333 DDR266

Maximum peak amplitude allowed for overshoot 1.5 V 1.5 V 1.5 V 1.5 V

Maximum peak amplitude allowed for undershoot 1.5 V 1.5 V 1.5 V 1.5 V

The area between the overshoot signal and VDD must be less than or equal to Max. area in Figure 1 3.0 V-nS 3.0 V-nS 3.6 V-nS 4.5 V-nS

The area between the undershoot signal and GND must be less than or equal to Max. area in Figure 1 3.0 V-nS 3.0 V-nS 3.6 V-nS 4.5 V-nS

0 0.5 0.68751.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.06.3125 6.5 7.0-5

-4

-3

-2

-1

0

1

2

3

4

5Max. amplitude = 1.5V

OvershootVDD

Max. area

Max. amplitude = 1.5V GND

UndershootTime (nS)

Figure 1: Address and Control AC Overshoot and Undershoot Definition

W9425G6EH


9.9 Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins SPECIFICATION

PARAMETER DDR500 DDR400 DDR333 DDR266

Maximum peak amplitude allowed for overshoot 1.2 V 1.2 V 1.2 V 1.2 V

Maximum peak amplitude allowed for undershoot 1.2 V 1.2 V 1.2 V 1.2 V

The area between the overshoot signal and VDD must be less than or equal to Max. area in Figure 2 1.44 V-nS 1.44 V-nS 2.25 V-nS 2.4 V-nS

The area between the undershoot signal and GND must be less than or equal to Max. area in Figure 2 1.44 V-nS 1.44 V-nS 2.25 V-nS 2.4 V-nS

0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0-5

-4

-3

-2

-1

0

1

2

3

4

5Max. amplitude = 1.2V

OvershootVDD

Max. area

Max. amplitude = 1.2V GND

UndershootTime (nS)

Figure 2: DQ/DM/DQS AC Overshoot and Undershoot Definition

W9425G6EH


10. TIMING WAVEFORMS 10.1 Command Input Timing

CLK

CLK

tCK

tCK

tCLtCH

tIS tIH

tIS tIH

tIS tIH

tIS tIH

tIS tIH

CS

RAS

CAS

WE

A0~A12BA0,1

Refer to the Command Truth Table

10.2 Timing of the CLK Signals

tCKtT tT

VIHVIH(AC)VIL(AC)VILCLK

CLK

CLK

CLK

VX VX VX

VIH

VIL

tCH tCL

W9425G6EH


10.3 Read Timing (Burst Length = 4)

tIS tIH

DA0 DA1 DA2

tCH tCL tCK

ADD

CMD

CLK

CLK

READ

Col

QA0 QA1 QA2 DA3QA3

tRPREtDQSCK

tDQSCK tDQSCK

tRPST

PostamblePreamble

Hi-Z

Hi-Z

tDQSQ tDQSQ tDQSQ

tQH

tQH

tAC

tLZ

tHZ

Hi-Z

Hi-Z

DA0 DA1 DA2QA0 QA1 QA2 DA3QA3

tRPREtDQSCK

tDQSCK tDQSCK

tRPST

PostamblePreamble

Hi-Z

Hi-Z

tDQSQ tDQSQ tDQSQ

tQH

tQH

tAC

tLZ tHZ

Hi-Z

Hi-Z

CAS Latency = 2

DQS

Output(Data)

CAS Latency = 3

DQS

Output(Data)

tIS tIH

Notes: The correspondence of LDQS, UDQS to DQ. (W9425G6EH)

LDQS DQ0~7

UDQS DQ8~15

W9425G6EH


10.4 Write Timing (Burst Length = 4)

tIS tIH tDSH tDSS tDSStDSH

tWPRES

tDHtDHtDH

tDS tDS tDS

tDQSS tDSH tDSHtDSS tDSS

Postamble

tWPRE

Preamble

tDQSH tDQSHtDQSL tWPST

DA0 DA1 DA2 DA3

tWPRES

tDS tDS

tDQSS

tDSH tDSHtDSS tDSS

Postamble

tWPRE

Preamble


tWPRES

tDH

tDStDS

tDQSS

Postamble

tWPRE

Preamble


DA0 DA1 DA2 DA3

tDS

tDH tDH

tCH tCL tCK

DQS

Input(Data)

LDQS

DQ0~7

UDQS

DQ8~15

x4, x8 device

x16 device

ADD

CMD

CLK

CLK

WRIT

Col

DA0 DA1 DA2 DA3

DA0 DA1 DA2 DA3

tDHtDHtDH

tDS

DA0 DA1 DA2 DA3DA0 DA1 DA2 DA3

tIS tIH

Note: x16 has two DQSs (UDQS for upper byte and LDQS for lower byte). Even if one of the 2 bytes is not used, both UDQS and LDQS must be toggled.

W9425G6EH


10.5 DM, DATA MASK (W9425G6EH)

W R IT

tD IPW

tD IPW

tD HtD HtD StD S

M asked

C LK

C M D

LD Q S

LD M

D Q 0~D Q 7 D 3D 1D 0

tD IP W

tD IPW

tD HtD HtD StD S

M asked

U D Q S

U D M

D Q 8~D Q 15 D 3D 2D 0

C LK

W9425G6EH


10.6 Mode Register Set (MRS) Timing

MRS

Register Set data

NEXT CMD

tMRD

CLK

CLK

CMD

ADD

A2 A1 A0

A3

A6 A5 A4

A8

BA1 BA0

0 0 0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0

1

0

1

1

1

0

0

0

1

0

1

2

4

8

2

4

8

Burst Length

Sequential Interleaved

Reserved Reserved

Reserved

Reserved

Reserved

Reserved

Sequential

Interleaved

Addressing Mode

CAS Latency

2

DLL Reset

No

Yes

MRS or EMRS

Regular MRS cycle

Extended MRS cycle

2.5

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

BA0

BA1 "0"

"0"

"0"

"0"

"0"

"0"

"0"

DLL Reset

Reserved

Addressing Mode

* "Reserved" should stay "0" during MRS cycle.

Reserved

Mode Register Set or

Extended Mode Register Set

CAS Latency

Burst Length

Reserved Reserved

3

W9425G6EH


10.7 Extend Mode Register Set (EMRS) Timing

EMRS

Register Set data

NEXT CMD

tMRD

CLK

CLK

CMD

ADD

A0

A1

BA1 BA0

0

1

0

1

1

1

0

0

0

1

0

1

Enable

Disable

DLL Switch

Output Driver Size

Full Strength

Half Strength

MRS or EMRS

Regular MRS cycle

Extended MRS cycle

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

BA0

BA1 "0"

"0"

"0"

"0"

"0"

"0"

"0"

* "Reserved" should stay "0" during EMRS cycle.

"0"

"0"

"0"

"0"

"0"

"0"

Output Driver

DLL Switch

Reserved

Mode Register Set or

Extended Mode Register Set

W9425G6EH


10.8 Auto-precharge Timing (Read Cycle, CL = 2) 1) tRCD (READA) ≥ tRAS (MIN) – (BL/2) × tCK

AP

Q7Q6Q5Q4Q3Q2Q1Q0

ACT READA ACT

Q0 Q1 Q2 Q3

ACTREADAACT

Q0 Q1

ACTAPREADAACT

tRPtRAS

CMD

DQS

DQ

CMD

DQS

DQ

CMD

DQS

DQ

BL=2

BL=4

BL=8

CLK

CLK

AP

Notes: CL=2 shown; same command operation timing with CL = 2,5 and CL=3 In this case, the internal precharge operation begin after BL/2 cycle from READA command.

AP

Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command.

W9425G6EH


10.9 Auto-precharge Timing (Read cycle, CL = 2), continued

2) tRCD/RAP(min) ≤ tRCD (READA) < tRAS (min) – (BL/2) × tCK

AP

Q7Q6Q5Q4Q3Q2Q1Q0

ACT READA ACT

Q0 Q1 Q2 Q3

ACTREADAACT

Q0 Q1

ACTAPREADAACT

tRPtRAS

CMD

DQS

DQ

CMD

DQS

DQ

CMD

DQS

DQ

BL=2

BL=4

BL=8

CLK

CLK

AP

tRAP

tRCD

tRAP

tRCD

tRAP

tRCD

Notes: CL2 shown; same command operation timing with CL = 2.5, CL=3. In this case, the internal precharge operation does not begin until after tRAS (min) has command.

AP

Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command.

W9425G6EH


10.10 Auto-precharge Timing (Write Cycle)

AP

WRITA ACT

ACTWRITA

ACTWRITACMD

DQS

DQ

CMD

DQS

DQ

CMD

DQS

DQ

BL=2

BL=4

BL=8

CLK

CLK

AP

AP

D0 D1

D0 D1 D2 D3

D0 D1 D2 D3 D4 D5 D6 D7

tDAL

tDAL

tDAL

The Write with Auto-precharge command cannot be interrupted by any other command.

AP Represents the start of internal precharging .

W9425G6EH


10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8)

CMD

ADD

DQS

CLK

CLK

DQ

ACT READ A READ B READ C READ D READ E

RowAddress COl,Add,A Col,Add,B Col,Add,C Col,Add,D Col,Add,E

QC0QA0 QA1 QB0 QB1

tCCDtCCDtCCDtCCDtRCD

10.12 Burst Read Stop (BL = 8)

READCMD

DQS

DQ

CLK

CLK

BST

Q0 Q1 Q2 Q3 Q4 Q5

Q0 Q1 Q2 Q3 Q4 Q5

CAS Latency

CAS Latency

CAS Latency = 2

DQS

DQ

CAS Latency = 3

W9425G6EH


10.13 Read Interrupted by Write & BST (BL = 8)

READCMD

DQS

DQ

CLK

CLK

BST

Q0 Q1 Q2 Q3 Q4 Q5

CAS Latency = 2

WRIT

D0 D1 D2 D3 D4 D5 D6 D7

Burst Read cycle must be terminated by BST Command to avoid I/O conflict.

10.14 Read Interrupted by Precharge (BL = 8)

READCMD

DQS

DQ

CLK

CLK

PRE

Q0 Q1 Q2 Q3 Q4 Q5

Q0 Q1 Q2 Q3 Q4 Q5

CAS Latency

CAS Latency

CAS Latency = 2

DQS

DQ

CAS Latency = 3

W9425G6EH


10.15 Write Interrupted by Write (BL = 2, 4, 8)

CMD

ADD

DQS

CLK

CLK

DQ

ACT WRIT A WRIT B WRIT C WRIT D WRIT E

RowAddress COl. Add. A Col.Add.B Col. Add. C Col. Add. D Col. Add. E

DC0 DC1 DD0 DD1DA0 DA1 DB0 DB1

tCCDtCCDtCCDtCCDtRCD

10.16 Write Interrupted by Read (CL = 2, BL = 8)

WRITCMD

DQS

DM

CLK

CLK

tWTR

DQ D4 D5 D6 D7D0 D1 D2 D3

Data must bemasked by DM

READ

Data masked by READcommand, DQS input ignored.

Q4 Q5 Q6 Q7Q0 Q1 Q2 Q3

W9425G6EH


10.17 Write Interrupted by Read (CL = 3, BL = 4)

WRITCMD

DQS

DM

CLK

CLK

READ

tWTR

DQ Q0 Q1 Q2 Q3D0 D1 D2 D3

Data must be masked by DM

10.18 Write Interrupted by Precharge (BL = 8)

WRITCMD

DQS

DM

CLK

CLK

ACT

tWR

DQ D4 D5 D6 D7D0 D1 D2 D3

Data must be masked by DM

PRE

tRP

Data masked by PRE command, DQS input ignored.

W9425G6EH


10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ∗ tCK = 100 MHz

CMD

DQS

CLK

CLK

DQ Q0a Q1a Q0b Q1b

ACTa/b : Bank Act. CMD of bank a/bREADAa/b : Read with Auto Pre.CMD of bank a/bAPa/b : Auto Pre. of bank a/b

ACTa ACTb READAa ACTaREADAb ACTb

APa APb

tRCD(a)

tRAS(a) tRP(a)

tRAS(b)

tRCD(b)

tRP(b)

CL(a) CL(b)

Preamble Postamble Preamble Postamble

tRRD

tRC(a)

tRC(b)

tRRD

10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4)

CMD

DQS

CLK

CLK

DQ Q2a Q3a Q2b Q3b

ACTa/b : Bank Act. CMD of bank a/bREADAa/b : Read with Auto Pre.CMD of bank a/bAPa/b : Auto Pre. of bank a/b

ACTa READAaACTb READAb ACTa ACTb

APa APb

tRCD(a)

tRAS(a) tRP(a)

tRAS(b)

tRCD(b)

tRP(b)

CL(a) CL(b)

Preamble Postamble

tRRD

tRC(a)

tRC(b)

tRRD

Q0a Q1a Q0b Q1b

W9425G6EH



CMD

DQS

CLK

CLK

DQ Q0a Q1a Q0b Q1b

ACTa/b/c/d : Bank Act. CMD of bank a/b/c/dREADAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/dAPa/b/c/d : Auto Pre. of bank a/b/c/d

ACTa ACTb READAaACTc READAbACTd READAcACTa

APaAPb

tRCD(a)

tRAS(a) tRP

tRAS(b)

tRCD(b)

CL(a) CL(b)

Preamble Postamble Preamble

tRRD

tRC(a)

tRRD

tRAS(c)

tRAS(d)

tRCD(d)

tRCD(c)

tRRD tRRD


C M D

D Q S

C LK

C LK

D Q

A C T a /b /c /d : B ank A c t. C M D o f bank a /b /c /dR E A D A a/b /c /d : R ead w ith A u to P re .C M D o f bank a /b /c /dA P a /b /c /d : A u to P re . o f bank a /b /c /d

A C T a R E A D A aA C T b R E A D A bA C T c R E A D A cA C T d R E A D A dA C T a

A P a A P b

tR C D (a )

tR A S (a ) tR P (a )

tR A S (b )

tR C D (b )

C L (a ) C L(b )

tR R D

tR C (a )

tR R D

tR A S (c )

tR A S (d )

tR C D (d )

tR C D (c)

tR R D tR R D

Q 2 a Q 3a Q 2b Q 3 b

P ream b le

Q 0a Q 1a Q 0 b Q 1bQ 0a Q 1 a

C L(c )

A P c

W9425G6EH


10.23 Auto Refresh Cycle

CMD

CLK

CLK

PREA AREF AREF CMDNOP NOP NOP

tRP tRFC tRFC

Note: CKE has to be kept “High” level for Auto-Refresh cycle.

10.24 Precharged/Active Power Down Mode Entry and Exit Timing

CMD

CLK

CLK

NOP CMDNOP

ExitEntry

CMD NOP

tIH tIS tCK tIH tIS

CKE

Precharge/ActivateNote 1,2

Note: 1. If power down occurs when all banks are idle, this mode is referred to as precharge power down. 2. If power down occurs when there is a row active in any bank, this mode is referred to as active power down.

10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing

NOP NOP NOP DLLRESET NOP NOP CMD

200 clocks

tISFrequency ChangeOccurs here

Minmum 2 clocksrequired beforechanging frequency

Stable new clockbefore power down exit

CLK

CLK

CMD

CKE

tRP

W9425G6EH


10.26 Self Refresh Entry and Exit Timing

CMD

CLK

CLK

tIH tIS tIH tIS

SELF CMDSELEX NOPNOPPREA

ExitEntry

CKE

tRP

tXSRD

NOPSELF

tXSNR

SELFX NOP ACT READ NOP

ExitEntry

Note: If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.

W9425G6EH


11. PACKAGE SPECIFICATION 11.1 TSOP 66 lI – 400 mil

L1

O 1O

D

1O

O

L

EE1

W9425G6EH


12. REVISION HISTORY VERSION DATE PAGE DESCRIPTION

A01 Dec. 12, 2007 All Formally data sheet

A02 Jan. 04, 2008 5, 25 Revise -4 speed grade Max.IDD4R/IDD4W value from 190mA to 210mA

5, 26 Revise -5 speed grade Max. CLK cycle time tCK value from 10nS to 12nS A03 Feb. 21, 2008

23 Change VDDQ max from VDD to 2.7V

5, 25 Modify -4 speed grade DC Characteristics IDD6 parameter value from 5mA to 3mA

9 Add figure to illustrate Initialization sequence after power-up

23

Revise overshoot/undershoot pulse width Before VIH (max.) = -1.2V with a pulse width < 3 nS After VIH (max.) = -1.5V with a pulse width < 5 nS Before VIL (min.) = VDDQ +1.2V with a pulse width < 3 nSAfter VIL (min.) = VDDQ +1.5V with a pulse width < 5 nS

A04 Apr. 11, 2008

26, 27, 29 Revise input setup/hold time tIS/tIH parameters with skew rate dependency of AC characteristics table

Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Issued Date: Feb. 4th, 2009 Model No.: V216B1-P01

Approval

1 Version 2.1

TFT LCD Preliminary Specification

MODEL NO.: V216B1 – P01

TV Head Division Approved By

LY Chen

LCD TV Marketing and Product Management Div. Prepared By

WY Li Steven Tu

QRA Dept. Product Development Div. Reviewed By

Tomy Chen WT Lin

Customer: __________________________

Approved by:_______________________________

Note:

刪除: 29

刪除: 2003

刪除: L05

刪除: Approval

Issued Date: Feb. 4th, 2009 Model No.: V216B1-P01

Approval

2 Version 2.1

- CONTENTS - REVISION HISTORY ------------------------------------------------------- 3 1. GENERAL DESCRIPTION ------------------------------------------------------- 4 1.1 OVERVIEW 1.2 CHARACTERISTICS 1.3 MECHANICAL SPECIFICATIONS 2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 5 2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASED ON CMO MODULE V216B1-L01) 2.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL) 2.3 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL) 3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 6 3.1 TFT LCD OPEN CELL 4. BLOCK DIAGRAM ------------------------------------------------------- 8 4.1 TFT LCD OPEN CELL 5. INPUT TERMINAL PIN ASSIGNMENT ------------------------------------------------------- 9 5.1 TFT LCD MODULE 5.2 LVDS DATA MAPPING TABLE 5.3 COLOR DATA INPUT ASSIGNMENT 6. INTERFACE TIMING ------------------------------------------------------- 12 6.1 INPUT SIGNAL TIMING SPECIFICATIONS 6.2 POWER ON/OFF SEQUENCE 7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 15 7.1 TEST CONDITIONS 7.2 OPTICAL SPECIFICATIONS 8. DEFINITION OF LABELS ---------------------------------------------- 19

8.1 OPEN CELL LABEL 8.2 CARTON LABEL

9. PACKING ------------------------------------------------------- 20 9.1 PACKING SPECIFICATIONS 9.2 PACKING METHOD 10. PRECAUTIONS ------------------------------------------------------- 22 8.1 ASSEMBLY AND HANDLING PRECAUTIONS 8.2 SAFETY PRECAUTIONS 11. MECHANICAL DRAWING ------------------------------------------------------- 23

刪除: 29

刪除: 2003

刪除: L05

刪除: Approval

Issued Date: Feb. 4th, 2009 Model No.: V216B1 – P01

Approval

Version 2.1

3

REVISION HISTORY

Version Date Page (New) Section Description

Ver 2.0 Ver 2.1

Aug. 15, ’08 Feb. 4th, ‘09

All P20

All Packing

Approval Specification was first issued. Packing specifications

(1) 27 lcd TV Panels / 1 Box (2) Box dimensions : 640(L) x 490(W) x 320(H) mm (3) Weight : Approx.24.2Kg


Approval

Version 2.1

4

1. GENERAL DESCRIPTION 1.1 OVERVIEW

V216B1- P01 is a 21.6-inch wide TFT LCD cell with driver ICs and a 30-pin 1-ch LVDS interface. The

product supports 1366 x 768 (16.9 wide screen) mode and displays up to 16.7 ( 6-bit+Hi-FRC colors) millions

colors. The backlight unit is not built in.

1.2 CHARACTERISTICS CHARACTERISTICS ITEMS SPECIFICATIONS Screen Diagonal [in] 21.6 Pixels [lines] 1366 x R.G.B. x 768

Active Area [mm] 477.417 (H) x 268.416 (V) (21.6” diagonal) Sub -Pixel Pitch [mm] 0.1165 (H) x 0.3495 (V)

Pixel Arrangement RGB vertical stripe Weight [g] TYP. 606 Physical Size [mm] 488.917(W) x 279.916(H) x 2.0(D) Typ. Display Mode TN / Normally White

Contrast Ratio 800:1 Typ. (Typical value measured at CMO’s module: V216B1-L01)

Glass thickness (Array/CF) [mm] 0.7 / 0.7 Viewing Angle (CR>10) +85/-85(H),+80/-80(V) Typ.

(Typical value measured at CMO’s module: V216B1-L01) Color Chromaticity R=(0.644, 0.331)

G=(0.273,0.588) B=(0.151,0.061) W=(0.285,0.293) *Please refer to “color chromaticity” on p.15 (Typical value measured at CMO’s module: V216B1-L01)

Cell Transparency [％] 7.38%Typ.s (Typical value measured at CMO’s module: V216B1-L01)

Polarizer (CF side) Anti-glare coating, 484.4(H) x 275.8(w). Hardness: 3H

Polarizer (TFT side) 484.4(H) x 275.8(w)

1.3 MECHANICAL SPECIFICATIONS Item Min. Typ. Max. Unit Note

Weight 606 g I/F connector mounting position

The mounting inclination of the connector makes the screen center within ±0.5mm as the horizontal. (2)

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

(2) Connector mounting position

+/- 0.5mm

刪除: The inverter module

for the Backlight Unit is not

built in.


Approval

Version 2.1

5

2. ABSOLUTE MAXIMUM RATINGS 2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASED ON CMO MODULE V216B1-L01)

Value Item Symbol Min. Max. Unit Note

Storage Temperature TST -20 +60 ºC (1), (3) Operating Ambient Temperature TOP 0 +50 ºC (1), (2), (3) Altitude Operating A OP 0 5000 M (3) Altitude Storage A ST 0 12000 M (3) Note (1) Temperature and relative humidity range is shown in the figure below.

(a) 90 %RH Max. (Ta ≦ 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation..

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled

chamber. Thermal management should be considered in your product design to prevent the surface

temperature of display area from being over 65 ºC. The range of operating temperature may

degrade in case of improper thermal management in your product design.

Note (3) The rating of environment is base on LCD module. Leave LCD cell alone, this environment condition can’t

be guaranteed. Except LCD cell, the customer has to consider the ability of other parts of LCD module

and LCD module process.

Relative Humidity (%RH)

Operating Range

Temperature (ºC)

100

80 60 -20 40 0 20 -40

90

80

40

60

20

10 Storage Range


Approval

Version 2.1

6

2.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL) Storage Condition : With shipping package.

Storage temperature range : 25±5

Storage humidity range : 50±10%RH Shelf life : a month

2.3 ELECTRICAL ABSOLUTE RATINGS

2.3.1 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL) Value Item Symbol Min. Max. Unit Note

Power Supply Voltage Vcc -0.3 6.0 V Input Signal Voltage VIN -0.3 3.6 V

3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD OPEN CELL Ta = 25 ± 2 ºC Value Parameter Symbol Min. Typ. Max. Unit Note

Power Supply Voltage VCC 4.5 5.0 5.5 V (1) Power Supply Ripple Voltage VRP - - 150 mV Rush Current IRUSH - - 3.0 A (2)

White - 0.50 - A Black - 0.85 0.95 A Power Supply Current Vertical Stripe

ICC - 0.75 - A

(3)

Differential Input High Threshold Voltage VLVTH +100 - - mV

Differential Input Low Threshold Voltage VLVTL - - -100 mV

Common Input Voltage VLVC 1.125 1.25 1.375 V

LVDS Interface

Terminating Resistor RT - 100 - ohm Input High Threshold Voltage VIH 2.7 - 3.3 V CMOS

interface Input Low Threshold Voltage VIL 0 - 0.7 V Note (1) The module should be always operated within above ranges.

Note (2) Measurement Conditions:


Approval

Version 2.1

7

Note (3) The specified power supply current is under the conditions at Vcc = 5 V, Ta = 25 ± 2 ºC, fv = 60 Hz,

whereas a power dissipation check pattern below is displayed.

Active Area Active Area

a. White Pattern b. Black Pattern

Vcc rising time is 470us

470us

+5V

GND

0.9Vcc

0.1Vcc


Approval

Version 2.1

8

4. BLOCK DIAGRAM

4.1 TFT LCD OPEN CELL

Active Area

c. Vertical Stripe Pattern

R

R

R

R

R R

R

R

G

G

G

G

B

B

B

B

B

B

G

G

G

G

B

B

B

B

R

R

TFT LCD PANEL

(1366x3x768)

DATA DRIVER IC

SCA

N D

RIVER

IC

DC/DC CONVERTER &

REFERENCE VOLTAGE

INPU

T CO

NN

ECTO

R

(P-TWO

,196108-30041) )

GND

Vcc

RX0(+/-)

RX1(+/-)

RX2(+/-)

RX3(+/-)

RXCLK(+/-)

SELLVDS

TIMING CONTROLLER

BACKLIGHT UNIT V/L Inverter (W/O)


Approval

Version 2.1

9

5. INPUT TERMINAL PIN ASSIGNMENT 5.1 TFT LCD MODULE

Pin No. Symbol Description Note 1 NC No Connection (2) 2 NC No Connection (2) 3 NC No Connection (2) 4 GND Ground 5 RX0- Negative transmission data of pixel 0 6 RX0+ Positive transmission data of pixel 0 7 GND Ground 8 RX1- Negative transmission data of pixel 1 9 RX1+ Positive transmission data of pixel 1

10 GND Ground 11 RX2- Negative transmission data of pixel 2 12 RX2+ Positive transmission data of pixel 2 13 GND Ground 14 RXCLK- Negative of clock 15 RXCLK+ Positive of clock 16 GND Ground 17 RX3- Negative transmission data of pixel 3 18 RX3+ Positive transmission data of pixel 3 19 GND Ground 20 NC No Connection (2) 21 SELLVDS Select LVDS data format (3) 22 NC No Connection (2) 23 GND Ground 24 GND Ground 25 GND Ground 26 VCC Power supply: +5V 27 VCC Power supply: +5V 28 VCC Power supply: +5V 29 VCC Power supply: +5V 30 VCC Power supply: +5V

Note (1) Connector part no.: P-TWO 196108-30041 (1.0mm FFC) or compatible

Note (2) Reserved for CMO internal use, please leave it open

Note (3) Low: JEIDA data format. High/open: VESA data format.

Note (4) Logic level voltage definition: Low: 0V, High: 3.3V


Approval

Version 2.1

10

5.2 LVDS DATA MAPPING TABLE

SELLVDS = H or Open (VESA)

SELLVDS = L (JEIDA)

R0~R7: Pixel R Data (7; MSB, 0; LSB)

G0~G7: Pixel G Data (7; MSB, 0; LSB)

B0~B7: Pixel B Data (7; MSB, 0; LSB)

DE : Data enable signal

Notes(1) RSVD(reserved)pins on the transmitter shall be “H” or “L”

刪除: Note (2) Specified

values are for lamp (Refer

to 3.2 for further

information).


Approval

Version 2.1

11

5.3 COLOR DATA INPUT ASSIGNMENT The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the

color. The higher the binary input, the brighter the color. The table below provides the assignment of color

versus data input.

Data Signal Red Green Blue Color

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Basic Colors

Black Red Green Blue Cyan Magenta Yellow White

0 1 0 0 0 1 1 1

0 1 0 0 0 1 1 1

0 1 0 0 0 1 1 1

0 1 0 0 0 1 1 1

0 1 0 0 0 1 1 1

0 1 0 0 0 1 1 1

0 1 0 0 0 1 1 1

0 1 0 0 0 1 1 1

0 0 1 0 1 0 1 1

0 0 1 0 1 0 1 1

0 0 1 0 1 0 1 1

0 0 1 0 1 0 1 1

0 0 1 0 1 0 1 1

0 0 1 0 1 0 1 1

0 0 1 0 1 0 1 1

0 0 1 0 1 0 1 1

0 0 0 1 1 1 0 1

0 0 0 1 1 1 0 1

0 0 0 1 1 1 0 1

0 0 0 1 1 1 0 1

0 0 0 1 1 1 0 1

0 0 0 1 1 1 0 1

0 0 0 1 1 1 0 1

0 0 0 1 1 1 0 1

Gray Scale Of Red

Red(0) / Dark Red(1) Red(2)

: :

Red(253) Red(254) Red(255)

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 1 : : 0 1 1

0 1 0 : : 1 0 1

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

Gray Scale Of Green

Green(0) / Dark Green(1) Green(2)

: :

Green(253) Green(254) Green(255)

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 1 : : 0 1 1

0 1 0 : : 1 0 1

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

Gray Scale Of Blue

Blue(0) / Dark Blue(1) Blue(2)

: :

Blue(253) Blue(254) Blue(255)

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 0 0 0

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 0 : : 1 1 1

0 0 1 : : 0 1 1

0 1 0 : : 1 0 1

Note (1) 0: Low Level Voltage, 1: High Level Voltage


Approval

Version 2.1

12

Tvd Tvb

Tv

Th

6. INTERFACE TIMING 6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram. Signal Item Symbol Min. Typ. Max. Unit Note

Frequency 1/Tc 60 76 82 MHZ LVDS Receiver Clock Input cycle to

cycle Jitter

Trcl -

- 200 ps

Setup Time Tlvsu 600 - - ps LVDS Receiver Data Hold Time Tlvhd 600 - - ps 47 50 53

Frame Rate Fr 57 60 63

Hz

Total Tv 778 806 888 Th Tv=Tvd+Tvb Display Tvd 768 768 768 Th -

Vertical Active Display Term

Blank Tvb 10 38 120 Th - Total Th 1442 1560 1936 Tc Th=Thd+Thb Display Thd 1366 1366 1366 Tc - Horizontal Active Display Term Blank Thb 76 194 570 Tc -

Note (1) Since this module is operated in DE only mode, Hsync and Vsync input signals should be set to low

logic level. Otherwise, this module would operate abnormally.

(2) Please refer to 5.1 for detail information.

INPUT SIGNAL TIMING DIAGRAM

DE

Thb

Valid display data (1366 clocks)

Tc

DCLK

Thd

DE

DATA


Approval

Version 2.1

13

LVDS RECEIVER INTERFACE TIMING DIAGRAM

RXCLK+/-

RXn+/-

141T

143T

145T

147T

149T

1411T

14

13T

Tlvsu

Tlvhd

Tc


Approval

Version 2.1

14

0.5≦T1≦10ms 0≦T2≦50ms 0≦T3≦50ms 1s ≦T4

50%

0V

0V

50%

T6 T5

T3 T1

0.1Vcc 0.1VCC

T4 T2

VALID

Power On Power Off

LVDS Signals

Power ON/OFF Sequence

Backlight (Recommended) 500ms≦T5 100ms≦T6

T7 T8

Option Signals (SELLVDS)

0≦T7≦T2 0≦T8≦T3

6.2 POWER ON/OFF SEQUENCE To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram below.

Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.

Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD

operation or the LCD turns off before the backlight turns off, the display may momentarily become

abnormal screen.

Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If

T2<0,that maybe cause electrical overstress failure.

Note (4) T4 should be measured after the module has been fully discharged between power off and on period.

Note (5) Interface signal shall not be kept at high impedance when the power is on.


Approval

Version 2.1

15

7. OPTICAL CHARACTERISTICS 7.1 TEST CONDITIONS

Item Symbol Value Unit Ambient Temperature Ta 25±2 oC Ambient Humidity Ha 50±10 %RH Supply Voltage VCC 5.0 V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS” Inverter Current IL 7.0 mA Inverter Driving Frequency FL 50 KHz Dimming Frequency FB 160 (type) Hz Minimum Duty Ratio DMIN 20 % Maximum Duty Ratio DMAX 100 % Inverter Ampower (27-D024817)

7.2 OPTICAL SPECIFICATIONS The relative measurement methods of optical characteristics are shown as below. The following items should

be measured under the test conditions described in 7.1 and stable environment shown in Note (5).

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR 600 800 - (2)

TR 1.3 2.2 Response Time

TF 3.7 5.8 ms (3)

Center Luminance of White LC 300 400 (4)

White Variation W 1.3 - (7)

Cross Talk CT 4 % (5)

Rx 0.644 - Red

Ry 0.331 -

Gx 0.273 - Green

Gy 0.588 -

Bx 0.151 - Blue

By 0.061 -

Wx 0.285 - White

Wy

Typ. -0.03

0.293

Typ. +0.03

-

(0),(6) Color Chromaticity

Color Gamut CG

x=0, Y =0 Viewing Angle at Normal Direction

With CMO’s

module: V216B1-L01

68 72 % NTSC Ratio

x+ 75 85 Horizontal

x- 75 85

Y+ 70 80 Viewing Angle

Vertical Y-

CR10 With CMO’s

module: V216B1-L01

70 80

Deg. (1)


Approval

Version 2.1

16

Note (0) Light source is the standard light source ”C” which is defined by CIE and driving voltage are based on

suitable gamma voltages. The calculating method is as following :

1. Measure Module’s and BLU’s spectrum. White is without signal input and R,G,B are with signal input.

BLU (for V216B1-L01) is supplied by CMO.

2. Calculate cell’s spectrum.

Calculate cell’s chromaticity by using the spectrum of standard light source “C”.

Note (1) Definition of Viewing Angle (x, y):

Viewing angles are measured by EZ-Contrast 160R (Eldim)

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) = L255 / L0

L255: Luminance of gray level 255

L 0: Luminance of gray level 0

CR = CR (5),

CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (7).

Note (3) Definition of Response Time (TR, TF):

12 o’clock direction

y+ = 90º

6 o’clock

y- = 90º

xx

y- y

x- y+

y- x+

Normal

x = y = 0º

X+ = 90º

X- = 90º

Optical

Response

100% 90%

10% 0%

TR Time TF

Gray Level 0

Gray Level 255 Gray Level 255


Approval

Version 2.1

17

Note (4) Definition of Luminance of White (LC):

Measure the luminance of gray level 255 at center point and 5 points

LC = L (5)

L (X) is corresponding to the luminance of the point X at the figure in Note (7).

Note (5) Definition of Cross Talk (CT):

CT = | YB – YA | / YA 100 (%)

Where:

YA = Luminance of measured location without gray level 0 pattern (cd/m2) YB = Luminance of measured location with gray level 0 pattern (cd/m2)

Note (6) Measurement Setup:

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature

change during measuring. In order to stabilize the luminance, the measurement should be executed

after lighting Backlight for 1 hour in a windless room.

Note (7) Definition of White Variation (W):

Measure the luminance of gray level 255 at 5 points

W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

Active Area

(D/4,W/4)

(0, 0) YB, U (D/2,W/8)

YB, R (7D/8,W/2)

YB, D (D/2,7W/8)

YB, L (D/8,W/2)

(D,W)

Gray 128

Gray 0

Active Area YA, U (D/2,W/8)

YA, R (7D/8,W/2)

YA, D (D/2,7W/8)

YA, L (D/8,W/2)

(0, 0)

(D,W)

Gray 128

(3D/4,3W/4)

LCD Module

LCD Panel

Center of the Screen Display Color Analyzer (Minolta CA210)

Light Shield Room

(Ambient Luminance < 2 lux)


Approval

Version 2.1

18

D

W

Active Area

Verti

cal L

ine

Horizontal Line

: Test Point

X=1 to 5

5

1 2

3 4

D/4 D/2 3D/4

W/4

W/2

3W/4

X


Approval

Version 2.1

19

8. DEFINITION OF LABELS 8.1 OPEN CELL LABEL

The barcode nameplate is pasted on each open cell as illustration for CMO internal control.

8.2 CARTON LABEL The barcode nameplate is pasted on each box as illustration, and its definitions are as following explanation

(a) Model Name: V216B1-P01

(b) Carton ID: CMO internal control

(c) Quantities: 30

(d) Production Location:XXXX, for example:TAIWAN or CHINA .

V216B1-P01

XXXXXXXXXXXX

P.O. NO.

Parts ID.

Carton ID. Quantities 30 XXXXXXXXXXXXXX

Made in XXXX


Approval

Version 2.1

20

9. packaging 9.1 packing specifications

(4) 27 LCD TV Panels / 1 Box (5) Box dimensions : 640(L) x 490(W) x 320(H) mm (6) Weight : Approx.24.2Kg

9.2 packing Method

Figures 9-1 and 9-2 are the packing method

Figure.9-1 packing method


Approval

Version 2.1

21

Film

Film

PE Sheet

PP Belt

Carton Label

Film

PP Belt

Carton Label

PE Sheet

Film

PP Belt

Carton Label

PE Sheet

Figure.9-2 packing method


Approval

Version 2.1

22

10. PRECAUTIONS 10.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) Do not apply rough force such as bending or twisting to the product during assembly.

(2) To assemble backlight or install module into user’s system can be only in clean working areas. The dust

and oil may cause electrical short or worsen the polarizer.

(3) It’s not permitted to have pressure or impulse on the module because the LCD panel will be damaged.

(4) Always follow the correct power sequence when the product is connecting and operating. This can

prevent damage to the CMOS LSI chips during latch-up.

(5) Do not pull the I/F connector in or out while the module is operating.

(6) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and

easily scratched.

(7) It is dangerous that moisture come into or contacted the product, because moisture may damage the

product when it is operating.

(8) High temperature or humidity may reduce the performance of module. Please store this product within

the specified storage conditions.

(9) When ambient temperature is lower than 10ºC may reduce the display quality. For example, the

response time will become slowly.

10.2 SAFETY PRECAUTIONS (1) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case

of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

(2) After the product’s end of life, it is not harmful in case of normal operation and storage.

刪除: The startup voltage

of Backlight is

approximately 1000 Volts.

It may cause electrical

shock while assembling

with inverter. Do not

disassemble the module or

insert anything into the

Backlight unit.


Approval

Version 2.1

23

奇美電子股份有限公司

11. Mechanical Drawing

SHENZHEN ACT INDUSTRIAL CO., LTD.

Model No.: AIP4904002A-G Rev.:V0.1 2009-4-21 Page 1 of 19

承认书

SPECIFICATION FOR APPROVAL

客户名称（CUSTOMER）：彩迅

客户料号（CLIENT P/N）： TBD

客户品名（DESCRIPTION）： TBD

A C T 品名（MODEL）： AIP4904002A-G

日期（DATE）： 2009-4-21

承认签章后请回传

Please return to us one copy of “SPECIFICATION FOR APPROVAL”

with your approved signatures

承认书 APPROVED SIGNATURES

客户承认(CUSTOMER APPROVAL) 安科讯公司承认（ACT APPROVAL）

工程师

ENGINEER

审核

CHECKED BY

批准

APPROVAL BY

工程师

ENGINEER

审核

CHECKED BY

批准

APPROVAL BY

盖章签署

(CHOP&SIGNATURES)

盖章签署

(CHOP&SIGNATURES)

日期（DATE）日期（DATE）

深圳市安科讯实业有限公司

SHEN ZHEN ACT INDUSTRIAL CO.,LTD.

中国广东省深圳市盐田区北山道北山工业区 5号楼

NO.5 Building, Beishan Industrial Park,

Beishan Road, Yantian District, Shenzhen, Guangdong, China

Tel：86-755-25558506 25558255 25552808

Fax：86-755-25558229 P.C.：518083

E-mail: [email protected] [email protected]

Web: www.szaction.com

G

xiaojin

新建图章

lixh

李小辉



目录 Catalog

变更履历表 ......................................................................................................................................................................4

1. 导言 Introduction........................................................................................................................................................5

1.1 电源概况 Power Supply Overview........................................................................................................................5

1.2 支持文件 Applicable Documents..........................................................................................................................5

2. 主要元器件 Key Components ...................................................................................................................................6

3. 电气规格 Electrical Specification ................................................................................................................................6

3.1 开关电源部分 Switching Power Supply Parts.......................................................................................................6

3.1.1 输入电压 Input Voltage ..........................................................................................................................6

3.1.2 输入频率 Input Frequency......................................................................................................................6

3.1.3 冲击电流 Inrush Current ........................................................................................................................6

3.1.4 待机功耗 Standby Input Power ................................................................................................................6

3.1.5 最大输入电流 Input Current Limiting .......................................................................................................6

3.1.6 效率 Efficiency ........................................................................................................................................7

3.1.7 电压调整率 DC Voltage Regulation .........................................................................................................7

3.1.8 输出电流 DC Output Current ...................................................................................................................7

3.1.9 输出纹波与噪声 Output Ripple and Noise ...............................................................................................7

3.1.10 输出动态负载响应 Output Dynamic Load Response ...............................................................................8

3.1.11 电压过冲 Overshoot at turn-on/ turn-off ....................................................................................................8

3.2 保护功能 Protection Function ..............................................................................................................................8

3.2.1 过压保护 Over Voltage Protection ............................................................................................................8

3.2.2 短路保护 Short Circuit Protection.............................................................................................................8

3.2.3 过流保护 Over Current Protection ............................................................................................................9

3.3 时序特性 Timing.................................................................................................................................................9

3.3.1 保持时间 Hold up Time ...........................................................................................................................9

3.3.2 启动时间 Start up Time ...........................................................................................................................9

3.4 逆变器部分 Inverter Parts..................................................................................................................................9

3.4.1 输入特性 Input Characteristic .................................................................................................................9

3.4.2 输出特性 Output Characteristic.............................................................................................................10

4 环境要求 Environment Requirement .........................................................................................................................10

4.1 温度 Temperature ..............................................................................................................................................10

4.2 湿度 Humidity ....................................................................................................................................................10

4.3 高度 Altitude .....................................................................................................................................................10



5 可靠性 Reliability ..................................................................................................................................................... 11

5.1 可靠性试验 Reliability Test ............................................................................................................................... 11

5.2 平均无故障间隔时间 MTBF ............................................................................................................................ 11

5.3 老化寿命测试 Burn-in and Life test ................................................................................................................... 11

6 产品安规要求 Product Safety Requirement .............................................................................................................. 11

6.1 标准 Standard ................................................................................................................................................... 11

6.2 接触电流 Leakage Current ................................................................................................................................ 11

6.3 绝缘强度 Dielectric Strength Testing ..................................................................................................................12

6.4 绝缘阻抗 Insulation Resistance ........................................................................................................................12

7 结构尺寸 Mechanical Dimensions ............................................................................................................................12

7.1 结构尺寸 Mechanical Dimensions......................................................................................................................12

7.2 结构图 Mechanical Appendix .............................................................................................................................12

7.3 AC输入端子 AC Connector ..............................................................................................................................13

7.4 DC输出端子 DC Connector ..............................................................................................................................13

8 包装 Packing ...........................................................................................................................................................13

9 品质担保 Quality Assurance Provision ......................................................................................................................15

9.1 服务承诺 Service ..........................................................................................................................................15

9.2 器件更改 Component Change ...........................................................................................................................15

10 主要测试设备 Major Test Equipment ......................................................................................................................16

11 出货检验标准 Inspection Standards .......................................................................................................................16

12 声明 Statement .......................................................................................................................................................16

关键器件清单 ................................................................................................................................................................17

样机图片 ........................................................................................................................................................................19



变更履历表 Revision History

Spec.版本 Spec. Edition

发行日期 Release Date

修改内容 Modified content

产品版本 Product Edition

V0.1 2009-4-21 初版 Initial V0.1



1. 导言 Introduction

1.1 电源概况 Power Supply Overview

本产品为 LCD二合一电源，适用于彩迅 19寸 LCD TV。

This product is PI power for LCD, and adapts to 19” LCD TV of caixun.

1.2 支持文件 Applicable Documents

本产品验证测试过程中遵循并选用以下标准（但不局限于）：

The products choose the standards as following for design verification test (No limited).

GB/T 2423.1-01电工电子产品基本环境试验规程试验 A：低温试验方法 Basic environmental testing procedures for electric and electronic products Tests A: Cold

GB/T 2423.2-01 电工电子产品基本环境试验规程试验 B：高温试验方法 Basic environmental testing procedures for electric and electronic products Tests B: Dry heat

GB/T 2423.3-93 电工电子产品基本环境试验规程试验 Ca：恒定湿热试验方法 Basic environmental testing procedures for electric and electronic products Test Ca: Damp heat, steady state

GB/T 2423.4-93 电工电子产品基本环境试验规程试验 Db：交变湿热试验方法 Basic environmental testing procedures for electric and electronic products Test Db: Damp heat cyclic

GB/T 2423.5-95 电工电子产品环境试验第 2部分：试验方法试验 Ea和导则：冲击 Environmental testing for electric and electronic products. Part 2: test methods. Test Ea and guidance: Shock

GB/T 2423.6-95 电工电子产品环境试验第 2部分：试验方法试验 Eb和导则：碰撞 Environmental testing for electric and electronic products. Part 2: Test methods. Test Eb and guidance: Bump

GB/T 2423.8-95 电工电子产品环境试验第 2部分：试验方法试验 Ed和导则：自由跌落 Environmental testing for electric and electronic products. Part 2: Test methods. Test Ed: Free fall

GB/T 2423.10-95 电工电子产品环境试验第 2部分：试验方法试验 Fc和导则：振动（正弦） Environmental testing for electric and electronic products. Part 2: Test methods. Test Fc and guidance:

Vibration(Sinusoidal) GB/T 2423.11-97 电工电子产品环境试验第 2部分：试验方法试验 Fd和导则：宽频带随机震动——一

般要求 Environmental testing for electric and electronic products. Part 2: Test methods. Test Fd: Random Vibration wide

band_ general requirements. GB/T 2423.22-87 电工电子产品基本环境试验规程试验 N：温度变化试验方法

Basic environmental testing procedures for electric and electronic products. Test N: Change of temperature GB8898-2001（音频、视频及类似电子设备安全要求）要求。

(Audio, video and similar electric apparatus –safety requirement) GB 17625.1-2003 低压电气及电子设备发出的谐波电流限值（设备每相输入电流≤16A）

The limits for the harmonic current emissions caused by low-voltage electrical and electronic equipments(equipment input current≤16A per phase)

GB/T 17626.2-1998 电磁兼容试验和测量技术静电放电抗扰度试验 Electromagnetic compatibility-Testing and measurement techniques-Electrostatic discharge immunity test

GB/T 17626.4-1998 电磁兼容试验和测量技术电快速瞬变脉冲群抗扰度试验 Electromagnetic compatibility-Testing and measurement techniques-Electrical fast transient/ burst immunity test

GB/T 17626.5-1998 电磁兼容试验和测量技术浪涌（冲击）抗扰度试验 Electromagnetic compatibility-Testing and measurement techniques-Surge immunity test GB/T 17626.11-1998 电磁兼容试验和测量技术电压暂降、短时中断和电压变化的抗扰度试验

Electromagnetic compatibility-Testing and measurement techniques-Voltage dips, short interruptions and voltage variations immunity tests



2. 主要元器件 Key Components

关键元器件信息参考附件关键器件清单.

Refer to appendix of key components information.

3. 电气规格 Electrical Specification

3.1 开关电源部分 Switching Power Supply Parts

3.1.1 输入电压 Input Voltage

表格 2 ：列举 AC输入电压范围，在此电压范围内，电源应正常工作并符合所有电气性能要求。

Table 2: Lists the AC input operating voltage range. The power shall work normally and meet all electrical requirements throughout this range.

表格 2：AC 输入电压限值 Table 2: AC Input Voltage Limitations

最小值 Minimum 额定值 Nominal 最大值 Maximum

90Vac 100Vac-240Vac 264Vac

3.1.2 输入频率 Input Frequency

表格 3 ：列举 AC输入频率范围，在此频率范围内，电源应正常工作并符合所有电气性能要求。

Table 3: Lists the AC input operating frequency range. The power shall work normally and meet all electrical requirements throughout this range.

Table 3: AC Input Frequency Limitations 表格 3：AC 输入频率限值

最小值 Minimum 额定值 Nominal 最大值 Maximum

47Hz 60Hz/50Hz 63Hz

3.1.3 冲击电流 Inrush Current

冲击电流峰值在冷启动（25）时，不大于 60A;且在任何负载和输入条件下，不导致永久性损坏或

危险，输入电压的定义见表格 2.

Peak inrush current shall be limited to 60A cold start at 25 degrees C, and shall not result in a permanent damage of the power supply under any conditions of load and input voltage as specified at any input voltage as specified in table 2.

3.1.4 待机功耗 Standby Input Power

在 230Vac/50Hz输入电压，+12V加 45mA电流，待机功耗不大于 1W。

The standby input power should no more than 1W under the 230Vac/50Hz input（12V/45mA）.

3.1.5 最大输入电流 Input Current Limiting

在输入电压最小值，负载为满载条件下，最大输入电流不大于 1.4A。

The input current should no more than 1.4A, under minimum input and full load.



3.1.6 效率 Efficiency

在 230Vac/50Hz输入电压，最大负载和额定负载条件下，电源的效率大于 80%.

The power supply efficiency shall be greater than 80% under 230Vac/50Hz input. It will be measured at the maximum load and typical load.

3.1.7 电压调整率 DC Voltage Regulation

在输出端子量测的电压需符合表格 4中标示的调整范围。

电压调整的限值不包括 3.1.10节中要求的 DC 负载瞬态变化。

The DC output voltages will remain within the regulation ranges shown in Table 5 when measured ate the load end of the output connectors.

The voltage regulation limits do not include the transient DC load changes, which are covered in Section 3.1.10.

表格 4：输出电压调整限值 Table 4: DC Output voltage regulation limits

Parameter

参数

Line Regulation

源效应调整

Load regulation

负载调整

Cross regulation

交叉调整

V1:12V ±1% ±5% -

3.1.8 输出电流 DC Output Current

表格 5：输出电流限值 Table 5: DC output current limits

Parameter

参数

Min.

最小值

Typ.

典型值

PEAK

峰值

Unit

单位

V1:12V 0.045 4.0 5.0 A

3.1.9 输出纹波与噪声 Output Ripple and Noise

下面表格 6是纹波与噪声要求，以 3.1.8节中定义的负载范围和 3.1.1节定义的输入电压为测试条

件，纹波与噪声均应符合要求，测试时示波器设置为 20MHz带宽，输出端并接一 0.1uF瓷片电容和一

10uF钽电解电容（低 ESR值）。

The following table 6 is output ripple and noise requirements, it will be met throughout the load ranges specified in Section 3.1.8 and under all input voltage conditions as specified Section 3.1.1, Measurements will be made with an oscilloscope set to 20MHz bandwidth limit. The outputs will be bypassed with one 0.1uF multilayer (type X7R) and one 10uF tantalum electrolytic (low ESR) capacitors.

表格 6：纹波与噪声限值 Table 6: Output ripples and noise limits

参数 Parameter 最大值 Max.

V1:12V 120mVp-p@25

200mVp-p@0



3.1.10 输出动态负载响应 Output Dynamic Load Response

输出电压在下列表格 7定义的负载变化时，符合规格要求，负载变化率为 0.1Amps/uS, 50Hz~10 KHz

之间。

The output voltages will remain within specified regulation limit of the nominal set voltage for changes in load as specified below under the following load steps defined below table 7. At a slew rate of 0.1Amps/uS between 50Hz to 10 KHz.

表格 7：输出动态负载响应限值

Table 7: Output dynamic load response limits

Dynamic Load 动态负载 DC Voltage Regulation 电压调整率

10%~100%~10% ≤±10%

10%~50%~10% ≤±5%

50%~100%~50% ≤±5%

3.1.11 电压过冲 Overshoot at turn-on/ turn-off

开机或关机时，电压过冲不得超过稳定值 10% .

Any overshoot at turn on or turn off shall be less than 10% of rated output voltage.

3.2 保护功能 Protection Function

3.2.1 过压保护 Over Voltage Protection

电源提供的过压保护，详细定义如下表：

The power supply will provide for over voltage protection as defined below.

表格 8：过压保护限值 Table 8: Over Voltage Protection limits

Parameter

参数

Min.

最小

Max

最大值

Unit

单位

V1:12V 15 23 VDC

3.2.2 短路保护 Short Circuit Protection

输出的短路定义为其输出阻抗小于 0.1欧姆，在上述 3.1节中定义的输入条件下，电源将进行保护，

保护过程中，不会出现诸如元器件、连接器等损坏危险。

An output short circuit is defined as any output impedance of less than 0.1 ohms. The power supply will protect without damage to overseers of to the unit (components, connectors, etc) under the input conditions specified in Section 3.1 above.



3.2.3 过流保护 Over Current Protection

电源具备过流保护功能，并在保护过程中无危险和损坏，在保护去除后，电源自动恢复其功能。

The power supply has OCP function, and without any damage during test, the unit shall recovery and functions automatically after the protection is removed.

输出 output 最小过流点 Min. current

最大过流点 Max. current

单位 unit

V1(12V) 4.8 7.2 A

3.3 时序特性 Timing

3.3.1 保持时间 Hold up Time

满载条件下，电源保持时间在 110Vac 输入时，保持时间不小于 8mS； 220Vac 输入时，保持时

间不小于 20mS。

Hold-up time no less than 8mS at 110Vac input and no less than 20mS at 220Vac input, the output loading should be set up with full load during the test.

3.3.2 启动时间 Start up Time

满载条件下，电源启动时间在 110Vac 输入时，启动时间不大于 3秒, 220Vac 输入时，启动时间

不大于 1.5秒。

Start up time no more than 3 seconds at 110Vac input and no more than 1.5second at 220Vac, the output loading should be set up with full load during the test.

3.4 逆变器部分 Inverter Parts

3.4.1 输入特性 Input Characteristic

表格 10 输入特性 Table 10 Input characteristic

参数 Parameter

标示符号 Symbol

最小值 Min.

典型值 Typical

最大值 Max.

单位 Unit

备注 Remarks

输入电压 Input Voltage Vin 10.8 12 13.2 VDC

亮度控制电压 Brightness Control Voltage BKLT-ADJ 0 - 5 V

Bright(max)=0V Bright(min)=5V

2.4 - 5.0 V ON 开关控制电压

ON/OFF Control Voltage BKLT-EN 0 - 1.2 V OFF

输入电流变化范围 Iin - 1.8 - A



3.4.2 输出特性 Output Characteristic

表格 11 输出特性 Table 11 Output Characteristic

参数 Parameter

标示符号 Symbol

最小值 Min.

典型值 Typical

最大值 Max.

单位 Unit

备注 Remarks

6 7 8 ADJ=0V 输出电流 Output Current

Io 2 3 4

mA（rms） ADJ=5V

Vs 1000 - 2300 V（rms） Load: Open 25 开路电压 Kickoff Voltage Vs 1300 - - V（rms） Load: Open 0

启动时间 Start-up Time

Ts 1 - 2 Sec -

频率/Frequency F 40 50 60 KHz -

效率/Efficiency η 65 N/A N/A % 用屏做负载

4 环境要求 Environment Requirement

4.1 温度 Temperature

工作环境温度: 0~ 50

Operating Ambient: 0~ 50

贮存环境温度: -25~ +80

Non-operating Ambient: -25~ +80

4.2 湿度 Humidity

工作时: 10%~90%相对湿度（非冷凝）

Operating: 10%~90% relative humidity (Non- condensing)

贮存时： 10%~90%相对湿度（非冷凝）

Non-operating: 10%~90% relative humidity (Non- condensing)

4.3 高度 Altitude

工作时：2000米

Operating: 2000 meters

贮存时：2000米

Non-operating: 2000meters



5 可靠性 Reliability

5.1 可靠性试验 Reliability Test

表格 12：可靠性试验项目 Table 12: Reliability test items

试验项目 Test Item

试验条件 Test conditions

数量 Test quantity

高温储存 Storage at high temperature test +80 16Hrs 2 Pcs

低温储存 Storage at low temperature -25 16Hrs 2 Pcs

高温工作 Operating at high temperature test +50 24Hrs 2 Pcs

低温工作 Operating at low temperature test 0 24Hrs 2 Pcs

低温启动试验 Low Temperature turn on test

在0下存放2小时后按最小输入电压、满载条件进行启动，EUT工作正常。 EUT should start-up normally after storage at 0 of 2 hours under minimum input voltage and maximum load.

2 Pcs

热循环试验 thermal circle test

0(30min)——50(30min)——0(30min) 连续工作4个周期

Continually work 4 cycles 2 Pcs

恒温恒湿试验/Constant temperature and humidity test

+50 90%RH 连续工作24小时 +50 90%RH, continually operating 24 hours

2 Pcs

5.2 平均无故障间隔时间 MTBF

25环境温度，满载条件，额定电压输入条件，平均无故障间隔时间≥100K 小时(MIL-HDBK-217F)。

MTBF no less than 100K hours (25 degrees C, Full load and rated voltage input, MIL-HDBK-217F)

5.3 老化寿命测试 Burn-in and Life test

ACT将与客户评估并确认电源产品室内老化寿命测试过程。

ACT shall discuss with customer to maker sure the power in house Burn-In and life test procedures.

6 产品安规要求 Product Safety Requirement

6.1 标准 Standard

遵循 IEC60065（音频、视频及类似电子设备安全要求）要求。

Meet IEC60065 (Audio, video and similar electric apparatus -safety requirement) standard requirement.

6.2 接触电流 Leakage Current

接触电流不得超过 3.5mA (230Vac/50Hz)。

Leakage current shall not exceed 3.5mA at 230Vac/50Hz.



6.3 绝缘强度 Dielectric Strength Testing

绝缘强度满足下表的要求，100% 在线产品执行此项测试，并每一项目至少保持 3S时间，无任何故障。

Hi-pot test shall be met the table 13 requirements, an item listing this test as a 100% production test must be performed and be maintained at that level for a minimum of 3 seconds without failure.

表格 13：耐压测试 Table 13: Hi-pot test

项目 Item

规格要求 Specification

备注 Remark

输入-----输出 Primary to Secondary 3.0KVac <10mA

输入-----地 Primary to P.G 1.5KVac <10mA

输出-----地 Secondary to P.G - -

无飞弧 No arcing 无击穿 No broken

6.4 绝缘阻抗 Insulation Resistance

初级对次级：≥50M欧姆，500VDC

-Primary to Secondary: 50 Meg. Ohms min. 500VDC

注：测试条件：常温，湿度小于 75%.

7 结构尺寸 Mechanical Dimensions

7.1 结构尺寸 Mechanical Dimensions 147mm*110mm*23mm (L*W*H)

7.2 结构图 Mechanical Appendix



7.3 AC输入端子 AC Connector

PIN NO. 定义

1 L (AC Line,100~240Vac,50/60Hz)

2 G(GND,0V)

3 N (AC Line,100~240Vac,50/60Hz)

7.4 DC输出端子 DC Connector

8 包装 Packing

若客户未提出包装方式时，均使用安科讯公司之包装方式 Unless specially requirement of customer, the packing according to ACT company style.

8.1 内包装: 防静电袋 Inner package: static-free bag.

8.2 外包装: 纸箱 Outer package: paper-box.

8.3 外包装箱标识: 客户、订单号、品名、数量、日期等信息 Outer package notes include the information: Customer Name, LOT Number, Model No., Date, and so on.

PIN NO. 定义

1 12V(11.4-12.6V)

2 12V(11.4-12.6V)

3 +5V(NC)

4 +5V(NC)

5 GND(0V)

6 GND(0V)

7 ON/OFF(0-1.2V INVERTER OFF,2.4-5.0V INVERTER ON)

8 ADJ(0-5VDC,0V亮度最大，5V亮度最小)



9 品质担保 Quality Assurance Provision

9.1 服务承诺 Service

1. 本公司确保全部产品合格及正常运行，并按照此规格书要求接受客户进货检验。如发现不符合技

术要求的产品(另行协商项目除外)，客户可将当日进货之相同批号产品退回安科讯公司。若在生产线上发

现不良现象，可于允收日起 30 日内向安科讯公司要求交换，但若不良之原因为客户生产线上所造成则不

适用此条款。

ACT Company is responsible for the quality control of all the products, and customer should check the products by this specification. The products (same Lots) could be returned to ACT Company if the products function were not meet customer requirement (unless any situations of discussion projects). When any failures were found in product line, customer can require change the products in 30 days to ACT Company, but the problem cause by the customer are not fit to this.

2. 安科讯公司供方对相关产品提供壹年保修，自出厂之日计。在此期间内，对于非人为因素导致故障的产品，给予免费维修或更换(收到故障品2周内)；超出保修期时间内，或人为因素导致故障的产品，本公司可酌情提供相应维护，需方承担维修材料及相应费用.

ACT Company promises one-year warranty for the products after service and would afford maintained service or substitute the fault products in 2 weeks (after received the products) if the failure reason were no by improper operation without cost. Otherwise if the fault products were over warranty period or caused by improper operation, ACT company also would afford the service but to take the maintain fee or material fee is requirement.

9.2 器件更改 Component Change

1. 因设计或工程变更而影响产品性能和品质时，必需提供相关文件，经由双方确认后方能生产，并需将变更后之规格书或图面附于规格书后，且追加标记。

When the production performance and quality are affected by the design or engineering modification, ACT Company need supply corresponding files and produce productions after discussion with customer. The modified specifications or diagrams must be enclosed and marked at new specifications’ book.

2. 当客户设计或制程需有所变更时，需由客户通知厂商做变更，并经由双方同意后方能生产，以确保制程的稳定及产品品质。

When customer needs to modified the design or the process, to notice ACT Company about the information is requirement. In order to guarantee the products quality and the process stability, ACT should be performed the modified contents after discussion together and agreement.

3. 元器件若有更改需求，需事先得到客户的承认。

Substitution may be made for parts, but prior to customer’s approval is requirement for any component change.



10 主要测试设备 Major Test Equipment

10-1 交流输入电源 AC SOURCE: CHROMA 61602 10-2 电源功率计/ POWER METER: PF9800 10-3 电子负载/ ELECTRONIC LOAD: CHROMA 6312 10-4 示波器/ OSCILLOSCOPE: Tektronix TDS 1012 10-5 万用表/ MULTIMETER: Fluke 45 10-6 直流输入电源/ DC POWER: TPR-3003-2D 10-7 耐压测试仪/ HI-POT TESTER:GOODWILL GPT-605 10-8 多路温度测试仪/Multi-routes temperature test instrument: WeiGe DWC2515 10-9 恒温恒湿箱 LOW AND HIGH TEMPERATURE ENVIRONMENT ALTERNATION TEST CHAMBER: TERCHY MHU-1000A

11 出货检验标准 Inspection Standards

表格 14 出货检验要求 Table 14 Inspection Requirement

NO. 检查项目 Test project

检验标准 Test standard

抽样水准 Sample Level

检验水准 Test standard

1 电气性能 Performance

严重缺点：CR=0 Serious defect: CR=0

2 尺寸 Size

主要缺点：AQL=0.65 Main defect: AQL=0.65

3 外观、包装 Shell , Package

GB2828-2003 II

次要缺点：AQL=1.0 Petit defect: AQL=1.0

12 声明 Statement

12-1 本承认书解释权归深圳市安科讯实业有限公司。 All rights reserved by Shenzhen ACT Industrial Co., Ltd. for all of this specification for approval.

12-2 本承认书一式两份，客户一份，供应商一份，自双方确认签字之日起生效。 This specification for approval has two copies, one for customer, and the other for provider. It comes into effect after approval this specification by customers.

12-3 如有更新，需由双方协商解决，另行补充。 If specification for approval needs to update, it’s made an agreement after discuss between customer and provider.



关键器件清单

基本标识品牌标识

5R/3A MF72 5D9 - 时恒

5R/3A MF72 5D9 - 裕合

82UF/400V 82UF 400V CapXon CAPXON

82UF/400V 82UF 400V THICON 万捷

82UF/400V 82UF 400V XUNDA 讯达

10UF/50V 10UF 50V XUNDA 讯达

10UF/50V 10UF 50V - 中怡达



470UF/25V 470UF 25V - 讯达

470UF/25V 470UF 25V - 中怡达

680uF/25V 680uF 25V CapXon CAPXON

680uF/25V 680uF 25V - 中怡达

680uF/25V 680uF 25V XUNDA 讯达

0.47uF 280V(UL:E246678) .47k 280V MPX/MKP 塑镕

0.47uF 275V(UL:E120045) .47k 275V MPX 凯励

0.47uF 275V(UL:E320206） .47k 275V MPX 万明

0.47uF 275V(UL:E183780） .47k 275V HQX 昱电

1000pF 250V (UL:E221839) 102M 250V STE CD 松田

1000pF 250V (UL:E114280) 102M 250V SE 成功

1000pF 250V (UL:E208107) 102M 250V HJ 万明

102K/1KV 102 1KV - 成功

102K/1KV 102 1KV - 松田

102K/1KV 102K 1KV - 万明

2200pF 250V(UL:E221839) 222M 250V HJ 万明

2200pF 250V(UL:E114280 ) 222M 250V SE 成功

2200pF 250V(UL:E208107 ) 222M 250V STE CD 松田

5PF/6KV 5 6KV - 万明

5PF/6KV 5 6KV - 成功

5PF/6KV 5 6KV - 松田

No. 物料名称规格本体外观标识

供应商位号单位用量

1

2 电解电容 C107 PCS 1

1 热敏电阻 THR101 PCS

1

4 电解电容 C206/C206A PCS 2

3 电解电容 C122 PCS

3

6 安规电容 CX101 PCS 1

5 电解电容 C118/C104A/C104 PCS

2

8 瓷片电容 C101 PCS 1

7 瓷片电容 CY101/CY102 PCS

1

10 高压电容 C213/C214 PCS 2

9 Y1电容 CY103 PCS



基本标识品牌标识

222J/630V 2J222J - 塑镕

222J/630V 2J222J - 万明

MBR20100CTG B20100G ON ON

SBR20100 B20100 - DIODES

600V/2A RL205 "Hg" 华高

600V/2A RL205 "HG" 文德

600V/2A RL205 PY 平洋

FR107 FR107 "HG" 文德

FR107 FR107 "Hg" 华高

1000V/2A FR207 "Hg" 华高

1000V/2A FR207 "HG" 文德

1000V/2A FR207 PY 平洋

AZ431AZ AZ431AZ-AE1 BCD BCD

TL431A TL431A EST EST

FQPF8N60C FQPF8N60C - FAIRCHILD

STM STP8NK60ZFP 8NK60 ST ST

STK0860F STK0860F AUK AUK

EL-817 (UL:E214129) 817 EL EVERLIGHT

LTV-817 (UL:E113898) 817 L LITEON

BPC-817 (UL: E236324) 817 _ Bright LED

H11A817 (UL: E90700) 817 - FairchildSemiconductor

K1010 (UL: E169586) 1010 - COSMO

250V 3.15A T3.15A 250V 3K 良胜

250V 3.15A T3.15A 250V 32S 宁利

B3942 B3942 - BITEK

AP4511GM 4511GM - APEC

AO4606 AO4606 - ALPHA＆OMEGA

SP5005（SOP16） SP5005 SP 硅动力

BIT3713（SSOP16） BIT3713 BITEK BITEK

R7731 R7731 - 立琦

SD4563 SD4563 - 光大

OB2263 OB2263 - 昂宝

No. 物料名称规格本体外观标识

供应商位号单位用量

1

12 二极管 D105 PCS 1

11 聚酯膜电容 CX102 PCS

4

14 二极管 D101 PCS 1

13 二极管BD101A/BD101B/BD

101C/BD101D PCS

1

16 带隙稳压源 U103 PCS 1

15 二极管 D103 PCS

1

18 光电耦合器 U102 PCS 1

17 场效应管 Q101 PCS

1

20 场效应管 Q204/Q205 PCS 2

19 保险管 F101 PCS

1

22 SMD/IC U101 PCS 1

21 SMD/IC U201 PCS



样机图片

零件面

焊锡面

主板型号:CX-MST106-V3.0 Date:2009-10-21

序号代码物料名称规格型号单位数量位号

1 T15.011060-03R PCB板CX-MST106-V3.0 双面

板,FR4(234.8*126.3mm) ROHSPCS 1 PCB

集成块 24C02 SOP-8 ROHS PCS 1 U12 需要烧录HDMI EDID CODE

集成块 24C02 SOP-8 ROHS PCS 1 U6 需要烧录VGA DDC

3 T06.100B32-00R 集成块 EN25F32-100HIP PCS 1 U24 需要烧录程序

4 T06.102404-00R 集成块 24C04 SOP-8 ROHS PCS 1 U21

5 T06.100106-CHR 集成块 MSD106CHL QFP256 SMD ROHS PCS 1 U2 主芯片

6 T06.101117-18R 集成块 AP1117-18 SOT-223 不可调 ROHS PCS 1 U11

7 T06.101117-33R 集成块 AP1117-33 SOT-223 不可调 ROHS PCS 1 U16

8 T06.107314-00R 集成块 IRF7314 SOP-8 ROHS PCS 1 U5

9 T06.101117-00R 集成块 AMS1117-adj SOT-223 可调 ROHS PCS 1 U28

10 T06.109425-00R 集成块 W9425G6EH-4,256M,TSOP66,ROHS PCS 1 U9

11 T06.106353-00R 集成块 CE6353 QFP64 ROHS PCS 1 U14

12 T06.109410-00R 集成块 EC9410 SOP-8 ROHS PCS 1 U15

13 T06.104558-00R 集成块 LM4558 SOP-8 ROHS PCS 1 U33

14 T06.107805-00R 集成块 LM7805 TO-252 ROHS PCS 1 U18

15 T06.209650-00R 集成块 D9650H SAWFB1 ROHS PCS 1 U23

16 T06.203953-00R 集成块 K3953D SAWFB1 ROHS PCS 1 U29

17 T06.101084-33R 集成块 AMS1084-3.3 TO-263 ROHS PCS 1 U30

18 T06.101517-00R 集成块功放TDA1517 DIP18 3W+3W PCS 1 U31

19 T06.100407-00R 集成块 R2S10407 SOP-24 ROHS PCS 1 U26

20 T12.XF1GA0-00R 高频头XF-1GA(DVB-T、PAL、SECAM)ROHS

PCS 1 U20

21 T04.8099DW-00R 贴片二极管 Bav99w SOT-363 ROHS PCS 4 DD24,DD25,DD26，D62

22 T04.800099-00R 贴片二极管 Bav99 SOT-23 ROHS PCS 2 DD30,DD32

23 T04.800054-0CR 贴片二极管 BAT54C,SOT-23 ROHS PCS 2 DD39,DD48

24 T04.805819-00R 贴片二极管 1N5819,SMD,DO-214,ROHS PCS 1 D3

25 T04.800277-52R 贴片二极管 BA277,SMD,SOD523,ROHS PCS 1 D66

26 T05.203904-00R 贴片三极管 NPN,MMBT3904,SMD,SOT-23,ROHS PCS 18 Q6,Q7,Q9,Q11,Q12,Q14,Q24,Q26,Q27,Q29,Q31,Q42,Q44,Q45,Q54,Q55,Q57.Q23

27 T05.203906-00R 贴片三极管 PNP,MMBT3906,SMD,SOT-23,ROHS PCS 3 Q22,Q32,Q41

28 T05.207002-00R MOS管 2N7002 SMD,SOT-23,ROHS PCS 1 Q56

29 T03.134700-12R 贴片磁珠 FB DCR=0.7Ω-3A(1206),ROHS PCS 22 L2,L4,L5,L10,L19,L30,L32,L34,L38,L40,L83，L3,L20，L16,L23,L47,L55,F3,L1,D8,L22,L25

30 T03.134700-06R 贴片磁珠 FB DCR=0.7Ω-1A(0603),ROHS PCS 17 L6,L7,L9,L17,L18,L31,L74，L11,L12,L13,L24,L28,L29,L45,L66,L68,L73

31 T03.504150-10R 贴片电感 15uH/1A DR105-SERIES ROHS PCS 1 L8

32 T01.365000-06R 贴片电阻 0Ω 0603 1/16W ±5% ROHS PCS 18 R3,R113,R154,R156,R282,R297,R355,R371,R382,R387,R374,R70,R291,R295,R285,R298,R322,R325

33 T01.365100-06R 贴片电阻 10Ω 0603 ±5% ROHS PCS 14 R54,R133,R135,R136,R137,R139,R140,R141,R142,R143,R146,R284,R230,R417

34 T01.365121-06R 贴片电阻 120Ω 0603 ±5% ROHS PCS 3 R63,R40,R42

35 T01.365470-06R 贴片电阻 47Ω 0603 ±5% ROHS PCS 20 R28,R29,R33,R45,R48,R51,R81,R83,R84,R90,R91,R92,R123,R130,R131,R132,R434,R459,R504,R505

36 T01.365750-06R 贴片电阻 75Ω 0603 ±5% ROHS PCS 18 R30,R31,R35,R46,R50,R53,R62,R86,R87,R88,R110,R128,R129,R235,R236,R246,R232,R506

T06.102402-00R2

拟制: 审核: 1/5



37 T01.365101-06R 贴片电阻 100Ω 0603 ±5% ROHS PCS 30R21,R103,R105,R111,R114,R165,R166,R167,R249,R274,R278,R294,R305,R311,R338,R388,R76,R176,R312,R316,R358,R359,R401,R402,R403,R425,R426,R428,R476,R715

38 T01.365153-06R 贴片电阻 15k 0603 ±5% ROHS PCS 1 R60

39 T01.365560-06R 贴片电阻 56Ω 0603 ±5% ROHS PCS 8 R72,R73,R104,R117,R118,R390,R395,R396

40 T01.365471-06R 贴片电阻 470Ω 0603 ±5% ROHS PCS 6 R56,R79,R138,R256,R317,R323,

41 T01.365102-06R 贴片电阻 1K 0603 ±5% ROHS PCS 20 R16,R24,R26,R27,R47,R107,R116,R157,R175,R178,R260,R286,R320,R420,R452,R658,R427,R429,R321,R367

42 T01.365220-06R 贴片电阻 22Ω 0603 ±5% ROHS PCS 5 R74,R75,R97,R102,R394

43 T01.365221-06R 贴片电阻 220Ω 0603 ±5% ROHS pcs 2 R435,R436

44 T01.365472-06R 贴片电阻 4.7K 0603 ±5% ROHS PCS 37R17,R177,R188,R215,R221,R222,R237,R241,R248,R275,R276,R319,R329,R334,R339,R340,R347,R349,R373,R376,R384,R391,R392,R393,R397,R453,R473,R657,R708,R710,R712,R713,R714,R718,R379,R409,R293

45 T01.365331-06R 贴片电阻 330Ω 0603 ±5% ROHS PCS 1 R78

46 T01.365103-06R 贴片电阻 10K 0603 ±5% ROHS PCS 47

R15,R19,R20,R22,R32,R36,R44,R57,R64,R80,R85,R101,R112,R119,R121,R122,R149,R158,R161,R207,R253,R259,R280R306,R307,R335,R336,R353,R389,R399,R400,R404,R410,R411,R412,R413,R414,R416,R418,R419,R475,R484,R709,R71,R254,R5,R711

47 T01.365332-06R 贴片电阻 3.3K 0603 ±5% ROHS PCS 1 R292

48 T01.365223-06R 贴片电阻 22K 0603 ±5% ROHS PCS 7 R108,R109,R152,R153,R289,R423,R380

49 T01.365123-06R 贴片电阻 12K 0603 ±5% ROHS PCS 6 R34,R38,R82,R89,R106,R115

50 T01.365330-06R 贴片电阻 33Ω 0603 ±5% ROHS PCS 16 R124,R126,R150,R155,R160,R170,R181,R201,R203,R205,R217,R219,R220,R223,R239,R240

51 T01.365333-06R 贴片电阻 33K 0603 ±5% ROHS PCS 3 R58,R224,R495

52 T01.365473-06R 贴片电阻 47K 0603 ±5% ROHS PCS 22 R145,R192,R195,R196,R210,R211,R216,R225,R226,R227,R228,R234,R252,R279,R281,R287,R301,R308,R314,R309,R296,R352

53 T01.365822-06R 贴片电阻 8.2K 0603 ±5% ROHS PCS 2 R204,R229

54 T01.365226-06R 贴片电阻 2.2M 0603 ±5% ROHS PCS 4 R212,R214,R283,R290


56 T01.365202-06R 贴片电阻 2K 0603 ±5% ROHS PCS 2 R243,R258

57 T01.365104-06R 贴片电阻 100K 0603 ±5% ROHS PCS 5 R251,R262,R272,R482,R503

58 T01.365511-06R 贴片电阻 510Ω 0603 ±5% ROHS PCS 1 R255


60 T01.365273-06R 贴片电阻 27K 0603 ±5% ROHS PCS 1 R324



63 T01.365681-06R 贴片电阻 680R 0603 ±5% ROHS PCS 2 R406,R407





68 T01.365151-06R 贴片电阻 150R 0603 ±5% ROHS PCS 1 R502


70 T01.385122-08R 贴片电阻 1.2KΩ 0805 ±5% ROHS PCS 4 R1,R4,R332,R333

71 T01.361901-06R 精密电阻 909Ω 0603 ±1% ROHS PCS 1 R2

拟制: 审核: 2/5



72 T01.361102-06R 精密电阻 1K 0603 ±1% ROHS PCS 2 R8,R9

73 T01.361391-06R 精密电阻 390Ω 0603 ±1% ROHS PCS 3 R10 ,R59,R457

74 T01.361622-06R 精密电阻 6.2K 0603 ±1% ROHS PCS 1 R14

75 T01.361202-06R 精密电阻 2K 0603 ±1% ROHS PCS 1 R18


77 T01.361103-06R 精密电阻 10K 0603 ±1% ROHS PCS 2 R244,R69,


T01.935270-06R 压敏电阻 EZJZ1V270RA 0603

T01.935100-06R 压敏电阻 ICVL1018100Y500FR

80 T01.205150-00R 碳膜电阻 15R/2W ROHS PCS 1 R147

81 T01.865220-06R 贴片排阻 22R 4P 0603 1/16W ±5% ROHS PCS 4 RP10,RP17,RP34,RP38

82 T01.865330-06R 贴片排阻 33R 4P 0603 1/16W ±5% ROHS PCS 3 RP12,RP13,RP16

83 T01.865470-06R 贴片排阻 47R 4P 0603 1/16W ±5% ROHS PCS 1 RP14

84 T01.865560-06R 贴片排阻 56R 4P 0603 1/16W ±5% ROHS PCS 3 RP35,RP36,RP37

85 T01.865101-06R 贴片排阻 100R 4P 0603 1/16W ±5% ROHS PCS 9 RP41,RP42,RP43,RP44,RP46,RP47,RP48,RP49,RP50

86 T02.336330-06R 贴片电容 33PF 16V +80-20% 0603 ROHS PCS 5 C167,C171,C398,C172,C173

87 T02.364103-06R 贴片电容 10NF 50V ±10% 0603 ROHS PCS 10 C3,C230,C277,C317,C318,C347,C177,C275,C345

88 T02.336331-06R 贴片电容 330PF 16V +80-20% 0603 ROHS PCS 6 C19,C21,C27,C40,C64,C74

89 T02.336105-06R 贴片电容 1uF 16V +80-20% 0603 ROHS PCS 5 C24,C301,C378,C448,C463

90 T02.336473-06R 贴片电容 47NF 16V +80-20% 0603 ROHS PCS 19 C16,C17,C23,C42,C45,C46,C48,C49,C51,C56,C57,C58,C77,C78,C82,C96,C100,C72,C88

91 T02.336104-06R 贴片电容 0.1uF 16V +80-20% 0603 ROHS PCS 116

C44,C67,C92,C125,C126,C127,C128,C131,C155,C164,C168,C169,C174,C175,C183,C184,C185,C187,C191,C306,C316,C344,C441,C443,C852,C853,C854,C13,C14,C41,C69,C98,C99,C103,C106,C108,C109,C110,C111,C118,C119,C129,C138,C143,C170,C176,C181,C182,C196,C197,C198,C199,C200,C215,C266,C267,C281,C310,C334,C336,C348,C406,C446,C456,C465,C36,C245,C371,C372,C373,C374,C375,C376,C380,C381,C385,C386,C387,C390,C393,C394,C395,C399,C400,C401,C402,C403,C407,C408,C409,C410,C411,C412,C415,C416,C417,C418,C420,C421,C428,C433,C434,C435,C436,C437,C438,C439,C440,C459,C186,C212,C213,C270,C341,C349,C343

92 T02.336225-06R 贴片电容 2.2uF 10V +80-20% 0603 ROHS PCS 24 C22,C28,C35,C37,C50,C55,C63,C66,C75,C229,C235,C238,C241,C242,C247,C248,C255,C256,C257,C389,C413,C429,C460,C116

93 T02.336561-06R 贴片电容 560PF16V +80-20% 0603 ROHS PCS 8 C26,C33,C34,C38,C47,C65,C68,C254

94 T02.336102-06R 贴片电容 1NF 16V +80-20% 0603 ROHS PCS 9 C39,C54,C262,C43,C93,C95,C233,C239,C307

95 T02.336822-06R 贴片电容 8.2NF 16V +80-20% 0603 ROHS PCS 1 C97

96 T02.336203-06R 贴片电容 22NF 16V +80-20% 0603 ROHS PCS 1 C165

97 T02.336183-06R 贴片电容 18NF 16V +80-20% 0603 ROHS PCS 4 C236,C237,C259,C260

98 T02.336100-06R 贴片电容 10PF 16V +80-20% 0603 ROHS PCS 1 C210

99 T02.336101-06R 贴片电容 100PF 16V +80-20% 0603 ROHS PCS 7 C211,C234,C240,C246,C252,C314,C315

100 T02.336204-06R 贴片电容 220NF 16V +80-20% 0603 ROHS PCS 4 C258,C346,C404,C414

101 T02.346106-12R 贴片电容 10UF 10V +80-20% 1206 ROHS PCS 35C30,C52,C53,C70,C80,C115,C117,C193,C283,C284,C313,C464,C469,C370,C377,C379,C383,C384,C388,C391,C396,C405,C422,C425,C426,C454,C249,C261,C265,C269,C280,C308,C311,C312,C331,

102 T02.233476-57R 切脚电解电容 47uF/16V(5*7)ROHS PCS 3 CA72,CA73,C243

103 T02.233104-57R 切脚电解电容 100uF/16V(5*7)ROHS PCS 10 CA2,CA9,CA39,CA47,CA51,CA52,CA464,CA465,C455,C458

PCS 10 DD19,DD20,DD28,DD29,DD52,DD16,DD17,DD41,DD42,DD43,79

拟制: 审核: 3/5



104 T02.233477-8BR 切脚电解电容 470uF/16V(8*12)ROHS PCS 8 CA3,CA6,CA8,CA15,CA50,CA55,CA61,CA62,

105 T02.223477-6QR 切脚电解电容 470uF/10V,6*12 PCS 1 C244

106 T07.190021-00R SCART插座 Scart 黑色接口 21PIN 带两定位引脚 PCS 1 P14

107 T07.23001D-00R HDMI接口 HDMI母座-01D ROHS PCS 1 CON9

108 T07.160001-0AR S端子 SVIDEO JACK SW-4-10 4PIN带屏蔽 PCS 1 CON16

109 T07.102017-19R 针座 2*17*2.0mm(立式)ROHS PCS 1 CON11

110 T07.102005-19R 插座 5PIN 2.0mm(立式白色)ROHS PCS 1 CN31

111 T07.102006-19R 插座 6PIN 2.0mm(立式白色）ROHS PCS 1 CON2

112 T07.102009-19R 插座 9PIN 2.0mm(立式白色)ROHS PCS 1 CON37

113 T07.102004-19R 插座 4PIN 2.0mm(立式白色） PCS 1 CON31

114 T07.200000-16R VGA插座VGA，HDR15SNG，DIP（蓝色）小

头PCS 1 CON7

115 T07.013505-00R 耳机插座 Phone Jack 5PIN CKX-3.5-20 PCS 1 CON8

116 T07.013055-00R 耳机插座 Phone Jack 7PIN PJ-3055 PCS 1 HP1

117 T07.112504-19R 插座 4PIN 2.54mm（立式白色）ROHS PCS 1 CN21

118 T11.002048-49R 晶振XTAL,20.48MHZ,33pF,30ppm,U49S,DIP

PCS 1 X1

119 T11.000012-49R 晶振 XTAL, 12MHZ,20pF,30ppm,U49S,DIP PCS 1 Y5

120 T11.000004-49R 晶振 XTAL, 4MHZ,20pF,30ppm,U49S,DIP PCS 1 Y4

121 T19.209E89-00R 主芯片散热片梭状散热片-9E89,28x28x10mm,黑色,ROHS

PCS 1 TO MST106

122 T50.190000-10R 绝缘导热胶主芯片导热胶 G 0.3 TO MST106 芯片

PCS 1 R398 3.3V

PCS 1 R386 5V

PCS 1 R7 12V

1 T07.020003-11R DC插座DC POWER JACK JS-DC014KA2.0 mm,ROHS

PCS 1 CON5

2 T50.000030-05R 跳线 30mmx0.5mm ROHS PCS 1 F2


4 T03.504150-12R 贴片电感 SMRH127-150M ROHS PCS 1 L33

5 T04.80SK34-00R 贴片二极管 SK34,SMD,DO-214,ROHS PCS 1 D12



2 T03.504150-12R 贴片电感 SMRH127-150M ROHS PCS 1 L33

3 T04.80SK34-00R 贴片二极管 SK34,SMD,DO-214,ROHS PCS 1 D12


1 T03.134700-12R 贴片磁珠 FB DCR=0.7Ω-3A(1206),ROHS PCS 1 R25

2 T07.112513-19R 插座间距2.54MM,1X13 DIP180,ROHS PCS 1 CON21

备注2、带DC头外置适配器供电注：针对小机型

备注1、屏电压选择注：只能选择一种电压根据订单屏电压选择

FB DCR=0.7Ω-3A(1206),ROHST03.134700-12R 贴片磁珠1

备注3、内置二合一电源板供电注：针对小机型

备注4、26寸及以上注：针对大机型

拟制: 审核: 4/5



1 T01.365000-06R 贴片电阻 0Ω 0603 1/16W ±5% ROHS PCS 3 R93,R94,R95

1 T06.10V330-00R 集成块 PI5V330 TSOP16 ROHS PCS 1 U17

2 T02.346106-12R 贴片电容 10UF 10V +80-20% 1206 ROHS PCS 6 C89,C90,C91 C79,C85,C87

3 T07.102005-19R 插座 5PIN 2.0mm(立式白色)ROHS PCS 1 CON4



6 T07.102004-19R 插座 4PIN 2.0mm(立式白色） PCS 1 CON13

7 T02.233477-8BR 切脚电解电容 470uF/16V(8*12)ROHS PCS 2 CA5,CA10

1 T07.062562-01R AV插座六孔(绿篮红，黄白红)，ROHS PCS 1 CON23 YPBPR+AV

2 T07.062492-00R AV插座三孔(黄白红),带屏蔽，带螺丝孔，

ROHSPCS 1 CON23 AV

1 T07.2200CI-00R pcmica卡座 pcmica CI卡座 PCS 1 CONN1

2 T06.17SZ32-00R 集成块 NC7SZ32 SOT-23-5 PCS 1 U27

3 T06.104953-00R 集成块 CEM4953 SOP-8 PCS 1 U7

4 T04.804001-00R 贴片二极管 1N4001,SMD,SMA,ROHS PCS 2 D4,D5

5 T04.805819-00R 贴片二级管 IN5819,SMD,DO-214,ROHS PCS 1 D6

6 T02.346106-12R 贴片电容 10UF 10V +80-20% 1206 ROHS PCS 1 C461

1 T06.10V330-00R 集成块 PI5V330 TSOP16 ROHS PCS 1 U17

2 T02.346106-12R 贴片电容 10UF 10V +80-20% 1206 ROHS PCS 6 C89,C90,C91 C79,C85,C87

序号更改后位号

1 LM4558 SOP-8 ROHS U32

2 13K 0603±5% ROHS R288,R299

3 10K 0603±5% ROHS R291,R295

4 47K 0603±5% ROHS R285,R298

5 10K 0603±5% ROHS R127,R144

6 22K 0603±5% ROHS R296,R352

7 470Ω 0603±5% ROHS R322,R3250Ω 0603 1/16W±5% ROHS

更改前

0Ω 0603 1/16W±5% ROHS

0Ω 0603 1/16W±5% ROHS

无

47K 0603±5% ROHS

备注9、带YPBPR功能

无

备注8、带CI卡功能

备注6、带DVD功能

备注7、AV, YPBPR选择

备注5、不带DVD功能，不带YPBPR功能

备注10、26寸及以上配8Ω喇叭时，作如下变更

数量

2PCS

1PCS

2PCS

2PCS

2PCS

2PCS

2PCS

无

拟制: 审核: 5/5

PO NO.:T0908-03 LT-2298(21.6) STL-02 版本：AO Date:2009-08-31

序号代码物料名称规格型号单位数量备注

1 T44.1E2298-20R 机壳本厂LT-2298 (21.6")高光黑.ROHS SET 1

1 T43.2298QK-02R 前壳 HIPS，全黑色罩光，有LOGO丝印"AXXION"，ROHS PCS 1 L216S60

2 T43.2298HK-00R 后壳HIPS，普通料，喷漆黑色，配内置电源板结构，拨动开

关孔不打开，8字型AC座孔要打开，ROHSPCS 1 L216S

3 T43.2298ZS-01R 装饰条 PVC，烫印银色，ROHS PCS 1 L216S60

4 T43.1998AJ-00R 按键ABS,普通银色，取消两头的两个按钮后留7个按键，

ROHSPCS 1 L185F

5 T43.1998GZ-00R 导光柱 PMMA，无色透明，ROHS PCS 1 L15F6

6 T43.2298JX-00R 机芯支架 HIPS，配MSTAR 106主板（SCART+AV)，ROHS PCS 1 L22S

7 T43.2298DY-00R 内置电源支架 HIPS，阻然料，22“内置电源板，ROHS PCS 1 L22S

8 T43.2298DB-00R 端子板HIPS，黑色同后壳，配MSTAR 106主板（SCART+AV)，DC座插孔不要，ROHS

PCS 1 L22S

9 T43.1998LZ-01R 喇叭支架 HIPS，ROHS PCS 2 L19S

10 T43.1998LD-00R 喇叭支架橡胶圈橡胶，ROHS PCS 4 L19F5

11 T43.3298BG-00R 壁挂小件 PC，内M6螺纹 PCS 4 L32S

12 T43.1998DZ-00R 底座 HIPS，全黑色罩光，ROHS PCS 1 L19S

13 T43.3298JD-00R 底座脚垫橡胶，Ø16*6，ROHS PCS 4 L32S

1 T43.1998ZZ-00R 底座转轴 SGSS，T=2MM PCS 1 L19S

2 T43.2298LP-00R 连屏件 SGSS，T=1MM，配屏型号 PCS 2 L216S

3 T43.2298PY-00R 屏压片 SGSS，T=0.8MM，配屏型号 PCS 3 L22F5

1 T16.213008-00R 螺丝 BA3*8 自攻,尖尾,镀镍，ROHS PCS 36

控制板-按键(3),按键-后壳(2),接收板-前壳(2),

喇叭-喇叭支架(8),机芯板-机心支架(4),内置电

源板-电源支架(4),机芯支架-后壳（2），内置

电源板支架-后壳（4）；连屏件-前壳(4),压屏

件-前壳（3）

2 T16.243010-01R 螺丝 BB3*10,自攻,平尾,镀黑锌,ROHS PCS 18前壳-后壳(10),壁挂小件-后壳（4），后壳-端

子板-机心支架(2),锁AC座(2)

3 T16.244012-01R 螺丝 BB4*12,自攻,平尾,镀黑锌,ROHS PCS 4 转轴-后壳(4)

4 T16.413010-11R 螺丝 PWA3*10，带垫w=φ11mm,自攻,镀镍，ROHS PCS 4 喇叭支架-后壳（4）

5 T16.234008-01R 螺丝 BM4*8机牙,加硬,镀黑锌，ROHS PCS 3 底座-转轴(3)

6 T16.233005-00R 螺丝 BM3*5机牙,加硬,镀镍,ROHS PCS 4 连屏件-屏(4)

1 T34.090803-00R 说明书 L-2298W（21.6")，T0908-03，ROHS PCS 1

2 保修卡 PCS 此单取消.请注意!

3 T28.138120-30R 电源线胶袋380*120(开口)*0.05mm,带环保丝印,透明PE袋(带透气孔),带

环保丝印PCS 1

4 T50.010012-00R 透明胶带 12MM ROHS 卷 .02 用于封附件胶袋

5 T32.070015-00R 7号电池 7号碳性1.5V,ROHS PCS 2

6 T23.250180-55R 附件盒 250*180*55MM，详细规格见图纸,ROHS PCS 1

7 T45.500320-00R 22寸屏保护胶片 500*320*0.1mm透明PVC片,ROHS PCS 1

8 T50.010030-10R 隐形胶纸 3M隐形胶带 ROHS 卷 .01 用于贴屏保护膜胶片

9 T29.090803-03R 按键功能贴纸PVC，7孔，T=0.3mm，丝印从左到右为“VOL-,VOL+,CH-

,CH+,MENU,SOURCE,POWER"PCS 1

10 T29.090803-01R 后壳贴纸 79*59mm,带背胶,ROHS PCS 1

11 T29.090803-02R 功能端子贴纸262*14*0.3mm,PVC黑色,带3M背胶,配MSTAR 106主板（SCART+AV），ROHS

PCS 1

一、机壳：

塑胶类

五金类

二、螺丝类

三、包材类

拟制: 审核: page 1 of 2

PO NO.:T0908-03 LT-2298(21.6) STL-02 版本：AO Date:2009-08-31

序号代码物料名称规格型号单位数量备注

T29.090803-04R 前壳贴纸 PCS 1 09.09.24

12 T29.TXM000-05R 流水号码贴纸 9248034500001--9248034503920 PCS 2 整机1，外箱1

13 T29.QC0000-04R QC贴纸 QC PASSED易碎贴纸 PCS 1

14 T29.ROHS00-14R ROHS贴纸见美工资料 PCS 1

15 T28.165600-30R 整机胶袋650（开口）*600*0.05mm透明PE袋，带环保丝印（带透气

孔)PCS 1

16 T31.142298-03R 缓冲材 LT-2298W,EPS发泡胶（配装配底座的整机）套 1 左上、左下、右上、右下4个（新开模物料）

17 T39.090803-00R 卡通箱彩盒596*222*460mm，ROHS PCS 1 09.09.17

18 T40.500001-00R 提手 PCS 1 需外购.请注意!

19 T50.010060-00R 封箱胶纸 60MM，ROHS 卷 .02

20 T41.102810-00R 无纺布黑色，带背胶,280*10*0.2mm,ROHS PCS 2 防震音及漏光

21 T41.105010-00R 无纺布黑色，带背胶,500*10*0.2mm,ROHS PCS 2 防震音及漏光

1 T54.MS1063-02R 主板 CX-MST106-V3.0 PCS 1 有发全功能的BOM

2 屏为本厂组装屏,玻璃型号为:V216B1-P01 PCS 1

3 T37.090803-01R 屏线 PCS 1 见图纸

4 T53.07B060-00R 二合一内置电源60W,4灯,ROHS 不带地线不带AC座安科迅

AIP4904002A-GPCS 1

5 T37.090803-02R 高压排线 PCS 1 见图纸

6 T26.114070-50R 喇叭 4Ω/3W,4070,ROHS PCS 2

7 T37.090803-10R 喇叭线 PCS 1 见图纸

8 T25.23VDE0-02R 电源线两脚圆插(八字尾) 2*0.75mm2 L=1.5M PCS 1 金宏业电线.请注意!!!

9 T07.21F180-00R AC座 RF-180(八字尾),带锁螺丝，ROHS PCS 1

10 T37.090803-05R 电源过桥线 PCS 1 见图纸

11 T40.403000-00R 热缩管￠3*15mm,ROHS PCS 1 用于电源开关过桥线

12 T42.000506-CXR 遥控器 CX-506 PCS 1 丝印见美工资料

1 T09.812665-01R 轻触开关立式6*6*5mm（红色),ROHS PCS 7

2 T37.090803-07R 按键板线 PCS 1 见图纸

3 T15.022011-00R 按键板PCB KEY: 2011 9E19方案+98机壳 PCS 1

1 T15.035011-02R 遥控板PCBIR:5011 9X19+98机壳，双面板,纤维板,

（35*18*1.6MM）ROHSPCS 1

2 T37.090803-08R 遥控板线 PCS 1 见图纸

3 T05.408238-00R 接收头 LMC 8238(2638) ROHS PCS 1

4 T02.233476-11R 切脚电解电容 47UF/16V(5*5MM),ROHS PCS 1

5 T04.67W030-25R 发光二极管（双色LED） φ3.0 (红/绿),共阴极,(雾状),ROHS PCS 1 09.09.19

6 T01.285100-00R 碳膜电阻 10Ω 1/8W,ROHS PCS 1

六、遥控板类：T55.030908-03R

四、电子类

五、按键板类:T55.020908-03R

拟制: 审核: page 2 of 2

MST Chassis Program Writer User’Guide

JINPIN ELECTRIAL COMPANY LTD. ZHUHAI S.E.Z Add:No.15,PingBei 2nd Road, Nan Ping Technology & Industrial Park, Zhuhai, Guangdong, China. Tel:(86-756)3837798 3837386

Http://www.jinnpina.com.cn

Software Upgrade

Preparing : Connect LPT-VGA download tool line, One connector is connected to VGA

connect port of Plasma TV ,while another side is connected to PC Parallel port . PC CMOS setup the Parallel port is “ECP”mode.

Store the MST ISP Tool into the PC.

图1 Figure 1.

图2 Figure 2 .

图3 Figure 3. 1) 释放包裹文件“ISP-tool.rar”,放在桌面上 Release the zip file ISP tool.rar send shortcut key to the desktop, clicking the

program icon when the icon displays in the Start Menu and the desk. Clicking the icon

图4 Figure 4.

Downloading :

2) 在桌面上双击 ISP 的图标 Dblclick ico, Run ISP_TOOL.exe

3) 点击“Read”键，选择加载文件的路径 click “Read” ico, Select the update binary by pressing browse button,Follow setp1,2,3,4

图5 Figure 5.

4).接通主电源开关，给电视机供电。 Turn on the LCD TV power supply. 5).

a.点击“Connect”连接电脑,如以下的图示所示，选择”确定”. Select the connect ico, display dialog the connect is ok.

图6 Figure 6.

b. 选择”Auto”图标，再点击“RUN”,进行录入升级软件。 Select the “Auto” ico, Press “Run” Upgrade button and start update process.

图7 Figure 7

图8 Figure 8.

changyf

文本框

EN25F32

c. 显示以下的打印信息，表示已经成功完成！ The update process is successful as the display “End time:xx:xx:xx”. After the update process is ok,

图9 Figure 9. 6）如果显示有“error”的信息，操作不成功，需要重新再点击“Run”进行烧录。

If display “ error”, repeat click “Run”.

7) 升级软件成功后，需要关掉主电源开关，等待电源指示灯完全息灭后再开机。 turn off power and wait indicator light is off. Turn on power and TV can work. 8）完成。

Done. 2007-10-19

This manual is the latest at the time of printing, and does not

include the modification which may be made after the printing,

by the constant improvement of product.

THE END

This Page intended to leave blank.

curtis lcd2226fr manual

Documents

parts list

exposed metallic parts

mechanical parts

ac plug

ac voltage measurementsfor

safety precaution

ac line cord

ahigher voltage