Current Mode Multiple-Valued Logic Circuits in Digital CMOS Technology

by Robert Sobot

B.A.Sc. The University of Belgrade 1989

A THESIS SUBMITTED IN PARTIAL FULFILLMENT

OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE

in the School of Engineering Science

O Robert Sobot 1996 Simon Fraser University

September 1996

All rights reserved. This thesis may not be reproduced in whole or in part, by photocopy or other means, without permission of the author.

Approval

Name: Robert Sobot

Degree: Master of Applied Science

Title of Thesis: Current Mode Multiple-Valued Logic Circuits in Digital CMOS Technology

Examining Committee: Dr. Glenn Chapman,Khairrnan School of Engineering Science, SFU

Dfl&kKyrzyc)d, Senior Supervisor School of Engineering Science, SFU

Dr. Rick Hobson, Supervisor School of Computing Science, SFU

Dr. Andrew Rawicz, Examiner School of Engineering Science, SFU

Date Approved:

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library of any other university, or other educational institution, on its own behalf or for one

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copying or publication of this work for financial gain shall not be allowed without my

written permission.

Title of Thesis/Project/Extended Essay

"Current Mode Multiple-Valued Logic Circuits in Digital CMOS Technology"

Author: (signature) Robert Sobot (name)

(date)

Abstract

Complexity of silicon integrated circuits (IC) in very large scale of integration (VLSI) using binary logic is reaching a point where most of the silicon area is occupied with inter-

connecting lines among devices on the chip, which represents a drawback of the approach.

First implication of the high wiring complexity is increased packing complexity with

increased number of pins (in today's VLSI IC number of pins exceeds 250). Therefore, high density layout must be used for data bus both in the silicon and on the printed circuit

board. Second implication is increased cross-talk noise which is one of the limiting factors

in design of high-speed and sophisticated ICs, especially in a low-power voltage environ-

ment and high-speed chips for arithmetic applications.

Alternate approaches for design of integrated circuits for arithmetic operations that would

use standard complementary metal-oxide-semiconductor (CMOS) technology and address the above issues have been proposed. One possible solution for reduction of high wiring

complexity, without affecting performance of a chip, is injecting more than two levels of signal into a single wire. This is known as multiple-valued logic (MVL), however, due to narrow voltage margins, especially in low power designs, current mode (CM) is proposed as a better approach to MVL design. Multiple-valued logic (MVL) has been studied exten- sively due to its potential advantages in chips performing arithmetic intensive operations.

Reduction in the wiring density leaves space for relaxed distance between the data lines,

therefore reducing parasitic capacitances between the lines and, finally, reducing cross talk

noise.

Research effort in this thesis is directed towards the development of functional current-

mode multiple-valued logic (CMMVL) circuits, as well as such basic building blocks as current sources, current mirrors and current comparators. In this thesis, the CMMVL

approach is used to design high-speed low-power CMMVL adders that can be used in

higher level designs such as CMMVL multipliers.

...

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to Ljubica

Acknowledgments

I would like to thank professor Dr. Marek Syrzycki for all the help, guidance

and support that he provided during my work on this thesis. Also, I would

like to thank the Canadian Microelectronic Corporation for providing silicon

space for my designs.

Table of Contents

. . Approval ............................................................................................................................ ii ... Abstract ............................................................................................................................. 111

Acknowledgments .............................................................................................................. v ... List of Tables .................................................................................................................. viii

List of Figures ................................................................................................................... ix

Introduction ..................................................................................... 1 1 . Analog Design in Digital CMOS Technology ................................................... 2 2 . Multiple-Valued Logic (MVL) ......................................................................... 3

.............................................................................................. 3 . Goal of the Thesis 5 4 . Organization of the Thesis ................................................................................. 6

CHAPTER 1 Adding Algorithms in Multiple-Valued Logic (MVL) ...................... 7 1.1 Multiple-Valued Logic (MVL) Signal Levels .................................................... 7 1.2 Redundant Positive-Digit (PD) Number Representation ................................... 9

.................................................... 1.3 Positive-Digit (PD) Two-Operand Addition 10 .............................................................................. 1.4 Decimal Adding Operation 11

1.5 Basic Functions Required by Multiple-Valued Logic Adders ......................... 12

CHAPTER 2 Structure of Current-Mode Multiple-Valued Logic (CMMVL) CMOS Adders ................................................................................. 13

2.1 CMMVL Adder Using Positive-Digit Adder (PDA) Cells .............................. 14 2.2 Decimal n-Digit CMMVL Adder ............................................................... 15 2.3 CMMVL Dynamic Mode Adder ..................................................................... 16

CHAPTER 3 Basic Building Blocks of Current-Mode Multiple-Valued Logic (CMMVL) CMOS Integrated Circuits ........................................... 17

3.1 Super MOS Transistor ..................................................................................... 17 3.2 Current Mirrors (CM) ...................................................................................... 18

3.2.1 Basic Current Mirror Configurations ................................................... 19 3.2.2 High-Swing Cascoded Current Mirror (HSCM) .................................. 20

........................ 3.2.3 Current Mirror with Super MOS Transistors (STCM) 20 .............................................................................. 3.3 Current Comparators (CC) -21

.......................................................... 3.3.1 Open-Loop Current Comparator 21 ....................................................... 3.3.2 Closed-Loop Current Comparator 22

....................................................................................... 3.4 Current Sources (CS) 23 3.5 Voltage-Switched Current Sources (VSCS) ..................................................... 23

CHAPTER 4 Design and Implementation of Basic Building Blocks for CMMVL Circuits in Digital CMOS Technology ............................................. 25

............................................................... 4.1 Design of the Super MOS Transistor 25 ............................................................................... 4.2 Design of Current Mirrors 29

....................................................................... 4.2.1 Implementation Results 32

....................................................................... 4.3 Design of Current Comparators 33 4.3.1 Examples of Open-Loop Current Comparators ................................... 34

.................................... 4.3.2 Example of Closed-Loop Current Comparator 35 4.4 Implementation Results ................................................................................... 37

CHAPTER 5 Design and Implementation of Current-Mode Multiple-Valued . . Log~c CMOS Adders .......................................................................... 38

5.1 Design of CMMVL Positive-Digit Adder (PDA) ............................................ 38 5.1.1 The PDA Cell Specification ................................................................. 38

....................................................... 5.1.2 The PDA Cell Circuit Description 39 ........................................................... 5.1.3 The PDA Cell Characterization 41

............................. 5.2 Design of CMMVL Single-Digit Decimal Adder (SDDA) 43 5.2.1 The SDDA Cell Specification .............................................................. 43 5.2.2 The SDDA Cell Circuit Diagram ......................................................... 44 5.2.3 The SDDA Cell Characterization ........................................................ 45

............................................................... 5.3 Design of Dynamic CMMVL Adder 46 ................ 5.4 Comparison of CMMVL adders with voltage-mode binary adders 48

CHAPTER 6 Conclusions ......................................................................................... 49 References ......................................................................................................................... 52

vii

List of Tables

Table: 1 . Pin description of the PDA cell ................................................................ 39

Table: 2 . Logical table for the PDA cell .................................................................. 39

Table: 3 . Pin description of the SDDA cell ............................................................. -44

............................... Table: 4 . Logical table for single-digit decimal adder (SDDA) 44

List of Figures

Figure: 1.1.

Figure: 1.2.

Figure: 2.1.

Figure: 2.2.

Figure: 2.3.

Figure: 2.4.

Figure: 3.1.

Figure: 3.2.

Figure: 3.3.

Figure: 3.4.

Figure: 3.5.

Figure: 3.6.

Figure: 3.7.

Figure: 4.1.

Figure: 4.2.

Figure: 4.3.

Figure: 4.4.

Figure: 4.5.

Figure: 4.6.

Comparison of binary (a) and MVL logic (b) signals and signal noise mar- gins .............................................................................................................. -7

................................... Noise margin definitions for n-level CMMVL logic 8

Hierarchical structure of a current-mode system ....................................... 13

The PDA based on radix-2 PD number representation .............................. 14

Block diagram of the n-digit CMMV decimal adder ................................. 15

Block diagram of dynamic CMMVL adder ............................................... 16

Super NMOS transistor (a) and its schematic symbol (b) ......................... 18

Simple current mirror (a) and cascoded current mirror (b) ........................ 19

High-swing cascoded current mirror (HSCM) .......................................... 20

Current mirror with the Super MOS transistors (STCM) .......................... 21

Open-loop current comparator with voltage output (a) and current output (b) ............................................................................................................... 22

Closed-loop current comparator ............................................................... 22

The VSCS block diagram .......................................................................... 23

DC characteristics of Super NMOS transistor and a single NMOS transis- tor ............................................................................................................... 26

Transient response comparison for the transistors ..................................... 27

Layout of the Super NMOS transistor (38pm x 90pm) ............................. 28

Testing result of the Super NMOS transistor ............................................. 28

Comparison of I-V characteristics for the current mirrors ......................... 29

Accuracy of the current mirrors ................................................................. 30

Figure: 4.7. Transient response of the current mirrors .................................................. 31

Figure: 4.8. Photomicrograph of the HSCM cell (215pm x 73pm) (a); and STCM cell layout (75pm x 95pm) (b) ........................................................................ -32

Figure: 4.9. Distribution of results for HSCM in Mite1 1Smm CMOS ........................ 32

.............................................................. Figure: 4.10. Measured accuracy of the STCM 33

Figure: 4.11. DC transfer curve (a) and transient response (b) of the open-loop current comparators ................................................................................................ 34

................................... Figure: 4.12. Transient response of dynamic current comparator 35

................ Figure: 4.13. Layout of the closed-loop current comparator (38pm x 98pm) 36

................ Figure: 4.14. Measured results from the closed-loop current comparator cell 37

Figure: 5.1.

Figure: 5.2.

Figure: 5.3.

Figure: 5.4.

Figure: 5.5.

Figure: 5.6.

Figure: 5.7.

Figure: 5.8.

Figure: 5.9.

Symbolic representation of the PDA cell ................................................... 38

One stage of the PDA: current mirror. current comparator and VCCS ..... 40

Schematic diagram of the PDA cell [6] ..................................................... 40

DC transfer characteristics of the PDA cell .............................................. 41

Noise margins for the PDA cell ................................................................. 42

Delay time for rising edge (td. ) and falling edge (tdf) of the PDA cell ..... 42

Symbolic representation of the SDDA cell .............................................. 43

Photomicrograph of the PDA (180pm x 75pm in CMOS 0 . 8 ~ ) ............ 43

A single-digit decimal CMMVL adder (SDDA) internal architecture ...... 45

Figure: 5.10. DC transfer characteristics of the one digit adder ...................................... 46

................. Figure: 5.11. Layout of the SDDA cell (392pm x 150pm in CMOS 1.5pm) 46

Figure: 5.12. Simulated output from ten-level dynamic CMMVL adder ....................... 47

Figure: 5.13. Dynamic CMMVL adder (first stage) (size: 415pm x 426pm in 1.5pm CMOS) .................................................................................................... 48

Introduction

Binary logic, based on switching between two voltage levels, V(0) and V(l), is certainly the dominant technique of signal coding today. However, for a digital system to

interact effectively with inherently analogue world, analogue signal processing and data

conversion circuits are still required. Most often complex systems consist of a digital sig-

nal environment and a layer of analogue interface circuits [I]. As a result mixed-mode IC's are common approach today in applications where both digital and analog signal pro-

cessing is required. Basically, analog part of the chip has to be technologically compatible

to the digital part.

High level of sophistication does not come without a price in increased complexity

and its related problems. Today's ICs are at the point where devices on the chips are so

small and so fast that time delay in interconnection lines is an order of magnitude higher

than the internal device time delay. Moreover, with increased density of chips, the number

of inter-chip connections is greatly increased as more and more functions are put on the

same chip [2]. Secondly the high number of external pins per chip package represents technical challenge of its own for both circuit and the packaging designers.

Furthermore, the requirement for low-power dissipation in a single chip has been

rapidly increased in the present deep submicron ULSI technology. Low power dissipation

can be achieved by reducing the supply voltage, signal capacitance, and the number of

active devices to perform a given function. Therefore, it is very important to explore tech-

niques that will meet requirements of future high speed, low powered ULSI integrated

chips and beyond, and to develop new circuit designs using lower device count per func-

tion and lower wiring complexity.

1. Analog Design in Digital CMOS Technology CMOS technology which is optimized for digital circuits is a dominant VLSI tech-

nology today, due to its low cost and its simplicity in comparison to technologies that are

used for analog circuit design. Because of that, analog designers are usually the ones who

have to adjust their circuits in such a way to make them feasible in the technology and at the same time make them able to perform the analog operation that they were designed

for.

Common approach today is to use a voltage-mode of operation for both digital and

analog parts of chip. However, the fact is that both BJTs and FETs are current output

devices [I]. In addition, traditional analog interface circuits operating in low-voltage domain are limited by signal to noise ratio and need to drive big load capacitances. Diffi-

culties faced by switched capacitors (such as needed for two poly-silicon layers) technique and other "voltage mode" analogue interface circuits, in coping with the advance of digital

CMOS processing technology had revived interest in "current mode7' techniques. In an

environment where capacitance dominates and low supply voltage must be used, the use

of current mode circuit techniques may be favorable from both dynamic range and speed

viewpoints, depending upon specific application. Finally, wiring complexity and its result-

ing effects, such as the time delay and cross-tak, have become a problem particularly in

arithmetic circuits, such as multipliers, where a long-word data bus is required.

Obviously, design techniques capable of handling the above problems must be

developed. One possible way to go is current-mode multiple-valued logic (CMMVL). Reasons to consider CMMVL logic are as follows:

injection of more than two levels of signal into a single wire leads to lower number wires in data bus for the same range of data.

0 lower number of data wires leads to lower number of pins required for the data bus.

reduced number of wires allows the space between any two wires in the data bus to be

larger without paying penalties in silicon area, leading to smaller fringe capacitance

and reduced cross-talk.

power consumption is proportional to the clock frequency, proportional to load capaci-

tance and proportional to the square power of the supply voltage. Obviously, reduction

of the voltage is the first choice for reducing power consumption, leading into reduced

dynamic range of the voltage-mode data signal. However, dynamic range of current

mode signals is several order of magnitude higher than the voltage ones, allowing

application of MVL.

basic current-mode circuits are, in general, slower than equivalent voltage mode ones.

However, using algorithms that take advantage of multiple-valued logic it is possible to

design fully current-mode arithmetic circuits that perform arithmetic operation with the

same (or higher) speed as equivalent voltage-mode circuits.

2. Multiple-Valued Logic (MVL) From the circuit complexity point of view, multiple-valued logic (MVL) is half-

way between binary logic and analog signal processing. It performs its operations by

using more than two discrete signal levels. In voltage-mode circuits a number of signal

levels is limited by the power-supply voltage and signal-to-noise ratio. In current-mode

circuits a number of signal levels is limited by resolution of current comparators and sig-

nal-to-noise ratio for given technology. MVL can be implemented either in voltage mode

[3], or in current mode [4]. The most widely used industrial MVL application is Intel 8087 math co-processor that uses a quaternary ROM [5] that provides 3 1 % ROM area savings compared to a binary ROM. Other reported designs include: current mode multiple valued

logic (CMMVL) multipliers [6][7][27], neural networks [8], and image processing system

191.

Parallel multiplier presented in [6] is based on the redundant number representa- tion using positive digits (called redundant positive-digit number presentation, or simply PD number representation). The proposed 12x12 bit parallel multiplier is constructed in 5pm CMOS technology powered by 5V. Seven current levels were used and the unit cur-

rent step was 50pA with typical worst-case delay time in order of 100ns. The PD algo-

rithm allows simpler circuit implementation because only positive current signals are used

for the coding.

Parallel multiplier presented in [7] is 32x32 bit parallel multiplier fabricated in 2pm CMOS technology including depletion-mode PMOS. Its operation is based on radix-

4 signed-digit (SD) number system that requires seven levels of current signals: three pos- itive values, three negative values and zero with the unit current of 31pA. Typical delay

time is 59ns which was very close to the fastest binary multiplier of that time. Further-

more, space occupied by the CMMVL multiplier is only 52% of space occupied by equiv-

alent binary-mode multiplier.

Parallel multiplier presented in [27] is 54x54 bit pipelined multiplier fabricated in 0.8pm CMOS technology powered by 1.5V. Algorithm used is radix-2 SD number presen-

tation that uses three levels of the input signal with the unit current step of 20pA. Its clock

frequency is 200MHz (4.6ns delay time) resulting in 1.4 times higher speed for the same power consumption in comparison to corresponding binary multiplier.

As it can be seen from the above brief presentation of state of the art CMMVL cir-

cuits first natural application is in such arithmetic circuit as adders and multipliers and cir-

cuits that use multipliers for their operation [8][9]. Two major issues in efficient design of CMMVL adders and multipliers are the numerical representation of the numbers and the

unit current step per logic level. Choice of the numerical representation is based on

required speed and robustness of the algorithm, trading for complexity of the circuit

implementation. Two of the numerical representation will be discussed in Chapter 1 in

more detail. A unit current step per logic level is usually chosen as a trade-off between the

resolution of a current comparator and the repeatability of current mirrors. In designs pub-

lished so far the unit step current was chosen in range of 20pA to 200pA depending upon

used technology, application and the circuit configuration [4] [7]. Obvious challenge is to investigate how far we can go into the low-unit-step current by using today's technology.

We will investigate this issue by aiming at the current range bellow 20pA.

Using the CMMVL approach to realize MVL arithmetic ICs simplifies adding and

subtracting operations on the chip, because these operations can be performed simply by

interconnecting current sources and mirrors [9]. Thus, the CMMVL circuits will use cur- rent-mode (CM) building blocks such as current sources, mirrors and comparators to per- form most of arithmetic operations. Since standards for the CMMV circuitry have not yet

been established, it is important to investigate various combinations of signal levels and

circuit architectures, as well as to optimize them for the best possible yield.

3. Goal of the Thesis

The goals for research work presented in this thesis is following:

study the concept of CMMVL

demonstrate feasibility of a low-current CMMVL approach

investigate numerical representation and corresponding current signal levels suitable

for the implementation of the unit current step that can be obtained in standard CMOS

technology.

investigate operational limits of the basic CMMVL building blocks required for the

implementation, develop a set of basic current-mode building blocks and extrapolate

design parameters

use CMMVL adders in CMOS technology as test vehicles for the approach

present the results and conclusions regarding technology constraints for the design, as

well as potential advantages and disadvantages of the CMMVL approach.

4. Organization of the Thesis

In Chapter 1 multiple-valued logic (MVL) signals and basic functions required by MVL will be presented. In Chapter 2 internal architectures of two static current-mode

multiple-valued logic (CMMVL) adders will be proposed as well as architecture for dynamic CMMVL adder. The first CMMVL adder, named PDA, will use seven levels of

current signal and redundant positive-digit (PD). Second CMMVL adder is a four-decimal digit decimal adder that implements decimal adding algorithm by using ten levels of cur-

rent signal. Third design presented in this thesis investigates dynamic-mode CMMVL

adder approach. Circuit presented here is a current level detecting part only, decoding part

would be implemented based on numerical representation, resulting in a fully dynarnic-

mode CMMVL adder. Chapter 3 covers internal structures of basic building blocks

required by the CMMVL adders. In Chapter 4 implementation of the basic building blocks

in CMOS technology and process related constraints will be discussed. Chapter 5 presents

practical realizations the two CMMVL adders and, finally, Chapter 6 provides review of

the work, and proposes future research targets.

CHAPTER 1 Adding Algorithms in Multiple-Valued Logic (MVL)

Similar to definitions of binary logic signals used to perform complex mathemati-

cal operations in Boolean algebra and corresponding algorithms, "n" levels of current sig-

nal, corresponding noise margins, and arithmetic algorithms have to be defined in order to

perform arithmetic operations in n-valued current-mode multiple-valued logic (CMMVL). This chapter provides definition of MVL signals, introduces definitions of MVL signal

noise margins, and next discusses redundant positive-digit (PD) number representation, decimal number presentation, and basic mathematical functions required for implementa-

tion of CMMVL adders. The two algorithms will be used in this thesis as the engine to

demonstrate proposed CMMVL approach by developing and building two CMMVL

adders that would use them.

1.1 Multiple-Valued Logic (MVL) Signal Levels Graphical presentation of binary and MVL signals is shown in Fig. 1.1. The n-val-

ued signal "I" contains set of "n" discrete values:

Figure 1.1. Comparison of binary (a) and MVL logic (b) signals and signal noise margins

where I, is inside current range NM, set by its low margin NML, and its high margin

NMH,:

I, E (NMH, - NML,) . (2) Unit current step ISO defined as a difference between any two subsequent levels of current

signal

Iso = ( I x - I x - l ) ; ( x ~ { I , ..., n - I } ) : (3) therefore, every level of the signal is integer multiple of the unit signal step Is0. Accord-

ingly, every level has its own noise-margin NM, where x E { 1, . . ., n - 1 } (see Fig. 1.1 .b).

Here, we introduce definitions of noise margins NML and NMH similar to the ones used in

the binary logic [ll]. The transfer characteristics IOU, vs. Ii, of the current-mode binary circuit is shown in Fig. 1.2. The slope of the transfer characteristic equals -1 at the two

unity current gain points. Nominal logic levels IOL and hH are real current levels gener- ated by the stage. Now, we can define the high and low noise margins as:

NML = IIL - IoL and NMH = IOH - IIH.

but

IIL IIH Iin

Figure 12. Noise margin definitions for n-level CMMVL logic

In binary logic the noise margins are defined for only two levels of signal. Here, it should

be noted that in MVL logic noise margins are different for each level of the same signal. It

makes sense to use the worst case among all noise margins for all the levels as the ones to

characterize CMMVL circuit. In this thesis we will refer to the worst case among all the

margins as the ones relevant for cell characterization.

1.2 Redundant Positive-Digit (PD) Number Representation Term "redundant number representations" refer to number representation proposed

by Avizienis [12]. There are two basic redundant number representations: signed-digit (SD) and positive digit (PD) representations. The SD number representations use symrnet- rical digit sets such as {-1,O, 1 } for radix-2, (-2, -1,0, 1 ,2} for radix-3 and {-(n+l) ,..., - 1, 0, 1, ..., n+l ) for radix-n. When the radix is "n", the number representation, in which each digit takes (q+l) values (0, 1,2, ..., n-1, n, ..., q ) (q 2 n), is called redundant positive-digit number (PD) representation. When the radix is 2, the number representation where each digit takes four values (0, 1, 2, 3 ) is called binary PD number representation [6]. It is obvious that current-mode implementation of the above algorithms would require bidirec-

tional current-mode circuits for SD and unidirectional current-mode circuits for PD repre-

sentations. As a result SD representation would require slightly higher circuit complexity

in comparison to PD representation which uses simpler currents but additional steps are

required to encode negative numbers. Ln this thesis PD number representation only will be

used for the designs.

For high speed parallel computer arithmetic, use of redundant number representa-

tion is attractive because the carry-propagation chains are eliminated during the operation

of addition and subtraction resulting in faster execution of multiple-bit adding and multi-

plication algorithms. In other words, time required for the execution is independent of the

word length. Therefore, long words will be added and multiplied in approximate same

order of time as short words making overall execution time independent of the word

length. Therefore, CMMVL circuits have a potential to execute operations of addition and

multiplication of long words equally fast as voltage-mode circuits using standard binary

adding and multiplication algorithms, in spite of fact that basic current-mode circuits may

require more time than voltage-mode ones to perform a single bit operations.

1.3 Positive-Digit (PD) Two-Operand Addition As an example of the PD representation let us consider the addition of two oper-

ands using radix-2 algorithm, X = (x"-~ ,..., xi ,..., xO) and Y = (y,-l ,..., yi ,..., yo), where

X i , Y i = (0, 1,2,3} ; (i= 0, ..., n - 1) are performed by the following three successive steps for ith digit.

Step 1: Adds up linearly xi and yi as follows:

z i = X i + yi

where z i E {0, 1, . . ., 6 ) is linear sum digit.

Step 2: Generates the intermediate sum wi and the carry digits ci('), c ~ ( ~ ~ from r-. 1 -

where c!~), c!'), wi E {O, 1}

Step 3: Adds up linearly wi and the carry digits of (i - 1) and (i - 2)th position on the right:

Note that the sum si also belongs to 10, 1, 2, 3).

The following example demonstrates the algorithm by showing the adding procedure on

adding operation of numbers 59 and 34.

Example: The procedure of addition is as follows:

Digital position: 5 4 3 2 1 0 Augend X: 1 0 1 3 2 3 algebraic value X = 59 Augend Y: 0 1 0 3 2 2 algebraic value X = 34 Linear sum (q) 1 1 1 6 4 5 Intermediate sum (wi) 1 1 1 0 0 1 Carry (c/'3 1 0 0 Carry (c/~> 1 1 1 Final sum (si) 1 2 3 1 0 1 (algebraic value S = 93)

If we use the redundant positive digit representation as internal representation in

binary arithmetic, the conversion of redundant positive digit representation into and from

equivalent binary number is required. However, that process also takes time and the

advantage of the redundant PD representation can be lost by the conversion, therefore, the

conversion should be performed once only at the final stage of the computation.

1.4 Decimal Adding Operation

In order to explore feasibility of CMMVL circuits that use more than seven levels

of current signal by means of lower unit currents we also consider a decimal adding algo-

rithm as a candidate for CMMVL implementation.

Decimal system is based on a ten-digit set (0, 1, 2, ..., 8, 9). Inherently, addition is not carry-over-free, therefore, there is carry-over (C,) propagation involved in the opera- tion. As it is well known, sum Si of two numbers X and Y, with digits xi and yi, where: xi,

yi = (0, 1 ,... , 9 ) (i = 1,2, ..., n) can be described by partial sums Si and carry-over Co as:

xi + y; + C,; (S; I 9) S; = xi + y i - 10; (S; 2 10) ( 1

where Si = (0, 1, ..., 9) is partial sum, and C , is carry-over value. CMMVL implementation of this algorithm requires ten levels of current signal to represent all the digits. However,

adding block where execution of Eq. 7 takes place has to have resolution of 20 levels of

current signal, because Si E (0, 1, . . ., 19) .

1.5 Basic Functions Required by Multiple-Valued Logic Adders

By examining the above two algorithms more closely, it can be concluded that the

adding operations can be broken down to a set of basic arithmetic operations. The most

basic arithmetic functions required for applications in CMMVL are listed below:

constant function: I,,, = I, (I, 2 0) ; where "Ion is constant.

stepfunction: I,, = ( (Iin I r e ; in other words the output current becomes Yo7' '0 ('in ' 'ref)

if the input value is less or equal than preset current value "I,:', otherwise, the output

is zero, which is in fact a threshold function.

linear function: I,,,i = ki . Iin; (i= 1, . . ., n) ; where ki is a scaling factor. This func- tion permits to produce "n" replicas of current values "Ii; with each replica, I,,,,hav-

ing its own different scaling factor "kiV. O(F(Xi)= 0; (i= 1, ..., n ) )

general function: Iou,~ = (F (xi) = 1 ; (i= 1, . . ., n) ) ; here the output cur- rent value I,,, can be either zero or some positive value "IO" depending upon outcome

of some logical function F(Xi) (i = 1, ..., n), where "Xi" can be either voltage or current variable.

Each of the above functions will be realized by designing appropriate building block and

after that the blocks will be used for synthesis of higher level functional blocks that will be

required by the intended MVL algorithm.

CHAPTER 2 Structure of Current-Mode Multiple- Valued Logic (CMMVL) CMOS Adders

An example CMMVL system (Fig. 2.1) consists of various CM blocks defined according to their complexity and functionality such as ROM, CMMVL multipliers, and

neural nets. Chip level consists of such CM blocks as CMMVL multipliers that, further

down in the hierarchy, consist of functional blocks such as CMMVL adder. At the basic

building block level there is a set of four basic blocks: current comparators (CC), current mirrors (CM), current sources (CS) and voltage switched current sources (VSCS). These four building blocks implement four linear functions described in Sec. 1.5 necessary to

make larger functional blocks. Input and output values in CMMVL have to be integer

multiples of the unit step current.

In this chapter we will propose architectures of the two CMMVL adders and one

approach for dynamic-mode CMMVL adder.

MVL current-mode system

FI r--- chip level memory multiplier adder 4 1 functional blocks

Figure 2.1. Hierarchical structure of a current-mode system

2.1 CMMVL Adder Using Positive-Digit Adder (PDA) Cells Implementation of the adder was determined by the logic description given by Eq.

1 to Eq. 6 in Sec. 1.3. Straightforward symbolic representation of the algorithm is shown

in Fig. 2.2. Execution of the fist step, Eq. 4, is performed by simple wiring of signals xi

and yi at common node, Ni. This is actually operation "for free" in CMMVL adders. Block

labeled "PDA" is where execution of Eq. 5 takes place. The internal structure of this block

will be presented in Sec. 5.1. Step 3 (corresponding to Eq. 6) is performed by, again, tak- ing advantage of current-mode operation and "free" addition of the current outputs from

the PD adders by wiring proper outputs from the PDA cells.

From diagram in Fig. 2.2 [4] it can be seen that design of the PDA will be simpli- fied very much by using CMMVL because only Eq. 5 has to be actually implemented. It

should be noted that the operation is carry-propagation free, in other words execution of

the steps goes in parallel for all the digits.

Figure 2.2. The PDA based on radix-2 PD number representation

2.2 Decimal n-Digit CMMVL Adder

Symbolic block diagram of circuit that implements decimal algorithm for two n-

digit numbers addition, S = A + B, where A = (ag, a1 ,..., aj ,..., a,) and B = (bo, bl ,..., bi ,..., b,), is shown in Fig. 2.3. Again, we take advantage of current mode operation by execut- ing the summation of the numbers by wiring at the input of the single-digit decimal adders

(SDDA). In the SDDA blocks execution of Eq. 7 and Eq. 8 take place. Internal structure of the SDDA cell will be proposed in Sec. 5.2. Inherently, this algorithm has carry-over prop-

agation chain, but addition of carry-over digit Co to the subsequent digit is performed by

wiring of the node to the input of the following SDDA, Fig. 2.3.

Based on algorithm presented in Sec. 1.4 it is obvious that the SDDA blocks must

have resolution of 20 levels of the current signal. The levels will be determined after we

design the basic building blocks in CMOS technology.

I I Sn Sn-1

I ... s2 I s1 so I

Figure 2.3. Block diagram of the n-digit CMMV decimal adder

SDDA

I

2.3 CMMVL Dynamic Mode Adder

In addition to the above two "static" versions of CMMVL adders, here we propose

dynamic approach to design a CMMVL adder. This approach comes as a result of a cur-

rent comparator operation mode that requires clock pulses for its operation. The unit cur-

rent step for the dynamic adder shown in Fig. 2.4, set at node ISO by external resistor, is

fed into array of 10 p-type output current mirror (CM). Each output can be set to its own value miISO, by scaling the mirrors. Current sum of two numbers, hata and 0.5b, comes through array of nine n-type current mirrors. This simple operation results in reducing

sizes of transistors required to set the mirrors output currents. The array of n-type current

mirrors generates identical current at all the outputs, Iref = h;, + 0.510, to the array of closed-loop current comparators (CC). From the other side p-type array generates 10 cur- rent levels for comparison with the IreF The array of CC compares each level miISO with

Ire, in parallel and generates voltage outputs Vi from each CC. The CC's execute the com-

parison operation synchronized with the clock pulses at node "clk". Outputs from the

array of DCC would go to decoder block where decoding would be performed depending

of what numerical representation is used and what adding algorithm is implemented. This

circuit will be built without the decoding part for the purpose of performance evaluation

and comparison with adders presented in Sec. 2.1 and Sec. 2.3.

array of 10 ptype CM mi IS >

ldata n-type CM

T) DECODER

dk D 1 Figure 2.4. Block diagram of dynamic CMMVL adder

CHAPTER 3 Basic Building Blocks of Current-Mode Multiple-Valued Logic (CMMVL) CMOS Integrated Circuits

In this chapter we will discuss practical realization of arithmetic functions intro-

duced in Sec. 1.5. They will be materialized here in a form of basic building blocks in

CMOS technology. CMOS current mirrors (CM) will serve as the linear function genera- tor; CMOS current comparators (CC) will serve as the step function generator; current sources (CS) will be materialized in form of either single NMOSPMOS transistors or in form of current mirrors and will generate the constant function; and voltage-switched cur-

rent source (VSCS) will be used as the general step function generator. Ln some of the pro- posed configurations the ordinary CMOS transistors will be replaced by Super MOS

transistors [13] for an improvement in low-current operations.

3.1 Super MOS Transistor

Single MOS transistor is basically a current mode device [I]. However, a typical MOS transistor has a moderate low output resistance comparing to its input resistance,

which makes it not as good current source device as one would like it to be. Therefore,

techniques, such as cascoded transistor configuration, have been developed with idea to

increase the output resistance and make it a better approximation of the ideal current

source.

The Super MOS is a compound circuit which behaves like a cascoded MOS tran-

sistor and has, like a regular MOS transistor, a source, a gate, and a drain terminal. How-

ever, it has an extremely high output impedance due to implementation of the gain-

boosting technique [13]. Moreover, it does not require any biasing voltage or current other than one single power supply. The circuit of an n-type Super MOS transistor is shown in

Fig. 3.1, while p-type Super MOS transistor is complementary structure. Transistors MI

and M2 are the main transistor and its cascode transistor respectively. The circuits mimics

DC transfer characteristic of a single n-MOS transistor of the same size as the MI, except

that operational gate voltage VGS for this circuit is considerably lower and, of course, the

output resistance is order of magnitude higher. The two features make this "device" very

promising candidate for low-power low-current applications.

4 b) Figure 3.1. Super NMOS transistor (a) and its schematic symbol (b)

3.2 Current Mirrors (CM) Current mirrors for applications in CMMVL circuits must feature very good lin-

earity and good transient response over several decades of the input signal. Here, four ver-

sions of current mirror will be designed and compared with intention to optimize them for

CMMVL applications: simple two-transistor current mirror (SCM), cascoded mirror (CCM) [14], high-swing cascoded current mirror (HSCM) [15], and two-transistor cur- rent mirror with the Super MOS transistors instead of single transistors (STCM) [13]. A desired parameters of current mirrors are:

- the output current should be dependent of the voltage VOUT as little as possible;

the signal mirror ratio M=IO&IIN; should depend of the magnitude of the currents,

over many decades of the input current, as little as possible;

minimum saturation voltage VDS(SAT); where a current mirror still operates properly, should be as low as possible. The difference between the power supply voltage and

VDS(SAT- determines the operating range of the current mirror. high-fieqwncy pe~ormance; current mirrors will be used in input stages of CMMVL circuits and, therefore should have sufficient transient response time to a current pulse

signal.

3.2.1 Basic Current Mirror Configurations

There are two well known current mirror configurations: simple two-transistor cur-

rent mirror (SCM) and cascoded mirror (CCM) [14]. The two are very simple and efficient configurations (Fig. 3.2). They will be compared to the two configurations known as high- swing cascoded current mirror (Sec. 3.2.2) and current mirror with Super MOS transistors (Sec. 3.2.3) in terms of the above mentioned desired performance.

Figure 3.2. Simple current mirror (a) and cascoded current mirror (b)

3.2.2 High-Swing Cascoded Current Mirror (HSCM) Although cascoding transistors increases the output resistance of a current mirror it

does so at the cost of reduced linear output voltage range [15]. This comes from the fact that each transistor in the bias circuit is diode connected, and as a result, is not very effi-

cient at providing the smallest possible drain-source voltage across each transistor to

maintain them in saturation. The circuit in Fig. 3.3 illustrates one way of biasing the tran-

sistor chain MI to M2 such that the minimum drain-to-source voltages are achieved. The

operational range of HSCM is limited by current source I,, that sets upper limit for the

input current line Outside of that limit the output current IOut begins to differ from the input

current Ii, significantly.

1 - 1 - - -

Figure 33. High-swing cascoded current mirror (HSCM)

3.2.3 Current Mirror with Super MOS Transistors (STCM) As it was mentioned in Sec. 3.1 the Super MOS transistor block has characteristics

which make it very promising candidate for low-voltage low-current applications. Its

modularity is also useful feature because the upper level designs can be made as same as if

the simple transistor were used. For example, current mirror with Super MOS transistors

(STCM) is made by simple replacement of the two transistors in SCM with Super MOS transistors, Fig. 3.3.

1 'out

Figure 3.4. Current mirror with the Super MOS transistors (STCM)

3.3 Current Comparators (CC) Step function described in Sec. 1.4 will be implemented by using a current com-

parator. In CMMVL applications this block has to have both good resolution and transient

response. Its performance has significant influence on operation of the upper level design

modules. In order to distinguish n-levels of signal in a data bus it is crucial that the current

comparators are designed and optimized for the particular operational conditions. Current

comparators can be implemented in two ways: as an open-loop comparators and as an

closed-loop current comparators. In this section we will consider two versions of open-

loop designs: with current output and voltage output, and one version of closed-loop

design, that are going to be used in coming CMMVL designs.

3.3.1 Open-Loop Current Comparator

Simple realization of an open-loop current comparator with voltage output is

shown in Fig. 3.5a. Basically, voltage at the common node for the input current source, Ii,,

and the reference current source IEf, swings between some two values Vmin and V,,.

The two-inverter chain at the output restores these voltage levels to the VDD and VSS.

Design shown in Fig. 3.5b is one possible configuration where current output is

generated from the current comparator [7] . In this design input current Iin is compared with Iref preset by M1 and its reference voltage VEf at node 1. Therefore, voltage at gate of

Figure 3.5. Open-loop current comparator with voltage output (a) and current output (b)

transistor M3 is turning "on" and "off' transistor M3, which serves as a switch between the

current source M2 and the output terminal.

This type of a current comparator is very popular due to its simplicity and little

space it occupies [16]. Nevertheless, transient response time of these current comparators can be long especially when Ii, is very close to Iref.

3.3.2 Closed-Loop Current Comparator

Closed-loop current comparator whose operation is based on the positive feedback

loop of two back-to-back inverters [16] is shown in Fig. 3.6. Its operation is controlled by

Figure 3.6. Closed-loop current comparator

clock signal pulses. While the clock is at its high level, the switches M5-M6 are closed and

potentials at both nodes N1 and N2 are equalized to V D d 2 regardless of relation between

Ii, and IEf. When the clock changes its state to low level and opens the switch Ms and M6,

there is potential difference (caused by currents Ii, and IRf) between the nodes N1 and N2 that will be amplified by the feedback loop. Two possible outcomes can result from that

action: a) if IinIEf, the output voltage Voutl will oscillate between VDD and VDd2. VOut1 and Vout2 deliver complementary signals in phase with the clock reference.

3.4 Current Sources (CS) Constant function from Sec. 1.5 will be implemented as a current source. 'For

experimental designs the current sources can be implemented as external resistors while

some of presented versions of current mirrors will be used as on-chip current sources. The

current mirrors will operate in continuous mode delivering constant current output inde-

pendent of the rest of the circuitry.

3.5 Voltage-Switched Current Sources (VSCS) Implementation of general step function introduced in Sec. 1.5, basically, requires

an voltage control source, a switch logic block, and a reference current source [26]. The voltage switch can be as simple as a single transistor or it can be a combination of n-MOS

T

switch voltage control block

Figure 3.7. The VSCS block diagram

and p-MOS transistors depending of the function F(X), Fig. 3.6. The current b will reach the output terminal only when the logic function turns "on" the switch logic block. The

entire building block is called voltage switched current source (VSCS).

CHAPTER 4 Design and Implementation of Basic Building Blocks for CMMVL Circuits in Digital CMOS Technology

In this chapter practical realizations of the basic building blocks introduced in

Chapter 3 will be presented. Circuit examples in this chapter will be designed in Mite1

1.5pm CMOS technology available through Canadian Microelectronic Corporation. This

technology was optimized for the 5V power supply voltage.

The goal here is to optimize the blocks for applications in proposed CMMVL

adders and to explore the technological limits in terms of low-current operation. There-

fore, a long-channel transistors will be used very often in most of the following designs.

Based on results obtained from experiments in this chapter we will propose specifications

of the adders feasible in a digital CMOS technology.

First, we will present design of Super MOS transistor because this block can be

used as a basic building block for all upper level designs. In the following section design

of current mirrors will discussed, followed by discussion of current comparator design.

4.1 Design of the Super MOS Tkansistor In order to verify behavior of the Super MOS transistor we designed and imple-

mented it in the CMOS technology as one of the CM building blocks. Its DC transfer char-

acteristics as well as its transient response has been next compared with those of

equivalent single MOS transistor.

From the circuit description in [13] and Sec. 3.1 first design consideration becomes obvious: cascoded transistors MI and M2 are the biggest two transistors in the circuit and

they are going to take most of the circuit's area. On the other hand the size ratio between

the two will have big influence on the overall circuit performance. Basic idea was to make

this circuit as a modular block for wide range of sizes of the two transistors. We decided to

use the minimum channel length of 1.5pm for all transistors, make it constant, and to

make the width of the M1 and the M2 variable, Fig. 3.1. Furthermore, we will use the same

two-stage amplifier for all sizes of the M1 and the M2. We found fiom simulation that ratio

of 5 to 1 for the M2 width versus the M1 width is good enough ratio above which the out-

put resistance does not change significantly. Using higher ratio would only result in bigger

sizes of the cascoded transistors without significant improvement in the output resistance.

By doing the above steps we have designed parameterized modular block that has

only one parameter in its description: width of the M1 transistor. Therefore, width of the

M1 transistor is variable, the length of M1 is 1.5pm, width of the M2 will be always 5

times width of the M1, the length of M2 will be as well 5 times longer then the length of

M1 e.g. 7.5pm, and lengths of the rest of the transistors will be 1.5pm. Diagram in Fig. 4.1

shows simulated DC transfer curves for Super NMOS transistors in range of 25pm to

lOOpm as well as the curves for a single NMOS transistor of the same size.

VGS = 0.9V VGS = 3 V

Vds [VI LEGEND:

............. NMOS - Super NMOS

Figure 4.1. DC characteristics of Super NMOS transistor and a single NMOS transistor

It can be seen that the single NMOS transistor, at VGS=0.9V, exhibits an Early

voltage of less than 5V whereas the Super MOS has an Early voltage which is several

orders of magnitude higher. At VGS'3V a single transistor exhibits an Early voltage

around 10V, while the Super NMOS transistor is again several orders of magnitudes

higher. Note that the "device" is already saturated at voltage only slightly above the satu-

ration voltage of one single NMOS transistor indicating a large possible output swing.

Another important characteristic that should be compared is transient response of

the two devices. Fig. 4.2 shows transient response of the two devices under the same test

conditions: VDD = 5V, W = 5pm, L = 1.5pm excited by the same pulse (Vh=5V, t, = Ins, tf = Ins, pulse width is 20011s). Note that delay time of the Super MOS transistor is consid- erably longer in comparison to a single transistor. Here, it can be seen that the delay time

is in order of 5011s for the Super MOS transistor vs. a few ns for a single transistor. So the

improvement in high output resistance is compromised by degraded high frequency per-

formance.

I LEGEND:

-25 0 50 100 150 200 250 300

time [ns] Figure 43. Transient response comparison for the transistors

Both NMOS and PMOS versions of Super MOS transistor were designed and

saved as modular blocks that can accommodate transistors in wide range of sizes, Fig. 4.3.

Figure 43. Layout of the Super NMOS transistor (38pm x 9 0 ~ )

In Fig. 4.4 testing result of the actual circuit are presented. It can be seen that the

circuits indeed exhibit very high output resistance. Furthermore, the simulation results are

more accurate for low VGS voltages which is one of the side effects of the design. The best

operational results of the circuit can be expected for VGS in range of 0.9V to 1.2V. From

the above experiment we can conclude that Super MOS transistor is feasible and can be

LEGEND: - test

......................................................... J - - - - . simulation

vGs=2.3v

Oo 1 2 3 4 5 Vd, M

Figure 4.4. Testing vs. simulated results of the Super NMOS transistor

used as a basic building block in higher level designs. However, we should keep in mind

that cost for improved output resistance of the block is in lower operating speeds of the

circuits and, in some cases, increased space requirements.

4.2 Design of Current Mirrors

The purpose of experimenting with current mirror configurations (Sec. 3.2) is to develop circuits capable of generating the linear function described in Sec. 1.5, including

its trivial case - constant function that would represent current source. Current mirrors for

applications in CMMVL circuits must have very good linearity and fairly good transient

response over several decades of the input signal. Target range for the current signal will

be below lOOpA for the CMOS technology. We expect fiom this experiment to determine

lowest possible limit for the unit current step that we can obtain from the technology. Cur-

rent mirrors in this chapter were designed by using the same size transistors for all four

versions: W=3.3pm, L=4pm. Size of the transistors was chosen to compare all configura-

tions at 10pA output current, and by no means represent the best optimization for all them.

In the evaluation we will consider: DC transfer curve but vs. Vout, where Vout will be

Output Voltage [V]

LEGEND: .....

-

STCM HSCM CCM

- SCM

Figure 45. Comparison of I-V characteristics for the current mirrors

swept from OV to 5V and Iin is 10pA; accuracy IOut vs. Iin over range for the Iin from

lOnA to 100pA; and transient response of all the circuits to a current pulse of 200ns

length, with rise and fall time of Ins and amplitude of 10pA.

DC characteristics: In Fig. 4.5. DC transfer curves are shown with emphasizing

saturation voltage VnS(SAn. It can be seen that ST current mirror is superior to the other current mirrors: it can operate properly right above saturation voltage for a single transis-

tor (in this technology 0.35V). It indicates that this configuration has a good potential for low power applications.

Sensitivity: In order to determine working range for proposed current mirror con-

figurations the circuits were tested under the same conditions. The output load was ideal

voltage source holding potential of the output node at 2.5V. This value was chosen as

acceptable

40

30

20 -

- 10 0 2 X

-20

-30

-40

output node potential for all involved current mirrors, because diagram in Fig.

-50 1 e-02 le-01 1 e+00 1 e+01 1 e+02 1 e+03

Input Current [pA] Figure 4.6. Sensitivity of the current mirrors

4.5 shows that above 2V all the circuits are already saturated and they generate proper

copy of the input current.

By comparing the sensitivity of the mirrors (Fig. 4.6) one can see that the current mirror built by using Super MOS transistors features superior accuracy over the entire

range from lOnA to 401A of the input current. It is interesting to note that cascoded con-

figuration shows identical results in the range up to 301A, and with its smaller complexity

and much better high-frequency performance it will be a potential candidate for high

speed applications.

Transient response: As it was mentioned earlier, the circuits were excited with

the input current pulse and the response was observed at the output load resistor. Value of

the resistor is not critical therefore value of 1KR was used. Ideal current pulse source of

lO1A was chosen as, again, acceptable low current value for all the circuits.As we

expected STCM has the worst transient response, since it is the most complicated struc-

ture, among the four, Fig. 4.7. It's delay time at rising edge is in order of 200ns, which is

much worse in comparison to approximately 30ns delay time of the others. At the falling

edge all the circuits have similar response.

15 I I . I

LEGEND: I I I I I I ..

I I I I .,.., *.. , I

STCM I * .................. I I '

HSCM ..A. . 10 - ....A. *.,A. ......... CCM

/' SCM / input pulse 5 / = 5 - ,,.,/ / /" 2 0 -

j - , .: ,

0

L 3 : -5 o

1 1

100 time [ns] 200 300 Figure 4.7. Transient response of the current mirrors

4.2.1 Implementation Results

One batch of Mitel chips containing STCM and HSCM (Fig. 4.8) current mirrors has been fabricated.

Figure 48. Photomicrograph of the HSCM cell ( 2 1 5 ~ x 73pm) (a); and STCM cell layout (75pm x 95pm) (b)

Testing results of HSCM, Fig. 4.9, show relatively wide distribution of the output

current characteristics for sample of 53 cells originally designed for but = 10pA set by internal transistor. As it can be seen from the diagram that most of the output current error

is as high as 30% and possibly results from poor transistor matching in manufacturing pro-

cess. Obviously, external current source should have been used to provide tuning capabil-

ity for this current mirror (resistor would have done fine) as well as some of transistor matching techniques.

I LEGEND:

Figure 4.9. Distribution of results for HSCM in Mitel 1.5pm CMOS

The STCM sensitivity was compared with the simulated characteristics, Fig. 4.10.

It should be noted that accuracy of the models for this technology is obviously not suffi-

cient for low-current simulations. Mismatch between simulated and measured results is

obvious in range below 1pA. However, accuracy of the STCM in range of input currents

of up to 200pA is better than 5% which proves the statement made before that this type of

current mirror is suitable for high-accuracy low-current applications.

Input Current w] Figure 4.10. Measured sensitivity of the STCM

4.3 Design of Current Comparators In this section structures presented in Sec. 3.3 will be examined. Optimization of

current comparator is one of key steps in the design of basic building blocks for CMMVL

applications. It's speed and accuracy are two major issues that determine overall behavior of the arithmetic CMMVL circuits. At the end of this experiment we should have avail-

able additional specifications for the adders such as maximum resolution and speed that

will be implemented in the design.

4.3.1 Examples of Open-Loop Current Comparators

This type of current comparators (Fig. 3.5) is usually not designed as a stand alone building block. Their operation is closely related to the surrounding blocks as well as the

layout design. Therefore, we will evaluate the comparators in simulated environment by

using current mirrors both as a source of reference current IEf and as a source of input cur-

rent Iin+

Simulated DC transfer characteristics of the two static current comparators from

Fig. 3.5 is shown in Fig. 4.11a. Reference current Iref was set to 20pA by choosing proper

size of a transistor that serves as the current source. Input current was swept from OpA to

30pA and the outputs were observed. Diagram in Fig. 4.1 l a shows comparative normal-

ized DC transfer curves of both voltage and current outputs. Resolution of the current

comparator with voltage output is in range of 500nA to 800nA, depending what error rnar-

gins are acceptable for the output voltage levels while resolution of the current comparator

with current output is approximately 250nA. It should be noted that chain of two inverters

have to be used in output stage of the current comparator with voltage output in order to

achieve this level of resolution.

LEGEND: ........ current response - voltage response

a) Input Current [pA] b) time [ns] Figure 4.11. DC transfer curve (a) and transient response (b) of the open-loop current comparators

Transient response curves of the open-loop current comparators are shown in Fig.

4.1 1 b. The comparators were excited by a current pulse Ii, = 20pA with rise and fall time

of 1 ns and length of 150ns. As they have similar configurations and the complexity, delay

times are in range of 1511s to 30ns for both of them.

4.3.2 Example of Closed-Loop Current Comparator

Closed-loop configuration is aiming at better resolution than conventional open-

loop current comparators. Purpose of experimenting with this stand-alone block is to

determine how it could be applied in CMMVL circuits and to find out if price in space and

complexity of this circuit is not too high for possible gain in speed.

This circuit was simulated for the reference current set to IEf = 20pA, and since

this is dynamic circuit, input current Ii, was set to I i , = Ird+ A, where A represents the

resolution. It was determined that the minimum resolution for this circuit, in Mite1 1.5pm

CMOS technology, is 250nA. Diagram in Fig. 4.12 shows the output voltage signal shape

of the circuit for two input currents: Ib=20.25pA and Ii,=19.75pA. It can be seen that

delay time is determined by the clock. In this technology the fastest clock used was 25ns

input signal LEGEND: *,..,..., lin= 19.75pA

200 300 time [ns]

Figure 4.12. Transient response of dynamic current comparator

half-cycle. That time determines delay time of the output signal. However, resolution of

200nA has been reported for this type of a current comparator in 1201. The layout of pro-

duced circuit is shown in Fig. 4.13.

Figure 4.13. Layout of the closed-loop current comparator ( 3 8 p x 9 8 p )

Testing results of this circuit are presented in Fig. 4.14. The diagram shows a

quasi- transient output from the circuit. Operation of this type of the circuit is based on the

clocking signal, therefore real transient analysis is possible only by using an oscilloscope.

In order to present the transition of the output voltage which shows exact moment of

crossing the reference current the following method was applied. External clock generator

delivering 5Hz positive square pulses from OV to 5V was used. HP Semiconductor Para-

metric Analyzer was used to: generate VDD=5V, to generate 1,f-150pA, to generate a

1001-step sweep DC current ranging from Ii,=lOOpA to 300pA, and to measure the out-

put voltage VOut. The slow clock rate was well synchronized with the sweeping rate deliv-

ering diagram in Fig. 4.14. However, fast clocking measurements of more than 5OOKHz

were observed using oscilloscope. Estimated resolution of this circuit is better than lOpA

~ ~ 0 ~ 1 ~ 0 ~ 1 ~ 0 ~ 1 ~ 0 ' 1 ~ 0 ~ 1 ~ 0 160 170 180 190 200 Input Current [pA]

Figure 4.14. Measured results from the closed-loop current comparator cell

4.4 Implementation Results

During this part of the research work the following basic building blocks were

manufactured and tested: Super MOS transistor, HSCM, STCM and closed-loop current

comparator. The first testing results were promising, however, it should be noted that the

simulation models in Mite1 technology are not sufficient for low-current simulations. Fur-

thermore, spread of testing results is quite wide, due to both low accuracy of the models

and the device mismatches.

From the above experiments we can conclude that Super MOS transistor exhibits

very low saturation voltage and very high output resistance. Current mirrors based on this

circuit demonstrate superior linearity over several decades of input current. In comparison

with HSCM space occupation is lower, however, both STCM and CCM are smaller. Also,

speed limitations set by the two stage amplifier have to be kept in mind. Open-loop config-

uration of current comparator is simpler for realization, while closed-loop configuration

has potentially better resolution and higher speed of operation.

CHAPTER 5 Design and Implementation of Current- Mode Multiple-Valued Logic CMOS Adders

Previous chapters presented development of basic building blocks required for

design of CMMVL adders presented in Chapter 2. In this chapter design and implementa-

tion results of the CMMVL adders will be presented.

5.1 Design of CMMVL Positive-Digit Adder (PDA) Architecture of CMMVL adder using the PDA cells was presented in Sec. 2.1.

Here, internal structure of the PDA cell suitable for implementation of radix-2 positive

algorithm that requires seven levels of the input current signal will be presented. Function-

ality of the block was described by Eq. 5.

5.1.1 The PDA Cell Specification

Symbolic representation of the PDA cell is shown in Fig. 5.1. The CMMVL adder

has been designed and manufactured using the Northern Telecom 0.8pm CMOS technol-

ogy. After fine tuning, the current of 11pA was chosen as the unit current step.

Pin description of the cell is shown in Table 1. Transfer function of the block is

presented in Table 2. In this case existence of the 11pA unit current at the corresponding

node is represented by the number "1" and its absence is presented by the number "0".

Figure 5.1. Symbolic representation of the PDA cell

TABLE 1. Pin description of the PDA cell

Pin Function Signal description Z i - input input signal is current that represents sum of two augends and

can have discrete values equal to multiplies of the unit current

step miISO where mi E (0, 1,2,3,4: 5,6} . The input current levels are: 0, l lpA, 22pA, 33pA, 44pA, 55pA, 66pA.

S i - output sum output current signal level is either OpA or 11pA. ci(') - first par- intermediate current level is either OpA or 11pA.

tial sum - second intermediate current level is either OpA or 11pA.

partial sum

TABLE 2. Logical table for the PDA cell

5.1.2 The PDA Cell Circuit Description

The circuit realization is based on set of current comparators and voltage con-

trolled current sources (VCCS). Each change from "0" to "1" and vice versa has to be detected and decoded properly by the switch in its VCCS. One stage of the cell is shown

in Fig. 5.2. Voltage switched current source (VSCS) consists of current source IO and switch. Current comparator consists of current source Iref and current source M,. The

switch will be closed or opened based on potential at the node 1. Straightforward setting

of the reference current levels would be: 0.5, 1.5, 2.5,3.5,4.5, and 5.5 times b. However, by doing so multiple output current mirrors that generate the current values would end up

with very long transistors. One possible approach to this problem is to do a simple adding

operation at the input stage and use half values of the current levels and, therefore, use half

Figure 5.2. One

-I- -L * I ' - , ~ = - 2

stage of the PDA: current mirror, current comparator and VCCS

size transistors. The input stage of current mirror (MI, M2, M,) consists of two identical transistors M1 and M2 effectively dividing the sum of zi and b/2 by two. That value is

being copied through M, and compared with Irefi NOW, the reference currents, IRf, are set

to: 0.5, 1. 1.5, 2, 2.5, and 3 times IO resulting in much smaller transistors.

Complete schematic diagram of the cell is shown in Fig. 5.3. Full implementation

the single VSCS stages is now obvious.

Figure 53. Schematic diagram of the PDA cell [6]

5.1.3 The PDA Cell Characterization

Testing and characterization of the cell was performed using HP SPA under the

following conditions: VDD=3.3V, Ii,=O to 70pA, RlOad=50Q for all the outputs.

From the diagram in Fig. 5.4 it can be seen that the PDA cell indeed executes Eq. 6

according to the logical table Table 2. For example, for Ii,=33pA (logic level 3) the out- puts read: si=l lpA, ~ ~ ( ~ ) = 1 lpA, C ~ ( ' ) = O ~ A , which corresponds to the levels 1, 1, 0 as in Table 2.

15 r , LEGEND: - measured

- 9 1 0 / ~ \ , , b-

.n .A,%, 1 . . . . . . . . . simulated 5 I 4

I I I I

0 (j- I 10 20 30 40 50 60 70

"0 10 20 30 40 50 60 70

lin [PA] Figure 5.4. DC transfer characteristics of the PDA cell

Batch of 27 PDA cells was manufactured and tested. All the falling edges are over-

lapped with the rising edges and spread of the DC characteristics is shown in Fig. 5.5.

Here I, denotes the measured current at the rising or falling edge for Iou,=5.5pA. It can be

seen that the distribution of the results is within +2pA which can be viewed as a sufficient

noise margin for the unit current step IS0 = 11pA.

1,- 3 1,- 2 I,- 1 1 x 1

I,+ 1 I,+ 2 I,+ 3 Iin MA1

Figure 5.5. Noise margins for the PDA cell

Simulated delay diagram time for rising edge td, and falling edge tdf is shown in

Fig. 5.6 for the input current in range of lOpA to 70pA. The outputs have different delay

times due to different complexity of VSCS at the outputs. The worst case delay time is

close to 80ns. LEGEND: - td, ........... tdf

Figure 5.6. Delay time for rising edge (td,) and falling edge (tdf) of the PDA cell

Photomicrograph of the cell is shown in Fig. 5.7. Size of the cell is 1XOp.m x

75pm. Dynamic power consumption of the cell is 775p.W, while DC power consumption ~

Figure 5.7. Photomicrograph of the PDA (180pm x 75pm in CMOS 0.8pm)

5.2 Design of CMMVL Single-Digit Decimal Adder (SDDA) Sum of two decimal digits is in range of 0 to 19. Therefore, the single-digit full

adder must be able to distinguish 20 levels of the input current signal: 0, lpA, 2pA, ...,

18pA, 19pA assuming that the unit current step is 1pA.

5.2.1 The SDDA Cell Specification

Symbolic representation of the SDDA cell is shown in Fig. 5.8. The CMMVL

adder has ben designed in the Mite1 1.5pm CMOS technology. This cell was designed for

the unit current step of 1 PA.

Figure 5.8. Symbolic representation of the SDDA cell

Pin description of the SDDA cell is shown in Table 3. Standard decimal numerical

presentation and adding algorithm described in Sec. 1.4 was implemented.

TABLE 3. Pin description of the SDDA cell

Pin Function Signal description z i - input input signal is current that represents sum of two augends and

can have discrete vahes equal to multiplies of the unit current

step ISO=lpA where zi E {OpA, lpA, 2pA, ..., 19pA) S i - output sum output current signal can have values

C O ~ - carry-over carry-over current signal can have values either OpA or 1pA. signal

Transfer function of the block is presented in the Table 4. Here, each number from

zero to nineteen is represented by current levels at both the sum pin and the carry-over

pins. For example number 15 (represented by current level of 15pA at the input pin zi) is decoded as lpA current at the carry-over pin and 5pA current at the sum pin. Number 4 is

decoded as OpA current at the carry-over pin and 4pA current at the sum pin.

TABLE 4. Logical table for single-digit decimal adder (SDDA)

5.2.2 The SDDA Cell Circuit Diagram

The SDDA cell is built of 5 current mirrors and a single current comparator, as

shown in Fig. 5.9. Low-current inputs use current mirrors with Super MOS transistors (n- type ST,, p-type STp) while high-swing current mirrors (HSCM) (n-type CM,, p-type CM,) were used everywhere else in the cell. The addition of the two currents 11=(0, lpA, ..., 9pA) and I2 = (0, IpA, ..., 9pA) is performed by wiring the two currents into the common node Ii,. The SDDA cell has ST, (I) mirror as the input stage to read the input

1CrA i switch

Figure 5.9. A single-digit decimal CMMVL adder (SDDA) internal architecture

current Ii, and generate two identical replicas of the current. One copy goes into the output

current mirror CMp (2) while the second copy goes into the open-loop current comparator (CC), where it is compared against the 9.5pA reference current set by CM, (3). If Iin is smaller than 9.5pA, the switch stays open, resulting in the output signals S = Iin and C,=O.

When the input current Iin > 9.5pA, the current comparator turns the switch on, effectively

connecting the 1pA current source STp (4) to the C, output and the lOpA current source to the common node, producing the output signals C, = 1pA and S = Iin - 10pA.

5.2.3 The SDDA Cell Characterization

Characterization of the cell was performed under the following conditions:

VDD=5V, Iso=lpA, I,= 0 to 19pA, RlOad = 1 KR for both the outputs.

Simulated DC transfer characteristics of the SDDA is shown in Fig. 5.10. for the

input current from OpA to 19pA. Upper diagram represents DC transfer characteristics of

the sum pin si. It can be seen that the output current follows the input current level up to

9pA. For the input currents higher of lOpA the output current level is lOpA lower than the

input current which is in fact realization of the Eq. 7. The carry-over pin generates OpA for

IhlOpA which is in agreement with the Eq. 8 and Table 4.

I, [PA] Figure 5.10. DC transfer characteristics of the one digit adder

Layout of the SDDA cells is shown in Fig. 5.1 1. It can be seen in upper right cor-

ner of the SDDA cell that HSCM was used as 9.5pA reference source, also STCM were

used for input current mirrors (left side of the SDDA cell). The size of the adder is 392p.m x 150pm in 1.5pm CMOS (the manufactured SDDA cell has not been manufactured yet due to delay in the production).

Figure 5.11. Layout of the SDDA ceU (392pm x 150pm in CMOS 15pm)

5.3 Design of Dynamic CMMVL Adder

As it was mentioned in Sec. 2.3 this design is for demonstrational purposes only.

The circuit was designed in Mite1 1.5pm technology and it is entirely based on the Super

MOS transistor current mirrors (STCM) and closed-loop current comparators.

Simulated output from this cell is shown in Fig. 5.12. Input current signal for this

cell is shown at the top of the figure. There are ten levels of input current from OpA to

270pA in steps of 30pA. Shape of the output signals is already known and have been

described in Chapter 3.3.2. The clock cycle was 100ns.

It is visible from the diagram how the ten levels of the current comparators were

set producj

" 0 1 2 3 4 5 time [ms]

Figure 5.12. Simulated output from ten-level dynamic CMMVL adder

Layout of this circuit is shown in Fig. 5.10. It is obvious that complexity of this

circuit is much grater than the other presented in this thesis. Consequently, the space occu-

pancy is prohibitively high. It is obvious that the choice of working algorithm is the most

important decision in this kind of design.

Figure 5.13. Photomicrograph of dynamic CMMVL adder (first stage) (415pm x 426pm in 1.5pm CMOS)

5.4 Comparison of CMMVL adders with voltage-mode binary adders

Even the concept of multiple-valued logic is fairly old, it is in last several years

when VLSI technology has advanced to the point to allow design of first working

CMMVL circuits. Therefore CMMVL circuits are at the very beginning of the develop-

ment and optimization process while voltage-mode binary logic is mature, very well opti-

mized technique. Full comparison between binary and CMMVL adders is yet to be done

in the future.

Voltage-mode binary adders are still faster and occupy less area in comparison

with presented CMMVL adders [28]. A typical 16 bit binary-coded-decimal adder occu- pies 164,828p.m2 in 1Spm CMOS [28], while four-digit CMMVL adder made of four SDDA cells occupies around 1 9 0 0 0 0 ~ m ~ which is about 13-15% smaller area. Potential

advantage of CMMVL addition over binary counterparts in both area and speed can be

expected in a long-word multipliers as suggested in [4] [6] [7].

CHAPTER 6 Conclusions

Concept of current-mode multiple-valued logic (CMMVL) was studied and pre- sented. As a result of effort put into this thesis work a set of basic building blocks for

CMMVL applications was manufactured and examined. The building blocks were used in

higher level of design for two versions of working CMMVL adders and one demonstra-

tion version of dynamic mode-mode circuit.

One of the conclusions from this thesis is that choice of numerical representation

and adding algorithm is the most important factor for success of the approach. The algo-

rithm determines number of required signal levels and, therefore, feasibility in today's

ULSI technology. It has been demonstrated that circuits built in today's CMOS can distin-

guish up to 20 levels of current signal. However, reported MVL circuits in voltage mode

used up to 4 levels of voltage signals.

Obviously low-power voltages of 3.3V, and below, will even more support choice

of current mode approach. It should be noted, once more, that carry-over propagation free

algorithms (such as radix algorithms) have clear advantages for long-words operations due to the fact that the operational time of the single step can be even slower than in usual

binary application, while the overall executing time is independent of the word length.

Radix algorithms proved useful for MVL applications. First CMMVL adder cell

called positive-digit adder (PDA) was designed in 0.8pm CMOS technology, powered by VDD = 3.3V, with seven levels of current signal using unit current step ISO = 1 lpA and

implemented positive-digit radix-2 algorithm, noise margins are less than 20%, and the

size is 180pm x 75pm. In comparison PDA cell from [4] was designed in 5pm CMOS, was powered by VDD = 5V, used ISO = 70pA, with noise margins approximately 30%,

and occupied 252.5pm x 450pm of silicon space. The improvement in effective area is

25%, in noise margins approximately 3096, while maintaining the same level of delay time

of approximately 70ns. Both designs proved feasibility of the concept, with clear advan-

tages showing when a more advanced CMOS technology was used.

The second design was single digit decimal adder (SDDA) designed in 1.5pm CMOS technology, powered by VDD = 5V, with ten levels of current signal using unit

current step ISO = l pA and implemented decimal current adding algorithm. Size of the cell

is 392pm x 150pm. Effective area is close to the PDA design in 0.8pm, but the unit cur-

rent step is extremely low. Lower current will result in longer delay time (estimated worst case delay time is around 200ns). Application of current mirrors using the Super MOS transistors and open-loop current comparators with voltage output decreased the unit cur-

rent step down to 1pA. However, overall complexity of the adder circuit is increased sig-

nificantly. It should be noted here that area of the decimal adder is larger than area of a

typical binary adder in the same technology. Full advantage of CMMVL approach in sav-

ing silicon area can be expected in higher level designs such as CMMVL multipliers.

In the last presented design yet another approach was demonstrated. The circuit

was built by using current mirrors built of the Super MOS transistors, and closed loop cur-

rent comparators. The increase in overall complexity of this circuit is obvious resulting in

increase size of the adder. However, the structure is very regular, due to regular shapes of

both the CMOS transistor and the current comparator.

Introduction of CMMVL approach clearly reduces number of a data bus wiring

complexity. For example, 4-digit adder using SDDA cell requires 4 wires for the input

data bus and covers range of numbers from 0 to 9999. In the same time similar binary

adder would require input data bus 14 wires wide. By the experiments, it is verified that

the circuits operate satisfactorily with sufficient noise margins as far as the characteristic is

concerned. In the actual ULSI implementation, however, a more detailed investigation is

required on various aspects, such as the tolerance against supply voltage variation and the

tolerance in the device parameters in the fabrication.

By comparing the results of the two used technologies it can be seen that one of the

key factors for success of this type of analog design is maturity of used technology. Natu-

rally, more mature technology has less fluctuation in production resulting in higher unifor-

mity of the chips. Furthermore, for designs that operate "on the edge" it is very important

to have extremely accurate device models that show real device response at low voltages

and low currents.

Finally, it can be concluded that initial testing of CMMVL logic circuits prove fea-

sibility of the CMMVL concept. Future work will focus on CMMVL multipliers for DSP

applications.

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