csee 4823 advanced logic design handout: lecture #10 (part...

10
CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16 Prof. Steven M. Nowick [email protected] Department of Computer Science (and Elect. Eng.) Columbia University New York, NY, USA

Upload: others

Post on 11-Jun-2020

30 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)

10/6/16

Prof. Steven M. Nowick [email protected]

Department of Computer Science (and Elect. Eng.)

Columbia University New York, NY, USA

Page 2: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

Conditional Sum Adders

Page 3: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

#3

8-Bit Conditional Sum Adder: Level 1 Deriving Design for Bits 4-7 = typical case (i.e. not near right side)

FA

y4 x4

s40

0 c50

FA

y4 x4

s41

1 c51

FA

y5 x5

s50

0 c60

FA

y5 x5

s51

1 c61

FA

y6 x6

s60

0 c70

FA

y6 x6

s61

1 c71

FA

y7 x7

s70

0 c80

FA

y7 x7

s71

1 c81

Page 4: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

#4

8-Bit Conditional Sum Adder: Level 2 Deriving Design for Bits 4-7 = typical case (i.e. not near right side)

s50 s51

S51-new

c60 c61

c61-new

c51

Notation: shows two 2-to-1 MUXes with the same select signal (c51)

Page 5: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

#5

FA

y4 x4

s40

0 c50

FA

y4 x4

s41

1 c51

8-Bit Conditional Sum Adder: Levels 1 & 2 Deriving Design for Bits 4-7 = typical case (i.e. not near right side)

FA

y5 x5

s50

0 c60

FA

y5 x5

s51

1 c61

FA

y6 x6

s60

0 c70

FA

y6 x6

s61

1 c71

FA

y7 x7

s70

0 c80

FA

y7 x7

s71

1 c81

s50 s51

S51-new

c60 c61

c61-new

c51

s70 s71

S70-new

c80 c81

c80-new

c70 s70 s71

S71-new

c80 c81

c81-new

c71

s50 s51

S50-new

c60 c61

c60-new

c50

Page 6: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

#6

8-Bit Conditional Sum Adder: Levels 1 to 4 Deriving Design for Bits 4-7 = typical case (i.e. not near right side)

Levels 1 through 4 (complete): see Conditional Sum Adder handout

Page 7: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

#7

8-Bit Conditional Sum Adder: Level 1 Deriving Design for Bits 0-3 = special case (i.e. at right side)

FA

y0 x0

s0

CIN C1 FA

y1 x1

s10

0 c20

FA

y1 x1

s11

1 c21

FA

y2 x2

s20

0 c30

FA

y2 x2

s21

1 c31

FA

y3 x3

s30

0 c40

FA

y3 x3

s31

1 c41

Note: no speculation of two options in bit 0, since CIN is known.

Page 8: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

#8

8-Bit Conditional Sum Adder: Level 1 & 2 Deriving Design for Bits 0-3 = special case (i.e. at right side)

FA

y0 x0

s0

CIN C1 FA

y1 x1

s10

0 c20

FA

y1 x1

s11

1 c21

FA

y2 x2

s20

0 c30

FA

y2 x2

s21

1 c31

FA

y3 x3

s30

0 c40

FA

y3 x3

s31

1 c41

s30 s31

S30-new

c40 c41

c40-new

c30 s30 s31

S31-new

c40 c41

c41-new

c31

s10 s11

S10-new

c20 c21

c20-new

C1

Page 9: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

#9

8-Bit Conditional Sum Adder: Levels 1 to 3 Deriving Design for Bits 0-3 = special case (i.e. at right side)

Levels 1 through 3 (complete): see Conditional Sum Adder handout

Page 10: CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)cs4823/handouts/csee4823-l10-part2-slides.… · CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16

#10

8-Bit Conditional Sum Adder: Final Design

…see Conditional Sum Adder Handout for complete detailed design