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COURSE/SUBJECT FILE

For

DIGITAL LOGIC DESIGN

Course file contents

1. Cover Page

2. Syllabus copy

3. Vision of the Department

4. Mission of the Department

5. PEOs and POs

6. Course objectives and outcomes

7. Brief notes on the importance of the course and how it fits into the curriculum

8. Prerequisites if any

9. Instructional Learning Outcomes

10. Course mapping with POs

11. Class Time Table

12. Individual time Table

13. Lecture schedule with methodology being used/adopted

14. Detailed notes

15. Additional topics

16. University Question papers of previous years

17. Question Bank

18. Assignment Questions

19. Unit wise Quiz Questions and long answer questions

20. Tutorial problems

21. Known gaps ,if any and inclusion of the same in lecture schedule

22. Discussion topics , if any

23. References, Journals, websites and E-links if any

24. Quality Measurement Sheets

a. Course End Survey

b. Teaching Evaluation

25. Student List

26. Group-Wise students list for discussion topics

Course coordinator HOD

Geethanjali College of Engineering and Technology

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

(Name of the Subject/Lab Course): DIGITAL LOGIC DESIGN

(JNTU CODE: A30401) Programme: UG

Branch: CSE Version No: 1

Year: II A & B Document Number :GCET/CSE/

Semester: I No. of Pages:

Classification status (Unrestricted/Restricted ) : Unrestricted

Distribution List: Unrestricted

Prepared by :

1) Name : D.VENKATESWARLU

2) Sign :

3) Design : ASSOCIATE PROFESSOR

4) Date : 26-05-2016

1) Name : M. VIJAY BHASKER REDDY

2) Sign :

3) Design : ASSISTANT PROFESSOR

4) Date : 26-05-2016

Verified by : *For Q.C only

1) Name : 1)Name :

2) Sign : 2) Sign :

3) Design : 3) Design :

4) Date : 4) Date :

Approved by (HOD) :

1) Name :

2) Sign :

3) Date :

2. JNTU Syllabus

DIGITAL LOGIC DESIGN( II Year B.Tech. CSE-I Sem)

UNIT-I

Digital Systems: Binary Numbers, Octal, Hexa Decimal and other base numbers, Number base conversions, complements, signed binary numbers, Floating point number representation, binary codes, error detecting and correcting codes, digital logic gates(AND, NAND,OR,NOR, Ex-OR, Ex-NOR), Boolean algebra , basic theorems and properties, Boolean functions, canonical and standard forms.

UNIT-II

Gate –Level Minimization and combination circuits , The K-Maps Methods, Three Variable, Four Variable, Five Variable , sum of products , product of sums Simplification, Don’t care conditions , NAND and NOR implementation and other two level implantation.

UNIT-III

Combinational Circuits (CC): Design Procedure, Combinational circuit for different code converters and other problems, Binary Adder, sub-tractor, Multiplier, Magnitude Comparator, Decoders, Encoders, Multiplexers, De-multiplexers.

UNIT-IV

Synchronous Sequential Circuits: Latches, Flip-flops, analysis of clocked sequential circuits, design of counters, Up-down counters, Ripple counters , Registers, Shift registers, Synchronous Counters. Asynchronous Sequential Circuits: Reduction of state and follow tables, Role free Conditions.

UNIT-V:

Memory: Random Access memory, types of ROM, Memory decoding, address and data bus,

Sequential Memory, Cache Memory, Programmable Logic Arrays, memory Hierarchy in terms of capacity and access time.

.

3.Vision of the Department

To produce globally competent and socially responsible computer science engineers contributing to the advancement of engineering and technology which involves creativity and innovation by providing excellent learning environment with world class facilities.

4 Mission of the Department

1. To be a center of excellence in instruction, innovation in research and scholarship, and service to the stake holders, the profession, and the public.

2. To prepare graduates to enter a rapidly changing field as a competent computer science engineer.

3. To prepare graduate capable in all phases of software development, possess a firm understanding of hardware technologies, have the strong mathematical background necessary for scientific computing, and be sufficiently well versed in general theory to allow growth within the discipline as it advances.

4. To prepare graduates to assume leadership roles by possessing good communication skills, the ability to work effectively as team members, and an appreciation for their social and ethical responsibility in a global setting.

5.PROGRAM EDUCATIONAL OBJECTIVES (PEOs) OF C.S.E. DEPARTMENT

1. To provide graduates with a good foundation in mathematics, sciences and engineering fundamentals required to solve engineering problems that will facilitate them to find employment in industry and / or to pursue postgraduate studies with an appreciation for lifelong learning.

2. To provide graduates with analytical and problem solving skills to design algorithms, other hardware / software systems, and inculcate professional ethics, inter-personal skills to work in a multi-cultural team.

3. To facilitate graduates to get familiarized with the art software / hardware tools, imbibing creativity and innovation that would enable them to develop cutting-edge technologies of multi-disciplinary nature for societal development.

\

PROGRAM OUTCOMES (CSE)

Program Outcomes

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization to the solution of complex engineering problems.

2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences.

3. Design/development of solutions : Design solutions for complex engineering problems and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations.

4. Conduct investigations of complex problems: Use research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and modeling to complex engineering activities with an understanding of the limitations.

6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice.

7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice.

9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments.

12. Life-long learning : Recognize the need for, and have the preparation and ability to engage in independent and life-long learning in the broadest context of technological change.

6. Objectives and Out comes

Course Objectives:

1. To understand basic number systems codes and logical gates.

2. To understand the Boolean algebra and minimization logic.

3. To understand the design of combinational and sequential circuits to improve the efficiency of the hardware and software systems.

4. To understand the basics of various memory systems, memory internal organizations and representations

5. To understand Memory speed accessing mechanisms.

Outcomes:

C204.1:- After this course students could able to do with number systems and codes and their application to digital circuits.

C204.2:- Could able to do with fundamentals of Boolean algebra and theorems, K-maps including minimization of logic functions to SOP or POS forms.

C204.3:- Could able to do with mathematical characteristics of logical gates. and how to use truth tables, boolean algebra, K-maps, and other methods to obtain design equations.

C204.4:- Learn how to use design equations and procedures to design the combinational and sequential systems consisting of gates and flip-flops.

C204.5:- Could know the basic s of various memory techniques.

C204.6:- And they should be in a position to continue with computer organization.

7 Brief notes on the importance of the course and how it fits into the curriculum

· Students can do with number systems and codes and their application to digital circuits.

· To know the fundamentals of Boolean algebra and theorems, K-maps including minimization of logic functions to SOP or POS forms.

· Students can do with mathematical characteristics of logical gates.

· Learning how to use truth tables, Boolean algebra, K-maps, and other methods to obtain design equations.

· Learning how to use design equations and procedures to design the combinational and sequential systems consisting of gates and flip-flops.

· Combining combinational circuits and flip-flops to design combinational and sequential systems.

· Students can do with basic s of various memory.

Scope

· The purpose of this course is that we:

· Learn what’s under the hood of an electronic component

· Learn the principles of digital design

· Learn to systematically debug increasingly complex designs

· Design and build a digital system

8. Prerequisites

· Boolean minimization

· Combinational networks design.

· Sequential networks design.

· Karnaugh map.

9 . Instructional Learning Outcomes

· Students can do with number systems and codes and their application to digital circuits.

· To know the fundamentals of Boolean algebra and theorems, K-maps including minimization of logic functions to SOP or POS forms.

· Students can do with mathematical characteristics of logical gates.

· Learning how to use truth tables, Boolean algebra, K-maps, and other methods to obtain design equations.

· Learning how to use design equations and procedures to design the combinational and sequential systems consisting of gates and flip-flops.

· Combining combinational circuits and flip-flops to design combinational and sequential systems.

· Students can do with basic s of various memory.

Scope

· The purpose of this course is that we:

· Learn what’s under the hood of an electronic component

· Learn the principles of digital design

· Learn to systematically debug increasingly complex designs

· Design and build a digital system

10. DLD COURSE MAPPING WITH PEOs AND POs

Mapping of Course with Programme Educational Objectives

S.No

Course

code

Semester

PEO 1

PEO 2

PEO 3

1

DLD

I

√

√

-

Mapping of Course outcomes with Programme outcomes:

*When the course outcome weightage is < 40%, it will be given as moderately correlated (L).

*When the course outcome weightage is >40 &< 60%, it will be given as moderately correlated (M).

*When the course outcome weightage is >60%, it will be given as strongly correlated (H).

POs

1

2

3

4

5

6

7

8

9

10

11

12

DLD

CO 1:

H

H

H

-

-

-

-

-

M

M

M

M

CO 2:

H

H

H

M

M

L

-

-

M

M

M

M

CO 3:

H

H

H

M

M

L

-

-

M

M

M

M

CO 4:

H

H

H

-

-

-

-

-

M

M

M

M

CO 5:

H

H

H

L

L

-

-

M

M

M

M

CO 6:

H

H

H

H

H

H

L

L

M

M

H

H

11

Geethanjali College of Engineering & Technology

Department of Computer Science & Engineering

TIME TABLE - ODD SEMESTER

Year/Sem/Sec: II-B.Tech I-Semester A-Section A.Y : 2016 -17 WEF:13-06-2016(V0)

Class Teacher: M.VIJAYABHASKER REDDY

Time 09.30-10.20 10.20-11.10 11.10-12.00 12.00-12.50 12.50-1.30 1.30-2.20 2.20-3.10 3.10-4.00

Period

1 2 3 4

LUNCH

5 6 7

Monday

MFCS

DLD* BEE DS*

BEC

Tuesday

DS* DLD BEE EDC

PS FL

Wednesday

PS

A1: DS LAB/ A2: EE LAB

BEE BEE*

EDC

Thursday

MFCS

EDC DS

CRT

PS*

Friday

EDC DS PS DLD A1: EE LAB/ A2: DS LAB

Saturday

MFCS* DLD DS DLD EDC PS BEE

S.No Subject(T/P) Faculty Name Contact No

1

PROBABILITY AND STATISTICS(PS) K.NAGARAJU/N.NAGIREDDY*

2

MATHEMATICAL FOUNDATIONS OF COMPUTER SCIENCE(MFCS)

DR.S.NAGENDERKUMAR/ CH. LATHA*

3

DIGITAL LOGIC DESIGN(DLD) M.VIJAY BHASKER REDDY/D.VENKATESWARLU*

4

ELECTRONIC DEVICES AND CIRCUITS(EDC) M.LAXMI

5

BASIC ELECTRICAL ENGINEERING(BEE) K.MAHINDER/AZRA ZAINEB*

6

DATA STRUCTURES(DS)

C.Y.RAO/C ESTHER VERMA*

7

ELECTRICAL AND ELECTRONICS LAB(EE LAB)

8

DATA STRUCTURES LAB (DS LAB)-LAB 6

C.Y.RAO/M.VIJAY BHASKER REDDY/G.JANARDHAN

9 FOREIGN LANGUAGES (FL)

10 BUSINESS ENGLISH CERTIFICATE COURCE (BEC)

11

CRT FACULTY I/C:M.VIJAY BHASKER REDDY

12 *-Tutorial Hour/Discussion Hour

TT. Coord:_____________ HOD:__________________ Dean Academics:-_______________ Principal:_________________

Room No : LH-121

EDC: J.BHARATHI ,B.RAMESH

BEE:K.MAHINDER, N.SANTHINATH, B.RAMESHBABU




Year/Sem/Sec: II-B.Tech I-Semester B-Section A.Y : 2016 -17 WEF:13-06-2016(V0)

Class Teacher: C.Y.RAO

Time 09.30-10.20 10.20-11.10 11.10-12.00 12.00-12.50 12.50-1.30 1.30-2.20 2.20-3.10 3.10-4.00

Period

1 2 3 4

LUNCH

5 6 7

Monday

DS B1: DS LAB/ B2: EE LAB MFCS

BEC

Tuesday

BEE B1: EE LAB/ B2: DS LAB PS

FL

Wednesday

DLD

EDC MFCS

CRT

DS*

Thursday

EDC DS PS MFCS

BEE

EDC

Friday

DLD

BEE DS

PS

EDC MFCS*

Saturday

DLD* BEE* PS EDC DS PS* MFCS


1

PROBABILITY AND STATISTICS(PS) Dr.V.S. TRINENI/N.SUBHADRA*

2

MATHEMATICAL FOUNDATIONS OF COMPUTER SCIENCE(MFCS) B.MAMATHA/CH. LATHA*

3

DIGITAL LOGIC DESIGN(DLD) DR.S.UDAY KUMAR/M.VIJAY BHASKER REDDY*

4

ELECTRONIC DEVICES AND CIRCUITS(EDC) Y.NAGALAXMI

5

BASIC ELECTRICAL ENGINEERING(BEE) K.MAHINDER/AZRA ZAINEB*

6

DATA STRUCTURES(DS)

C.Y.RAO/C ESTHER VERMA*

7


EDC: BEE: B.RAMESHBABU/ SOUMIDATTA/ V. RAKESH

8

DATA STRUCTURES LAB (DS LAB)-LAB 6

C.Y.RAO/B MAMATHA/G.JANARDHAN



11

CRT FACULTY I/C: C.Y.RAO



Room No: LH-126




Year/Sem/Sec: II-B.Tech I-Semester C-Section A.Y : 2016 -17 WEF:13-06-2016(V0)

Class Teacher: D.VENKATESWARLU

Time 09.30-10.20 10.20-11.10 11.10-12.00 12.00-12.50 12.50-1.30 1.30-2.20 2.20-3.10 3.10-4.00

Period

1 2 3 4

LUNCH

5 6 7

Monday

CRT

DS DLD* EDC BEE* PS*

Tuesday

MFCS PS BEE EDC C1: DS LAB / C2: EE LAB

Wednesday

EDC

BEE MFCS DLD DS*

BEC

Thursday

PS DLD

DS MFCS* BEE

Friday

DS C1: EE LAB / C2: DS LAB MFCS

FL

Saturday

EDC DLD BEE DS MFCS PS EDC


1

PROBABILITY AND STATISTICS(PS)

N.NAGI REDDY/K.NAGARAJU*

2


CH.LATHA/B.MAMATHA*

3

DIGITAL LOGIC DESIGN(DLD) D.VENKATESWARLU/M.VIJAY BHASKER REDDY*

4

ELECTRONIC DEVICES AND CIRCUITS(EDC) J.BHARATHI

5

BASIC ELECTRICAL ENGINEERING(BEE) AZRA ZAINEB/K.MAHINDER*

6

DATA STRUCTURES(DS) ESTHER VARMA/ D.VENKATESWARLU*

7


8

DATA STRUCTURES LAB (DS LAB)-LAB 6 C.ESTHER VARMA/D.VENKATESWARLU/G.JANARDHAN



11

CRT FACULTY I/C: CH.LATHA



Room No : LH-127

EDC:J.BHARATHI, B.RAMESH

BEE: AZRA ZAINEB//SOUMIDATTA/K.MAHINDER




Year/Sem/Sec: II-B.Tech I-Semester D-Section A.Y : 2016 -17 WEF:13-06-2016(V0)

Class Teacher:C.ESTHER VARMA

Time 09.30-10.20 10.20-11.10 11.10-12.00 12.00-12.50 12.50-1.30 1.30-2.20 2.20-3.10 3.10-4.00

Period

1 2 3 4

LUNCH

5 6 7

Monday

DS DLD* PS BEE D1:DS LAB /D2: EE LAB

Tuesday

BEE DLD CRT PS MFCS EDC

Wednesday

DLD

DS BEE MECS*

BEC

Thursday

MFCS D1:EE LAB /D2: DS LAB EDC PS* DS*

Friday

EDC MFCS PS BEE DS

FL

Saturday

PS DS EDC DLD BEE* EDC MFCS


1

PROBABILITY AND STATISTICS(PS)

N.SUBHADRA/Dr.V.S. TRINENI*

2


CH.LATHA/B.MAMATHA*

3

DIGITAL LOGIC DESIGN(DLD) D.VENKATESWARLU/M.VIJAY BHASKER REDDY*

4

ELECTRONIC DEVICES AND CIRCUITS(EDC) V.SIDDARTHA

5

BASIC ELECTRICAL ENGINEERING(BEE) AZRA ZAINEB/K.MAHINDER

6

DATA STRUCTURES(DS) ESTHER VARMA/C.Y.RAO*

7


8

DATA STRUCTURES LAB (DS LAB)-LAB 6 C.ESTHER VARMA/ /CH.LATHA/A.YADAGIRI



11

CRT FACULTY I/C: ESTHER VARMA



Room No : LH-128

EDC:Y.NAGALAXMI, B.RAMESH

BEE: V.PADMAJA /

12

Faculty Name:Dr.S.Uday Kumar Sub/Lab: DLD II CSE-B I Sem A.Y:2016-17 I semester

Time 09.30-10.20 10.20-11.10 11.10-12.00 12.00-12.50 12.50-1.30 1.30-2.20 2.20-3.10 3.10-4.00

Period

1 2 3 4

LUNCH

5 6 7

Monday

Tuesday

Wednesday

B

Thursday

Friday

B

Saturday

B*

Faculty Name:D.VENKATESWARLU Sub/Lab: DLD / DS LAB ( C & D) II CSE I Sem A.Y:2016-17 I semester

Time 09.30-10.20 10.20-11.10 11.10-12.00 12.00-12.50 12.50-1.30 1.30-2.20 2.20-3.10 3.10-4.00

Period

1 2 3 4

LUNCH

5 6 7

Monday

D* A* C*

Tuesday

D C-DS LAB B1

Wednesday

D C C*(DS)

Thursday

C

Friday

C-DS LAB B2

Saturday

C D

Faculty Name:M. Vijay Bhasker Reddy Sub/Lab: DLD / DS LAB ( A &B) II CSE I Sem A.Y:2016-17 I semester

Time 09.30-10.20 10.20-11.10 11.10-12.00 12.00-12.50 12.50-1.30 1.30-2.20 2.20-3.10 3.10-4.00

Period

1 2 3 4

LUNCH

5 6 7

Monday

D* A* C*

Tuesday

A

Wednesday

A-DS LAB B1

Thursday

Campus CRT-II A

Friday

A A-DS LAB B2

Saturday

B* A A

13. Lecture schedule with methodology being used/adopted

MICRO PLAN:

SL.

No

Unit No

Topic to be covered in One lecture

Reg/ Additional

Teaching aids used LCD/OHP/BB

1

1

Digital Systems, Binary Numbers

Regular

BB

2

Number base conversions, Octal

and Hexadecimal Numbers and

Regular

BB

Other base conversions

3

Complements, Signed binary numbers

Regular

BB

4

Floating point representations

Regular

BB

Binary codes

Assignment test on unit-1

Error detecting and correcting

5

Binary Storage and Registers, Binary logic

Regular

BB

6

Conversion from gray code to other codes

Additional

BB

7

Tutorial class on unit-1

Digital Logic Gates(AND,NAND,OR,Ex-OR,Ex-NOR ect.,)

8

Boolean Algebra and– Basic Definitions, Axiomatic definition of Boolean Algebra

Regular

BB

9

Basic theorems and properties of Boolean algebra

Regular

BB

10

Boolean functions

Regular

BB

canonical and standard forms

13


14


15

2

Gate level minimization – The map method

Regular

BB

16

three-Variable ,Four-variable and Five-Variable maps.

Regular

BB

17


18

Six-variable map

Additional

BB

19

Product of sums simplification

Regular

BB

20

Sum of product simplification, Don’t-care conditions

Regular

BB

21

NAND and NOR implementation

Regular

BB

22


23

other Two-level implementations: AND–OR–INVERT Implementation, and

Regular

BB

24

OR-AND-INVERT Implementation.

Regular

BB

25


26

3

Combinational Circuits, Analysis procedure Design procedure

Regular

BB

27

Combinational circuits for different code conversion(BCD to excess-3 code)

Regular

BB

28

Multiplier

Regular

BB

29

Binary Adder- Subtractor(half, full & binary adder)

Regular

BB

30

Decimal Adder(BCD Adder)

Regular

BB

31

Binary multiplier, Magnitude comparator

Regular

BB

32

Decoders

Regular

BB

33

Encoders

Regular

BB

34

Multiplexers and De-Multiplexers

Regular

BB

35


36


37

38

4

Sequential circuits: ;

Regular

BB

39

latches(storage elements):SR and D-Latches

Regular

BB

40

Flip-Flops: Edge Trigger D-flip flop

Regular

BB

41

SR,JK,D and T-Flip-Flops

Regular

BB

42


43

Analysis of clocked sequential circuits

Regular

BB

44

Design of counter: Ripple counter :

Regular

BB

45

Binary ripple counter, BCD Ripple counter and

Regular

BB

46

Synchronous circuits :binary counter and

Regular

BB

47

Up-Down binary counter

Regular

BB

48

Asynchronous sequential circuits

Regular

BB

49

Other counter : Ring and Johnson counters

Additional

BB

50

Registers: Register with parallel load,

Regular

BB

51

Shift registers: serial transfer and serial adder and

Regular

BB

52

Universal shift register

Regular

BB

53

Reduction of state and follow table

Regular

BB

54

Role free conditions

Regular

BB

55


56

57

5

Introduction to memory systems. Random-Access Memory

Regular

BB

58

Types of memories : RAM and ROM. Types of ROMs

Regular

BB

59

Address and data bus

Regular

BB

60

Memory Decoding

Regular

BB

61

Programmable logic Array, and

Regular

BB

62

programmable Array logic

Regular

BB

64

Hierarchy of memory in terms of capacity and access time

Regular

BB

65


Lecture Schedule with expected dates

II Year B.Tech. CSE-I Sem A-Section Faculty: M Vijay Bhasker Reddy w.e.f: 13/06/2016

SL.

No

Unit No


Expected dates


1

1


13/06/2016

BB

2



14/06/2016

BB

3


14/06/2016

4


17/06/2016

BB

5

Tutorial

18/06/2016

6


20/06/2016

7

Binary codes

21/06/2016

8


21/06/2016

9


24/06/2016

BB

10


25/06/2016

BB

11


27/06/2016

12


28/06/2016

13


28/06/2016

BB

14

Tutorial

01/07/2016

15


02/07/2016

BB

16

Boolean functions

04/07/2016

BB

17


05/07/2016

18


05/07/2016

19

2


11/07/2016

BB

20


12/07/2016

BB

21


12/07/2016

22

Six-variable map

15/07/2016

BB

23

Tutorial

16/07/2016

24


18/07/2016

BB

25


19/07/2016

BB

26


19/07/2016

BB

27


22/07/2016

BB

28


23/07/2016

BB

29


23/07/2016

30

3


26/07/2016

BB

31


26/07/2016

BB

32

Multiplier

29/07/2016

BB

33


30/07/2016

BB

34

Tutorial

01/08/2016

35


02/08/2016

BB

36


02/08/2016

BB

37

Decoders

05/08/2016

BB

38

Encoders

06/08/2016

BB

39

Tutorial

16/08/2016

40


16/08/2016

BB

41


19/08/2016

42

4


22/08/2016

BB

43


23/08/2016

BB

44


23/08/2016

BB

45


26/08/2016

BB

46

Tutorial

27/08/2016

47


29/08/2016

BB

48


30/08/2016

BB

49


30/08/2016

BB

50

Tutorial

02/09/2016

51


03/09/2016

BB

52


06/09/2016

BB

53


06/09/2016

BB

54


09/09/2016

BB

55


10/09/2016

BB

56


13/09/2016

BB

57


13/09/2016

BB

58

Tutorial

16/09/2016

59


17/09/2016

BB

60


19/09/2016

BB

20/09/2016

61

5


23/09/2016

BB

62


24/09/2016

63


26/09/2016

BB

64

Memory Decoding

27/09/2016

BB

65


30/09/2016

BB

66


01/10/2016

BB

67


04/10/2016

BB


II Year B.Tech. CSE-I Sem B-Section

Faculty: Dr. S Udaya Kumarw.e.f: 13/06/2016

SL.

No

Unit No


Expected dates


1

1


15/06/2016

BB

2



15/06/2016

BB

3


17/06/2016

4


17/06/2016

BB

5

Tutorial

18/06/2016

6


22/06/2016

7

Binary codes

22/06/2016

8


24/06/2016

9


24/06/2016

BB

10


25/06/2016

BB

11


29/06/2016

12


29/06/2016

13


01/07/2016

BB

14

Tutorial

01/07/2016

15


02/07/2016

BB

16

Boolean functions

06/07/2016

BB

17


06/07/2016

18


09/07/2016

19

2


13/07/2016

BB

20


13/07/2016

BB

21


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II Year B.Tech. CSE-I Sem C-Section

w.e.f: 13/06/2016

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w.e.f: 13/06/2016

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14. Detailed notes

Unit-I

BINARY SYSTEMS

Philosophy of Number Systems

Numbering System:

Many number systems are in use in digital technology. The most common are the decimal, binary, octal, and hexadecimal systems. The decimal system is clearly the most familiar to us because it is a tool that we use every day. Examining some of its characteristics will help us to better understand the other systems. In the next few pages we shall introduce four numerical representation systems that are used in the digital system. There are other systems, which we will look at briefly.

· Decimal

· Binary

· Octal

· Hexadecimal

Decimal System:

The decimal system is composed of 10 numerals or symbols. These 10 symbols are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. Using these symbols as digits of a number, we can express any quantity. The decimal system is also called the base-10 system because it has 10 digits.

103

102

101

100

10-1

10-2

10-3

=1000

=100

=10

=1

.

=0.1

=0.01

=0.001

Most Significant Digit

Decimal point

Least Significant Digit

Even though the decimal system has only 10 symbols, any number of any magnitude can be expressed by using our system of positional weighting.

Decimal Examples

1) 3.1410

2) 5210

3) 102410

4) 6400010

Binary System

In the binary system, there are only two symbols or possible digit values, 0 and 1. This base-2 system can be used to represent any quantity that can be represented in decimal or other base system.

23

22

21

20

2-1

2-2

2-3

=8

=4

=2

=1

.

=0.5

=0.25

=0.125


Binary point


Binary Counting

The Binary counting sequence is shown in the table:

23

22

21

20

Decimal

0

0

0

0

0

0

0

0

1

1

0

0

1

0

2

0

0

1

1

3

0

1

0

0

4

0

1

0

1

5

0

1

1

0

6

0

1

1

1

7

1

0

0

0

8

1

0

0

1

9

1

0

1

0

10

1

0

1

1

11

1

1

0

0

12

1

1

0

1

13

1

1

1

0

14

1

1

1

1

15

In additional to binary and decimal, two other number systems find wide-spread applications in digital systems. The octal (base-8) and hexadecimal (base-16) number systems are both used for the same purpose- to provide an efficient means for representing large binary system.

Octal System

The octal number system has a base of eight, meaning that it has eight possible digits: 0,1,2,3,4,5,6,7.

83

82

81

80

8-1

8-2

8-3

=512

=64

=8

=1

.

=1/8

=1/64

=1/512


Octal point


Octal to Decimal Conversion

(A) 2378 = 2 x (82) + 3 x (81) + 7 x (80) = 15910

(B) 24.68 = 2 x (81) + 4 x (80) + 6 x (8-1) = 20.7510

(C) 11.18 = 1 x (81) + 1 x (80) + 1 x (8-1) = 9.12510

(D) 12.38 = 1 x (81) + 2 x (80) + 3 x (8-1) = 10.37510

Hexadecimal System

The hexadecimal system uses base 16. Thus, it has 16 possible digit symbols. It uses the digits 0 through 9 plus the letters A, B, C, D, E, and F as the 16 digit symbols.

163

162

161

160

16-1

16-2

16-3

=4096

=256

=16

=1

.

=1/16

=1/256

=1/4096


Hexa Decimal point


Hexadecimal to Decimal Conversion

4. 24.616 = 2 x (161) + 4 x (160) + 6 x (16-1) = 36.37510

5. 11.116 = 1 x (161) + 1 x (160) + 1 x (16-1) = 17.062510

6. 12.316 = 1 x (161) + 2 x (160) + 3 x (16-1) = 18.187510

Code Conversion

Converting from one code form to another code form is called code conversion, like converting from binary to decimal or converting from hexadecimal to decimal.

Binary-To-Decimal Conversion

Any binary number can be converted to its decimal equivalent simply by summing together the weights of the various positions in the binary number which contain a 1.

Binary

Decimal

110112

24+23+01+21+20

=16+8+0+2+1

Result

2710

and

Binary

Decimal

101101012

27+06+25+24+03+22+01+20

=128+0+32+16+0+4+0+1

Result

18110

You should have noticed that the method is to find the weights (i.e., powers of 2) for each bit position that contains a 1, and then to add them up.

Decimal-To-Binary Conversion

There are 2 methods:

6. Reverse of Binary-To-Decimal Method

7. Repeat Division

Reverse of Binary-To-Decimal Method

Decimal

Binary

4510

=32 + 0 + 8 + 4 +0 + 1

=25+0+23+22+0+20

Result

=1011012

Repeat Division-Convert decimal to binary

This method uses repeated division by 2.

Convert 2510 to binary

Division

Remainder

Binary

25/2

= 12+ remainder of 1

1 (Least Significant Bit)

12/2

= 6 + remainder of 0

0

6/2


0

3/2


1

1/2


1 (Most Significant Bit)

Result

2510

= 110012

The Flow chart for repeated-division method is as follows:

Binary-To-Octal / Octal-To-Binary Conversion

Octal Digit

0

1

2

3

4

5

6

7

Binary Equivalent

000

001

010

011

100

101

110

111

Each Octal digit is represented by three binary digits.

Example:

100 111 0102 = (100) (111) (010)2 = 4 7 28

Repeat Division-Convert decimal to octal


Example: Convert 17710 to octal and binary

Division

Result

Binary

177/8


1 (Least Significant Bit)

22/ 8


6

2 / 8



Result

17710

= 2618

Binary

= 0101100012

Hexadecimal to Decimal/Decimal to Hexadecimal Conversion

Example:

2AF16 = 2 x (162) + 10 x (161) + 15 x (160) = 68710

Repeat Division- Convert decimal to hexadecimal


Example: convert 37810 to hexadecimal and binary:

Division

Result

Hexadecimal

378/16


A (Least Significant Bit)23

23/16


7

1/16



Result

37810

= 17A16

Binary

= 0001 0111 10102

Binary-To-Hexadecimal /Hexadecimal-To-Binary Conversion

Hexadecimal Digit

0

1

2

3

4

5

6

7

Binary Equivalent

0000

0001

0010

0011

0100

0101

0110

0111

Hexadecimal Digit

8

9

A

B

C

D

E

F

Binary Equivalent

1000

1001

1010

1011

1100

1101

1110

1111

Each Hexadecimal digit is represented by four bits of binary digit.

Example:

1011 0010 11112 = (1011) (0010) (1111)2 = B 2 F16

Octal-To-Hexadecimal Hexadecimal-To-Octal Conversion

1) Convert Octal (Hexadecimal) to Binary first.

2) Regroup the binary number by three bits per group starting from LSB if Octal is required.

3) Regroup the binary number by four bits per group starting from LSB if Hexadecimal is required.

4) Example:

Convert 5A816 to Octal.

Hexadecimal

Binary/Octal

5A816

= 0101 1010 1000 (Binary)

= 010 110 101 000 (Binary)

Result

= 2 6 5 0 (Octal)

Complement representation of negative numbers

Signed-Magnitude representation:

This is the simplest method.

Write the magnitude of the number in binary. Then add a 1 to the front of it if the number is negative and a 0 if it is positive.

Examples: +7 would be 111 and then a 0 in front so 00000111 for an 8-bit representation.

-9 would be 1001 (+9) and then a 1 so 10001001 for an 8-bit representation.

It is not the best method or representation because it makes computation awkward.

2’s complement representation:

Most widely used method of representation.

Positive numbers are represented as they are (simple binary).

To get a negative number, write the positive number in binary, then change all 0’s to 1’s and 1’s to 0’s. Then add 1 to the number.

Example : +7 would be 0111 in 4-bit 2’s complement.

To represent –5 we take +5 (0101) and then invert the digits (1010) and add 1

(1011). –5 is thus 1011.

Suppose you already have a number that is in two’s complement representation and want to find its value in binary.

If the number starts with a 1 it is a negative number. If it starts with a 0 it is a positive number.

If it is a negative number, take the 2’s complement of that number. You will get the number in ordinary binary. The sign you already know. Let’s take 1101.

Take the 2’s complement and you get 0011. Since it started with a 1, it was

negative and the value is 0011 which is 3. The number represented by 1101 is –3

in 2’s complement.

Lets see how this system is better:

If we add +5 and -5 in decimal we get 0.

Let’s add them in 4-bit signed-magnitude. +5 is 0101 and –5 is 1101. On adding we get

10010. That is not zero.

Let’s do the same thing in 2’s complement. Adding 0101 (+5) and 1011 (-5) gives

10000. If we discard the carry of 1 we get 0000 – i.e. 0.

Thus addition works out ok for negative numbers in 2’s complement whereas it doesn’t in

sign magnitude.

Similarly, you can show that multiplication and subtraction all work in 2’s complement

but do not in other representations. The other number systems require much more

complicated hardware to implement basic mathematical functions. i.e.

add/subtract/multiply.

Sign-and-magnitude

8 bit signed magnitude

Binary

Signed

Unsigned

00000000

+0

0

00000001

1

1

...

...

...

01111111

127

127

10000000

−0

128

10000001

−1

129

...

...

...

11111111

−127

255

One may first approach the problem of representing a number's sign by allocating one sign bit to represent the sign: set that bit (often the most significant bit) to 0 for a positive number, and set to 1 for a negative number. The remaining bits in the number indicate the magnitude (or absolute value). Hence in a byte with only 7 bits (apart from the sign bit), the magnitude can range from 0000000 (0) to 1111111 (127). Thus you can represent numbers from −12710 to +12710 once you add the sign bit (the eighth bit). A consequence of this representation is that there are two ways to represent zero, 00000000 (0) and 10000000 (−0). Decimal −43 encoded in an eight-bit byte this way is 10101011.

This approach is directly comparable to the common way of showing a sign (placing a "+" or "−" next to the number's magnitude). Some early binary computers (e.g. IBM 7090) used this representation, perhaps because of its natural relation to common usage. Sign-and-magnitude is the most common way of representing the significand in floating point values.

Ones' complement

8 bit ones' complement

Binary value

Ones' complement interpretation

Unsigned interpretation

00000000

+0

0

00000001

1

1

...

...

...

01111101

125

125

01111110

126

126

01111111

127

127

10000000

−127

128

10000001

−126

129

10000010

−125

130

...

...

...

11111110

−1

254

11111111

−0

255

Alternatively, a system known as ones' complement can be used to represent negative numbers. The ones' complement form of a negative binary number is the bitwise NOT applied to it — the complement of its positive counterpart. Like sign-and-magnitude representation, ones' complement has two representations of 0: 00000000 (+0) and 11111111 (−0).

As an example, the ones' complement form of 00101011 (43) becomes 11010100 (−43). The range of signed numbers using ones' complement is represented by −(2N−1−1) to (2N−1−1) and +/−0. A conventional eight-bit byte is −12710 to +12710 with zero being either 00000000 (+0) or 11111111 (−0).

To add two numbers represented in this system, one does a conventional binary addition, but it is then necessary to add any resulting carry back into the resulting sum. To see why this is necessary, consider the following example showing the case of the addition of −1 (11111110) to +2 (00000010).

'''binary decimal'''

11111110 -1

+ 00000010 +2

............ ...

1 00000000 0 <-- not the correct answer

1 +1 <-- add carry

............ ...

00000001 1 <-- correct answer

In the previous example, the binary addition alone gives 00000000, which is incorrect. Only when the carry is added back in does the correct result (00000001) appear.

This numeric representation system was common in older computers; the PDP-1, CDC 160A and UNIVAC 1100/2200 series, among many others, used ones'-complement arithmetic.

A remark on orthography: The system is referred to as "ones' complement" because the negation of a positive value x (represented as the bitwise NOT of x) can also be formed by subtracting x from the ones' complement representation of zero that is a long sequence of ones (-0). Two's complement arithmetic, on the other hand, forms the negation of x by subtracting x from a single large power of two that is congruent to +0.[1] Therefore, ones' complement and two's complement representations of the same negative value will differ by one.

The Internet protocols IPv4, ICMP, UDP and TCP all use the same 16-bit ones' complement checksum algorithm. Although most computers lack "end-around carry" hardware, the extra complexity is accepted because "it is equally sensitive to errors in all bit positions".[2] In UDP, the all 0s representation of zero indicates that the optional checksum feature has been omitted. The other representation, FFFF, indicates a checksum value of 0.[3] (Checksums are mandatory in IPv4, TCP and ICMP; they were omitted from IPv6).

Note that the ones' complement representation of a negative number can be obtained from the sign-magnitude representation merely by bitwise complementing the magnitude.

Binary Arithmetic:

Binary addition

Adding binary numbers is a very simple task, and very similar to the longhand addition of decimal numbers. As with decimal numbers, you start by adding the bits (digits) one column, or place weight, at a time, from right to left. Unlike decimal addition, there is little to memorize in the way of rules for the addition of binary bits:

0 + 0 = 0

1 + 0 = 1

0 + 1 = 1

1 + 1 = 10

1 + 1 + 1 = 11

Just as with decimal addition, when the sum in one column is a two-bit (two-digit) number, the least significant figure is written as part of the total sum and the most significant figure is "carried" to the next left column. Consider the following examples:

. 11 1 <--- Carry bits -----> 11

. 1001101 1001001 1000111

. + 0010010 + 0011001 + 0010110

. --------- --------- ---------

. 1011111 1100010 1011101

The addition problem on the left did not require any bits to be carried, since the sum of bits in each column was either 1 or 0, not 10 or 11. In the other two problems, there definitely were bits to be carried, but the process of addition is still quite simple.

As we'll see later, there are ways that electronic circuits can be built to perform this very task of addition, by representing each bit of each binary number as a voltage signal (either "high," for a 1; or "low" for a 0). This is the very foundation of all the arithmetic which modern digital computers perform.

Negative binary numbers

With addition being easily accomplished, we can perform the operation of subtraction with the same technique simply by making one of the numbers negative. For example, the subtraction problem of 7 - 5 is essentially the same as the addition problem 7 + (-5). Since we already know how to represent positive numbers in binary, all we need to know now is how to represent their negative counterparts and we'll be able to subtract.

Usually we represent a negative decimal number by placing a minus sign directly to the left of the most significant digit, just as in the example above, with -5. However, the whole purpose of using binary notation is for constructing on/off circuits that can represent bit values in terms of voltage (2 alternative values: either "high" or "low"). In this context, we don't have the luxury of a third symbol such as a "minus" sign, since these circuits can only be on or off (two possible states). One solution is to reserve a bit (circuit) that does nothing but represent the mathematical sign:

. 1012 = 510 (positive)

.

. Extra bit, representing sign (0=positive, 1=negative)

. |

. 01012 = 510 (positive)

.

. Extra bit, representing sign (0=positive, 1=negative)

. |

. 11012 = -510 (negative)

As you can see, we have to be careful when we start using bits for any purpose other than standard place-weighted values. Otherwise, 11012 could be misinterpreted as the number thirteen when in fact we mean to represent negative five. To keep things straight here, we must first decide how many bits are going to be needed to represent the largest numbers we'll be dealing with, and then be sure not to exceed that bit field length in our arithmetic operations. For the above example, I've limited myself to the representation of numbers from negative seven (11112) to positive seven (01112), and no more, by making the fourth bit the "sign" bit. Only by first establishing these limits can I avoid confusion of a negative number with a larger, positive number.

Representing negative five as 11012 is an example of the sign-magnitude system of negative binary numeration. By using the leftmost bit as a sign indicator and not a place-weighted value, I am sacrificing the "pure" form of binary notation for something that gives me a practical advantage: the representation of negative numbers. The leftmost bit is read as the sign, either positive or negative, and the remaining bits are interpreted according to the standard binary notation: left to right, place weights in multiples of two.

As simple as the sign-magnitude approach is, it is not very practical for arithmetic purposes. For instance, how do I add a negative five (11012) to any other number, using the standard technique for binary addition? I'd have to invent a new way of doing addition in order for it to work, and if I do that, I might as well just do the job with longhand subtraction; there's no arithmetical advantage to using negative numbers to perform subtraction through addition if we have to do it with sign-magnitude numeration, and that was our goal!

There's another method for representing negative numbers which works with our familiar technique of longhand addition, and also happens to make more sense from a place-weighted numeration point of view, called complementation. With this strategy, we assign the leftmost bit to serve a special purpose, just as we did with the sign-magnitude approach, defining our number limits just as before. However, this time, the leftmost bit is more than just a sign bit; rather, it possesses a negative place-weight value. For example, a value of negative five would be represented as such:

Extra bit, place weight = negative eight

. |

. 10112 = 510 (negative)

.

. (1 x -810) + (0 x 410) + (1 x 210) + (1 x 110) = -510

With the right three bits being able to represent a magnitude from zero through seven, and the leftmost bit representing either zero or negative eight, we can successfully represent any integer number from negative seven (10012 = -810 + 110 = -710) to positive seven (01112 = 010 + 710 = 710).

Representing positive numbers in this scheme (with the fourth bit designated as the negative weight) is no different from that of ordinary binary notation. However, representing negative numbers is not quite as straightforward:

zero 0000

positive one 0001 negative one 1111

positive two 0010 negative two 1110

positive three 0011 negative three 1101

positive four 0100 negative four 1100

positive five 0101 negative five 1011

positive six 0110 negative six 1010

positive seven 0111 negative seven 1001

. negative eight 1000

Note that the negative binary numbers in the right column, being the sum of the right three bits' total plus the negative eight of the leftmost bit, don't "count" in the same progression as the positive binary numbers in the left column. Rather, the right three bits have to be set at the proper value to equal the desired (negative) total when summed with the negative eight place value of the leftmost bit.

Those right three bits are referred to as the two's complement of the corresponding positive number. Consider the following comparison:

positive number two's complement

--------------- ----------------

001 111

010 110

011 101

100 100

101 011

110 010

111 001

In this case, with the negative weight bit being the fourth bit (place value of negative eight), the two's complement for any positive number will be whatever value is needed to add to negative eight to make that positive value's negative equivalent. Thankfully, there's an easy way to figure out the two's complement for any binary number: simply invert all the bits of that number, changing all 1's to 0's and vice versa (to arrive at what is called the one's complement) and then add one! For example, to obtain the two's complement of five (1012), we would first invert all the bits to obtain 0102 (the "one's complement"), then add one to obtain 0112, or -510 in three-bit, two's complement form.

Interestingly enough, generating the two's complement of a binary number works the same if you manipulate all the bits, including the leftmost (sign) bit at the same time as the magnitude bits. Let's try this with the former example, converting a positive five to a negative five, but performing the complementation process on all four bits. We must be sure to include the 0 (positive) sign bit on the original number, five (01012). First, inverting all bits to obtain the one's complement: 10102. Then, adding one, we obtain the final answer: 10112, or -510 expressed in four-bit, two's complement form.

It is critically important to remember that the place of the negative-weight bit must be already determined before any two's complement conversions can be done. If our binary numeration field were such that the eighth bit was designated as the negative-weight bit (100000002), we'd have to determine the two's complement based on all seven of the other bits. Here, the two's complement of five (00001012) would be 11110112. A positive five in this system would be represented as 000001012, and a negative five as 111110112.

Binary Subtraction

We can subtract one binary number from another by using the standard techniques adapted for decimal numbers (subtraction of each bit pair, right to left, "borrowing" as needed from bits to the left). However, if we can leverage the already familiar (and easier) technique of binary addition to subtract, that would be better. As we just learned, we can represent negative binary numbers by using the "two's complement" method and a negative place-weight bit. Here, we'll use those negative binary numbers to subtract through addition. Here's a sample problem:

Subtraction: 710 - 510 Addition equivalent: 710 + (-510)

If all we need to do is represent seven and negative five in binary (two's complemented) form, all we need is three bits plus the negative-weight bit:

positive seven = 01112

negative five = 10112

Now, let's add them together:

. 1111 <--- Carry bits

. 0111

. + 1011

. ------

. 10010

. |

. Discard extra bit

.

. Answer = 00102

Since we've already defined our number bit field as three bits plus the negative-weight bit, the fifth bit in the answer (1) will be discarded to give us a result of 00102, or positive two, which is the correct answer.

Another way to understand why we discard that extra bit is to remember that the leftmost bit of the lower number possesses a negative weight, in this case equal to negative eight. When we add these two binary numbers together, what we're actually doing with the MSBs is subtracting the lower number's MSB from the upper number's MSB. In subtraction, one never "carries" a digit or bit on to the next left place-weight.

Let's try another example, this time with larger numbers. If we want to add -2510 to 1810, we must first decide how large our binary bit field must be. To represent the largest (absolute value) number in our problem, which is twenty-five, we need at least five bits, plus a sixth bit for the negative-weight bit. Let's start by representing positive twenty-five, then finding the two's complement and putting it all together into one numeration:

+2510 = 0110012 (showing all six bits)

One's complement of 110012 = 1001102

One's complement + 1 = two's complement = 1001112

-2510 = 1001112

Essentially, we're representing negative twenty-five by using the negative-weight (sixth) bit with a value of negative thirty-two, plus positive seven (binary 1112).

Now, let's represent positive eighteen in binary form, showing all six bits:

. 1810 = 0100102

.

. Now, let's add them together and see what we get:

.

. 11 <--- Carry bits

. 100111

. + 010010

. --------

. 111001

Since there were no "extra" bits on the left, there are no bits to discard. The leftmost bit on the answer is a 1, which means that the answer is negative, in two's complement form, as it should be. Converting the answer to decimal form by summing all the bits times their respective weight values, we get:

(1 x -3210) + (1 x 1610) + (1 x 810) + (1 x 110) = -710

Indeed -710 is the proper sum of -2510 and 1810.

Binary Codes

Binary codes are codes which are represented in binary system with modification from the original ones. Below we will be seeing the following:

· Weighted Binary Systems

· Non Weighted Codes

Weighted Binary Systems

Weighted binary codes are those which obey the positional weighting principles, each position of the number represents a specific weight. The binary counting sequence is an example.

8421 Code/BCD Code

The BCD (Binary Coded Decimal) is a traight assignment of the binary equivalent. It is possible to assign weights to the binary bits according to their positions. The weights in the BCD code are 8,4,2,1.

Example: The bit assignment 1001, can be seen by its weights to represent the decimal 9 because:

1x8+0x4+0x2+1x1 = 92421 Code

This is a weighted code, its weights are 2, 4, 2 and 1. A decimal number is represented in 4-bit form and the total four bits weight is 2 + 4 + 2 + 1 = 9. Hence the 2421 code represents the decimal numbers from 0 to 9.

5211 Code

This is a weighted code, its weights are 5, 2, 1 and 1. A decimal number is represented in 4-bit form and the total four bits weight is 5 + 2 + 1 + 1 = 9. Hence the 5211 code represents the decimal numbers from 0 to 9.

Reflective Code

A code is said to be reflective when code for 9 is complement for the code for 0, and so is for 8 and 1 codes, 7 and 2, 6 and 3, 5 and 4. Codes 2421, 5211, and excess-3 are reflective, whereas the 8421 code is not.

Sequential Codes

A code is said to be sequential when two subsequent codes, seen as numbers in binary representation, differ by one. This greatly aids mathematical manipulation of data. The 8421 and Excess-3 codes are sequential, whereas the 2421 and 5211 codes are not.

Non Weighted Codes

Non weighted codes are codes that are not positionally weighted. That is, each position within the binary number is not assigned a fixed value.

Excess-3 Code

Excess-3 is a non weighted code used to express decimal numbers. The code derives its name from the fact that each binary code is the corresponding 8421 code plus 0011(3).

Example: 1000 of 8421 = 1011 in Excess-3

Gray Code

The gray code belongs to a class of codes called minimum change codes, in which only one bit in the code changes when moving from one code to the next. The Gray code is non-weighted code, as the position of bit does not contain any weight. The gray code is a reflective digital code which has the special property that any two subsequent numbers codes differ by only one bit. This is also called a unit-distance code. In digital Gray code has got a special place.

Decimal Number

Binary Code

Gray Code

0

0000

0000

1

0001

0001

2

0010

0011

3

0011

0010

4

0100

0110

5

0101

0111

6

0110

0101

7

0111

0100

8

1000

1100

9

1001

1101

10

1010

1111

11

1011

1110

12

1100

1010

13

1101

1011

14

1110

1001

15

1111

1000

Binary to Gray Conversion

•Gray Code MSB is binary code MSB.

•Gray Code MSB-1 is the XOR of binary code MSB and MSB-1.

•MSB-2 bit of gray code is XOR of MSB-1 and MSB-2 bit of binary code.

•MSB-N bit of gray code is XOR of MSB-N-1 and MSB-N bit of binary code.

Function Definitions

The logic operations given previously are defined as follows :

Define f(X,Y) to be some function of the variables X and Y.

f(X,Y) = X.Y

•1 if X = 1 and Y = 1

•0 Otherwise

f(X,Y) = X + Y

•1 if X = 1 or Y = 1

•0 Otherwise

f(X) = X'

•1 if X = 0

•0 Otherwise

Truth Tables

Truth tables are a means of representing the results of a logic function using a table. They are constructed by defining all possible combinations of the inputs to a function, and then calculating the output for each combination in turn. For the three functions we have just defined, the truth tables are as follows.

AND

X

Y

F(X,Y)

0

0

0

0

1

0

1

0

0

1

1

1

OR

X

Y

F(X,Y)

0

0

0

0

1

1

1

0

1

1

1

1

NOT

X

F(X)

0

1

1

0

Truth tables may contain as many input variables as desired.

F(X,Y,Z) = X.Y + Z

X

Y

Z

F(X,Y,Z)

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

1

1

0

0

0

1

0

1

1

1

1

0

1

1

1

1

1

Boolean Switching Algebras

A Boolean Switching Algebra is one which deals only with two-valued variables. Boole's general theory covers algebras which deal with variables which can hold n values.

Axioms

Consider a set S = { 0. 1}

Consider two binary operations, + and . , and one unary operation, -- , that act on these elements. [S, ., +, --, 0, 1] is called a switching algebra that satisfies the following axioms S

Closure

If X S and Y S then X.Y S

If X S and Y S then X+Y S

Identity

an identity 0 for + such that X + 0 = X

an identity 1 for . such that X . 1 = X

Commutative Laws

X + Y = Y + X

X . Y = Y . X

Distributive Laws

X.(Y + Z ) = X.Y + X.Z

X + Y.Z = (X + Y) . (X + Z)

Complement

X S a complement X'such that

X + X' = 1

X . X' = 0

The complement X' is unique.

Theorems

A number of theorems may be proved for switching algebras

Idempotent Law

X + X = X

X . X = X

DeMorgan's Law

(X + Y)' = X' . Y', These can be proved by the use of truth tables.

Proof of (X + Y)' = X' . Y'

X

Y

X+Y

(X+Y)'

0

0

0

1

0

1

1

0

1

0

1

0

1

1

1

0

X

Y

X'

Y'

X'.Y'

0

0

1

1

1

0

1

1

0

0

1

0

0

1

0

1

1

0

0

0

The two truth tables are identical, and so the two expressions are identical.

(X.Y) = X' + Y', These can be proved by the use of truth tables.

Proof of (X.Y) = X' + Y'

X

Y

X.Y

(X.Y)'

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

X

Y

X'

Y'

X'+Y'

0

0

1

1

1

0

1

1

0

1

1

0

0

1

1

1

1

0

0

0

Note : DeMorgans Laws are applicable for any number of variables.

Boundedness Law

X + 1 = 1

X . 0 = 0

Absorption Law

X + (X . Y) = X

X . (X + Y ) = X

Elimination Law

X + (X' . Y) = X + Y

X.(X' + Y) = X.Y

Unique Complement theorem

If X + Y = 1 and X.Y = 0 then X = Y'

Involution theorem

X'' = X

0' = 1

Associative Properties

X + (Y + Z) = (X + Y) + Z

X . ( Y . Z ) = ( X . Y ) . Z

Duality Principle

In Boolean algebras the duality Principle can be is obtained by interchanging AND and OR operators and replacing 0's by 1's and 1's by 0's. Compare the identities on the left side with the identities on the right.

Example

X.Y+Z' = (X'+Y').Z

Consensus theorem

X.Y + X'.Z + Y.Z = X.Y + X'.Z

or dual form as below

(X + Y).(X' + Z).(Y + Z) = (X + Y).(X' + Z)

Proof of X.Y + X'.Z + Y.Z = X.Y + X'.Z:

X.Y + X'.Z + Y.Z

= X.Y + X'.Z

X.Y + X'.Z + (X+X').Y.Z

= X.Y + X'.Z

X.Y.(1+Z) + X'.Z.(1+Y)

= X.Y + X'.Z

X.Y + X'.Z

= X.Y + X'.Z

(X.Y'+Z).(X+Y).Z = X.Z+Y.Z instead of X.Z+Y'.Z

X.Y'Z+X.Z+Y.Z

(X.Y'+X+Y).Z

(X+Y).Z

X.Z+Y.Z

The term which is left out is called the consensus term.

Given a pair of terms for which a variable appears in one term, and its complement in the other, then the consensus term is formed by ANDing the original terms together, leaving out the selected variable and its complement.

Example :

The consensus of X.Y and X'.Z is Y.Z

The consensus of X.Y.Z and Y'.Z'.W' is (X.Z).(Z.W')

Shannon Expansion Theorem

The Shannon Expansion Theorem is used to expand a Boolean logic function (F) in terms of (or with respect to) a Boolean variable (X), as in the following forms.

F = X . F (X = 1) + X' . F (X = 0)

where F (X = 1) represents the function F evaluated with X set equal to 1; F (X = 0) represents the function F evaluated with X set equal to 0.

Also the following function F can be expanded with respect to X,

F = X' . Y + X . Y . Z' + X' . Y' . Z

= X . (Y . Z') + X' . (Y + Y' . Z)

Thus, the function F can be split into two smaller functions.

F (X = '1') = Y . Z'

This is known as the cofactor of F with respect to X in the previous logic equation. The cofactor of F with respect to X may also be represented as F X (the cofactor of F with respect to X' is F X' ). Using the Shannon Expansion Theorem, a Boolean function may be expanded with respect to any of its variables. For example, if we expand F with respect to Y instead of X,

F = X' . Y + X . Y . Z' + X' . Y' . Z

= Y . (X' + X . Z') + Y' . (X' . Z)

A function may be expanded as many times as the number of variables it contains until the canonical form is reached. The canonical form is a unique representation for any Boolean function that uses only minterms. A minterm is a product term that contains all the variables of F¿such as X . Y' . Z).

Any Boolean function can be implemented using multiplexer blocks by representing it as a series of terms derived using the Shannon Expansion Theorem.

Summary of Laws And Theorms

Identity

Dual

Operations with 0 and 1

X + 0 = X (identity)

X.1 = X

X + 1 = 1 (null element)

X.0 = 0

Idempotency theorem

X + X = X

X.X = X

Complementarity

X + X' = 1

X.X' = 0

Involution theorem

(X')' = X

Cummutative law

X + Y = Y + X

X.Y = Y X

Associative law

(X + Y) + Z = X + (Y + Z) = X + Y + Z

(XY)Z = X(YZ) = XYZ

Distributive law

X(Y + Z) = XY + XZ

X + (YZ) = (X + Y)(X + Z)

DeMorgan's theorem

(X + Y + Z + ...)' = X'Y'Z'... or { f ( X1,X2,...,Xn,0,1,+,. ) } = { f ( X1',X2',...,Xn',1,0,.,+ ) }

(XYZ...)' = X' + Y' + Z' + ...

Simplification theorems

XY + XY' = X (uniting)

(X + Y)(X + Y') = X

X + XY = X (absorption)

X(X + Y) = X

(X + Y')Y = XY (adsorption)

XY' + Y = X + Y

Consensus theorem

XY + X'Z + YZ = XY + X'Z

(X + Y)(X' + Z)(Y + Z) = (X + Y)(X' + Z)

Duality

(X + Y + Z + ...)D = XYZ... or {f(X1,X2,...,Xn,0,1,+,.)}D = f(X1,X2,...,Xn,1,0,.,+)

(XYZ ...)D = X + Y + Z + ...

Shannon Expansion Theorem

f(X1,...,Xk,...Xn)

Xk * f(X1,..., 1 ,...Xn) + Xk' * f(X1,..., 0 ,...Xn)

f(X1,...,Xk,...Xn)

[Xk + f(X1,..., 0 ,...Xn)] * [Xk' + f(X1,..., 1 ,...Xn)]

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