cscdfdfe611 lecture week01

7/28/2019 CSCdfdfE611 Lecture Week01

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2005/3/27

Supplemental Lecture Notes Week 1

The Digital Systems Design Process

2002 Dr. James P. Davis

CSCE 611CSCE 611

Digital Systems Design IDigital Systems Design I

Page 2 2002 Dr. James P. Davis

CSCE 611 LectureCSCE 611 Lecture -- Week 1Week 1

z Introduction9 Drivers for VLSI Systems-On-a-Chip (SOC)

9 Example: Wireless Communications

9 The Widening Productivity Gap: Capacity vs. Capability

z Research Background

9 VLSI-based Design Space (Y-chart)

9 Abstraction Levels and Representation Domains

9 Detailed R&D Example: the Hydra Experience

Design Methodology

FPGA Design Example

Successes & Limitations

z Extrapolation9 The VLSI Architecture Continuum

9 The CSCE 790 Design Process

9 Possible Directions for Research


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IntroductionIntroduction -- The New RealitiesThe New Realities

Telecomm ComputersConsumerElectronics

"chip"

VLSI

Silicon

"At the root of cascading changes of modern economic life...devaluing

the constraints of material resources, the microchip has devalued most

resources in technology, business and geopolitics...overcoming the

large accumulations of physical capital and made possible the launchin

of global economic enterprises...microchips find their value not in theirsubstance but in their intellectual content: their design..."

George Gilder, Microcosm, 1989


IntroductionIntroduction -- VLSI SOCVLSI SOC DriversDrivers

z Many market and technology factors coming together to createpressure on electronics product engineering organizationsworldwide.

9 Increasing global competition and new markets.

9 Increasing rate of product innovations and new product introductions.

9 Decreasing time-to-market windows.

9 Decreasing shelf life for products in many categories.

9 Increasing pressure on competitive cost containment, profit margins.

9 Increasing convergence: integrated functionality in single electronicsdevices and product packages.

9 Increasing quality expectations: means for containing distribution andsupport costs.

9 Increasing innovation in silicon process technology and wafer scaleintegration densities.

9 Increasing disparity: capacity of the underlying technologies versus

capability of designers to manage increasing design complexity.


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IEEE802.11aIEEE802.11a

G2/G3G2/G3

NetworkNetwork

CDMACDMA

ExampleExample Wireless CommunicationsWireless Communications

z The market is seeking producttechnology options to coverdifferent geography ranges anddata rates.9 Bluetooth WPAN.WPAN.

9 IEEE 802.11 - WLAN.WLAN.

9 2/3G Network WWAN.WWAN.

z The opportunity for creatingvalue chains encompassingproduct offerings, distributionand new service offeringshinges on the ability to get lowcost solutions to marketquickly.9 Deliver content to wireless

handheld devices.

9 Function convergence in thehandset and at the base station.

9 Requires large cross-functionaldesign teams in varied disciplines.

Blue ToothBlue Tooth

802.11b802.11b

Range

Data Rate

WWANWWAN

WLANWLANWPANWPAN

Source: Knowledge Edge KK


ExampleExample 802.11a Wireless Communications802.11a Wireless Communications

Convolution

Encoder

Inter-

leaver

Serial/

Parallel

Wave

Shaping

Wave

Shaping

D/A

D/A

I

QMapping

Data

from

MAC

Viterbi

Decoder

Deinter-

leaver

64-pt

FFT

Remove

Cyclic

Prefix

Parallel

/Serial

Receive

Filter

Receive

Filter

A/D

A/D

I

Q

Demap

p-ing

Data

to

MAC

Channel

Estimation

Frequency

Equaliztion

Timing

Synchronize

AGC

Transceiver ControllerTx/Rx Datapath Controller

Control

from

MAC

Rx Block

Tx Block

Control Block

0.5~1k

gates

Dual port

SRAM ROM block

40k~100k

gates

1~2mm2

30k~60k

gates

1~1.5mm2

Small RAM block

and control

logic

40~80k gates,

1~ 1.5mm2

+(200k gates)30~60Kbit momory

unknown

depends on thealgorithm

Cyclic

Prefix

64-pt

IFFT

Source: Knowledge Edge KK


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24

9

3

Months

1985 1990 1995 2000

10,000K

1,000K

100K

DesignSize

Product Time-to-Market

Device Capacity

Design Capability

The Capacity vs. Capability GapThe Capacity vs. Capability Gap

z Increasing capacity of thetechnology:9 The rate of new technology

and associated siliconprocess changes hascontinued to follow MooresLaw.

z The capability of designersand design teams to usethis capacity isnt keepingup.9 The Capacity versus

Capability Gap is widening.

9 Each set of technology andprocess changes requiresdesigners to manage evermore complexity in the designprocess.

9 New architectures,abstractions, methods andtools are required to addressthis increasing complexity.

Source: Dataquest


IntroductionIntroduction VLSI SOC ObjectivesVLSI SOC Objectives

z The objectives of SOC approaches are to better manage designcomplexity.9 Using betterdesign planningin trade-off analysis and decision-making

greater availability of downstream design constraints earlier in theprocess.

back annotating early iteration data into high-level design activities.

9

Using electronic systems design best practices Increased levels of design reuse. More effective hardware-software co-design.

Better trade-offs between general-purpose vs. domain-specificarchitectures and algorithms.

Greater integration of functionality on-chip (hardware-software, analog-digital).

z SOC Architecture Imperatives9 Reusability/Extensibility faster creation of primary and derivative products.

9 Reliability managing device technology constraints as geometry shrinks.

9 Scalability bigger and bigger design densities and integration levels.

9 Performance data throughput, system capacity.

9 Resource Utilization function, area, power, clocking, interconnect.


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VLSIVLSI--based Design Space (Ybased Design Space (Y--chart)chart)


Behavior to Architecture MappingBehavior to Architecture Mapping


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Levels of Abstraction in VLSI System DesignLevels of Abstraction in VLSI System Design

z A design transforms from"concept" to "implementation" ina series of ordered levels.

z From the highest level to lower

levels of design "abstraction", adesign is iteratively refined.

z The design description is verifiedand validated at each level,often cycling between levels ofabstraction.

z Design descriptions are

described using one or moredomain representations(Behavior, Structure, Physical).

Architectural Algorithm

Behavioral

Functional/RTL

Structural

Geometrical

block diagram

flowchart

state equationsstate diagramflowdiagram

RTL notationdatapath diagramtruth table

schematic diagramnetlist

layout

mask

queueing network

petri net


Design as a ProblemDesign as a Problem--solving Processsolving Process

9 Many possible solutions,some better than others.

9 Search through "solutionspace".

9 Trade-offs and constraintchecks at each node.

9 At dead-end node,"backtrack" and tryanother path.

9 Backtracking is costly

and time consuming.

Application

Requirements

Specification High-level Designand Verification

Layout,

Routing

Field Test

Productionand

Logic

Timing

Design,

Analysis

z The "search" for an optimal solution involves tools & methods.


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Impact of Backtracking on the Design ProcessImpact of Backtracking on the Design ProcessApplication

Requirements

High-levelDesign and

Verification

Gate-level

Analysis and

Verification

Function

and Timing

Specification

Analysis and

Physical

Verification

Text documentation

HDL Coding or Text documentation

Logic Synthesis or Schematic Capture

Layout and Routing

Area or TimingConstraint

Violation

Behavioral orFunctionalConstraint

Violation

ViolationRequirements

Area or TimingConstraint

Violation

Support easy exploration ofdesign alternatives.

Allow function & behaviorchanges to be made quickly.

Eliminate unnecessary"cycling" through design steps.

Improve the turnaround time

per cycle.

Behavioral or functionalconstraint violationscause 50-80% of cyclingbetween design steps.

ApproachGoalProblem


DesignDesign--forfor--Synthesis Methods & ToolsSynthesis Methods & Tools

NO YES

NO

YES

FunctionalSimulation

HDL SimulationRequired?

CorrectFunction?

CaptureDesign

Compile &Checking

NO YES

NO YES

CorrectEntry?

NO

YES

BehavioralSimulation

Cycle-basedSimulation?

CorrectBehavior?

NO YES

NO YES

Done

LogicSynthesis

Gate-levelTiming

Analysis

CorrectTiming?

Area &Speed?

Partition,Place &Route

FabricateDevice

Start

Synopsys VSSTM

HDL CompilerTM

FPGA CompilerTM

DesignWareTM

Synopsys Design CompilerTM

Design Analyzer

Synopsys SGETM

Timing AnalyzerTM

Design Approach - "stepwise refinement", with

"iterative enhancement".

Create design "skeleton", with core functions and

cycle-level timing information specified.

Iterate the design through synthesis, checking key

area and timing constraints.

Return to the top of the process to make corrections, and

to enhance the design description.

Integrate completed behavioral block with other blocksfor HDL "system" simulation.

KBS flowHDL

blockHDL

TM

TM


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Domains and AbstractionsDomains and Abstractions

Handshaking, Pipelining applications

In peripherals, data communications

Domains.


Partitioning of Control & Data PathPartitioning of Control & Data Path

Control Unit

steering

logic

registerclocked

logic

registerclocked

Data Path Unit

Data inData out

Control in

SelectStatus

Control out

combin.

State

Registers

input/next statedecoding logic CLK

inputs

present state information

next stateinformation

output decodinglogic

control outputs

^RES

MUX

Defines both synchronous and asynchronoustransformations of data moving through theblock.

Defines clock-based sequencing ofactions in data path or external to theblock.

Modeled using RTL model.Modeled using FSM model.

Data Path UnitControl Unit


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RTL Schematic NotationRTL Schematic Notation

Higher-level

Block

Block name

Block type

block name

Bounding Box

(Encapsulates block's internal structure and interconnect)

UART

block_1

Architectural - LocalInput portInput pin

Output pin(appears as Output port

Bi-directional pin(appears as Bi-directional port

Internal output/Buffer pin(appears as Buffer port

Functional

at higher level)

at higher level)

at higher level)


ASM Control Sequencing and SchedulingASM Control Sequencing and Scheduling

s0

s1

s3

s5

input1 & input2

10

^RES

CLK1 (rising)

signal1

Areg


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ASM Scalable MacroASM Scalable Macro--function Libraryfunction Library

z RTL macro-functions: contain over 30 primitive data path elements in a library.

z Macros are "scalable" - with any number of buses and any bus widths.

z Macros can be used to construct more complex user-defined data path

functions.9 Macro-function definition: AnyXN(A_bus,B_bus) ::= BOR(AND(B_bus,NOT(DECO(A_bus))))9 Macro-function binding: CollisionEvent


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ExampleExample XMIT/RCV Block DiagramXMIT/RCV Block Diagram

ExampleExample -- XMIT/RCV ASM ThreadsXMIT/RCV ASM ThreadszzThread for SIA Baud Clock GeneratorThread for SIA Baud Clock Generator

zzThread for SIAThread for SIAControlControlsequencersequencer

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