csa complete

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CSA

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Instruction Code

The organization of a computer is defined by itsinternal registers, the timing and controlstructure, and the set of instructions that ituses.

The internal organization of a digital system isdefined by the sequence of micro-operations itperforms on data stored in its registers.

The general purpose digital computer is capableof executing various micro-operations and it canbe instructed as to what specific instructions it

must perform.2/13/2012 2Er. KAPIL PRASHAR


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Continued

y The user of a computer can control the process bymeans of a program.

y A program is a set of instructions that specify theoperations, operands, and the sequence by which

processing has to occur.y An instruction is a binary code that specifies a

sequence of micro-operations.

y Instructions and data are stored in memory.

y The ability of store and execute instructions, thestored program concept (von Neumann architecture),is the most important property of a general-purposecomputer.



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Continued

An instruction code is a group of bits that instructthe computer to perform a specific operation (set ofmicrooperations).

Operation code is a basic part of instruction code; agroup of bits that define such operations as add,subtract, multiply, shift, and complement.

The operation code must consist of at least n bits

for a given 2n

(or less) distinct operations. Control unit receives the instruction from memory

and interprets the operation code bits. It thenissues a sequence of control signals to initiate MOs

in internal registers.2/13/2012 4Er. KAPIL PRASHAR


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Continued

For every operation code, the control issues asequence of MOs, needed for h/w implementation

ofv that operation.

An operation code is called macro-operation because

it specifies a set of micro-operations. An instruction code specify also the registers or the

memory words for operands and results Memory words can be specified by their address

Registers can be specified by a binary code ofkbitsspecifying one of 2kpossible registers.

Each computer (CPU) has its own instruction codeformat.



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Continued

A simple computer organization One register

An instruction code format with two parts Operation code

An address: tells the control where to find an operand from memory. Thedata processed with data in register.

Fig. next Control reads 16-bit instruction fromprogram memory. It uses the 12-bit address part ofinstruction to read 16-bit operand from data memory.It then executes the operation specified by the

operation code. If an operation does not need an operand from

memory, the address bits can be used for otherpurposes, e.g. clear AC, complement AC ( no need of

address).2/13/2012 6Er. KAPIL PRASHAR


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Stored Program Organization



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Continued

When the second part of an instruction codespecifies an operand(not address), the instructionis said to have an immediate operand.

When the second part specifies an address of anoperand, the instruction is said to have a directaddress.

Indirect address: the second part specifies amemory location where the address of theoperand is found.

Indirect address increases addressable memorysize

=> more bits for specifying addresses of operands.2/13/2012 8Er. KAPIL PRASHAR


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Indirect address

mode bit

Effective address



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Computer Registers

Instructions are stored in consecutive memorylocations and are executed sequentially one at atime.

The control reads an instruction from a specificaddress in memory and executes it: after that nextinstruction is read and executed, and so on.

Registers are needed for storing fetchedinstructions, and counters for computing theaddress of the next instruction.



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Continued

Computer needs processor registers for data

manipulation and holding addresses (see.Next Fig. and Table).

Program counter (PC) goes through acounting sequence and causes the computer

to read sequential instructions from memory. Instructions are read and executed in

sequence unless a branch instruction isencountered

Calls for a transfer to a nonconsecutive instruction in theprogram

The address part of a branch instruction becomes the address ofthe next instruction in PC

Next instruction is read from the location indicated by PC



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Continued

The basic computer has (seeF

ig. In previous slide): 8 registers 1 memory unit

1 control unit

Common bus

The outputs of 7 registers and memory areconnected to the common bus.

Connections to bus lines are specified by selectionlines S0, S1, and S2.

A register load during the next clock pulse transitionis selected with a LD (load) input.

Memory write/read is enabled with write/readsignals.



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Figure : Basic Computer registers connected to a common bus2/13/2012 14Er. KAPIL PRASHAR


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Continued INPRreceives a character from an input device.

OUTRreceives a character from ACand delivers it to anoutput device.

Bus receives data from 6 registers and the memory unit.

5 registers have three control lines: LD (load), INR(increment), and CLR (clear): equivalent to a binarycounter with parallel load and synchronous clear. 2registers have only a LD input.

AR is used to specify memory address: no need for anaddress bus.

16 inputs to AC

come from an adder and logic circuitwith three sets of inputs: ACoutput, DR, INPR.



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Continuedy Content of any register can be applied onto the bus, and

an operation can be performed in the adder and logiccircuit during the same clock cycle. The clock transition atthe end of the cycle transfers the content of the bus intothe designated register and the output of the adder and

logic circuit into AC, e.g.:

DR ACand AC DR

ACto the bus (S2S1S0 = 100), enabling the LD ofDR,transferring DRinto AC(through adder and logic unit),

and enabling LD ofAC, all during the same clock cycle.The two transfers occur upon the arrival of the clockpulse transition at the end of the clock cycle.



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Computer Instructions

yThe basic computer has three 16-bit instruction code

formats (see. Next Fig.).

y Opcode contains 3 bits and the meaning of the remaining13 bits depends on the operation code encountered.

y A memory-reference instruction uses 12 bits to specify

address and one bit to specify addressing mode I.y The register-reference instructions are recognized by

opcode 111 with 0 in bit 15.

y A Register-register instruction specifies an operation onor test of the ACregister. An operand is not needed: 12bits are used for specifying the operation or test to beexecuted.



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Continuedy Input-output instruction is recognized by the opcode 111

with 1 in bit 15. Remaining 12 bits are used to specify thetype of input-output operation or test performed.

y Bits 12-15 are used to recognize the type of instruction.

y

IfBits 12-14 are not 111 the instruction is a memoryreference type: I(bit 15) is taken as the addressing mode.

y If bits 12-14 are 111, bit 15 is inspected for the type ofinstruction: 0 for register-reference and 1 for input-output instruction.

y 25 instructions (see. Next Table).



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Instruction Set completeness

y Sufficient set of instructions for computingany function known to be computable.

Three categories of instructions:1. Arithmetic, logical, and shift instructions

2. Instructions for moving information to andfrom memory and processor registers

3. Program control instructions together withinstructions that check status conditions

4. Input and output instructions



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Continued

Arithmetic, logical, and shift instructions providecomputational capabilities for processing data.

All computation are done in processor registers: instructionsfor moving information between memory and registers areneeded.

Status checking (e.g. comparing magnitudes of two numbers)and program control instructions (e.g.branch) for altering theprogram flow.

Input and output instructions for human-computer

interaction: programs must be transferred into memory andthe results of computations must be transferred to the user.

Instructions in Table 5-2 constitute a minimum set.



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Continued

y Addition and subtraction: ADD, CMA, INC.y Shifts: CIR, CILy Multiplication and division: addition, subtraction,

and shift.

y Logic: AND, CMA, CLA => NAND => all logicoperations with two variables.

y Moving information: LDA, STA.y Branching and status checking: BUN, BSA, ISZ, and

skip operations.

y Input-output: INP, OUT



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Continued

The instruction set of the basic computer iscomplete, but not efficient.

An efficient set of instructions includesseparate instructions for frequently usedoperations in order to perform them fast.Examples: OR, exclusive-OR, subtract, multiply,

divide. These operation must be programmedin the basic computer.



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Timing and Control

Timing for all registers is controlled by amaster clock generator.

Clock is applied to all flip-flops andregisters in the system.

Clock pulses do not change the state of a

register unless it is enabled by a controlsignal generated in the control unit.



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Continued There are two major types of control organization: hardwire

control and microprogrammed control Hardwire organization (see next Fig.): the control logic is implemented

with gates, flip-flops, decoders, and other digital circuits

Can be optimized to produce fast mode of operation

Requires changes in the wiring if the design has to be modified

Microprogrammed organization: the controlinformation is stored in a control memory (store)

The control memory is programmed to initiate the requiredsequence of micro-operations

Any required modifications can be done by updating the

microprogram in control memory.

A microprogram is a program consisting of microcode that controls the different parts of a

computer's central processing unit (CPU). The memory in which it resides is called a controlstore.



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Continued Block diagram of the (hardwire) control unit is shown in next

Figure. (control logic derived later)

IRcontains an instruction read from memory three parts: I-bit, opcode, bits 0-11 Opcode is decoded with a 3 x 8 decoder (outputs D0-D7)

Iis transferred to a flip-flop

4-bit sequence counter (SC) provide the sequence of 16 timingsignals

synchronous clear and increment When required, SC can be cleared (CLR signal enabled) by a suitable

control logic, e.g. (see Fig.):

D3T4: SC 0

Control outputs are a function of all incoming signals to thecontrol logic gates. SCenables sequential control outputs.



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Continued

Memory read/write are initiated by a rising clock edge.

It is assumed that memory access is completed in one

clock cycle assumption is often not valid in real computers because the

memory cycle is usually longer that the clock cycle => wait cycles(states) must be provided until the memory word is available.

No wait cycles in basic computer introduced here.

Next rising edge will load the memory word into a

register.



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Continued

It is important to understand the timing relationshipbetween clock transition and the timing signals.

For example, the register transfer statement:

T0: AR PC

specifies a transfer of the content PCinto ARif the timingsignal T

0is active. T

0is active an entire clock cycle. During

this time interval the content ofPC is placed onto the busand LD input of AR is enabled. The actual transfer occursat the end of the clock cycle when the clock goes through

a positive transition (latches inputs to flip-flops). Thissame transition increments SC: the next clock cycle hasT1

active and T0

inactive.



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Instruction Cycle

A program consists of a sequence of instruction, and itresides in the memory.

Each instruction cycle in basic computer has following

phases:1. Fetch an instruction from memory

2. Decode the instruction

3. Read the effective address from memory if instruction defines anindirect address

4. Execute the instruction

After phase 4, the control jumps back to phase 1. This

process continues until HALT instruction is encountered.



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Fetch and Decode

Initially program counter PCin loaded with the address

of the first instruction in the program.

SCis cleared (i.e. timing signal T0 is active). SCisincremented after each clock pulse.

Fetch and decode phases can be specified by following

register transfer statements:



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Continued

during T0:1. Place the content ofPC onto bus (S2S1S0 = 010 => 2)

2. Transfer the content of the bus to AR (enable LD input of AR)

The next clock transition initiates transfer from PC to AR

during T1

:

1. Enable the read input of memory

2. Place the content of memory onto the bus (S2S1S0 = 111 => 7)

3. Transfer the content of bus to IR (enable LD input of IR)

4. Increment PC (enable INR input ofPC)

The next clock transition initiates the read and increment

operations



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Continued

During T2:

1. Opcode is decoded by the 3 x 8 decoder

2. IR(0-11) is transferred to AR (address register)

3. IR(15) is latched to flip-flop I

2 and 3 occur at the end of the clock cycle



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Determine the Type of Instruction

Timing signal is T3 (after decoding) During T3, the control unit determines thetype instruction that was just read frommemory (see Fig.).

After the instruction has been executed SC is

cleared and control returns to fetch phasewith T0 = 1. It is assumed (not explicitly shown in transfer

statements) that SC is incremented with everypositive clock transition.

When SC is cleared, SC. 0 statement isincluded.



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Register-Reference Instruction Recognized by the control when D7 = 1 and I= 0.

Uses bits 0-11 of the instruction code to specify one of 12instructions.

The 12 bits are available in IR(0-11) and they weretransferred to ARduring time T2.

See Table for control functions and microoperations for theregister-reference instructions.

Each control function share Boolean relation D7IT3 (denoted by r)

The particular control function is indicated by one of the bits in IR(0-11)

The execution of a register-reference instruction is completed at timeT3:the sequence counter is cleared to 0 and control goes back to fetch the

next instruction with timing signal T1.



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Memory-Reference Instructions

Table lists the seven memory-referenceinstructions: the execution of each

instruction requires a sequence of

microoperations because data is stored inmemory and cannot be processed directly.

The effective address resides in AR and

was placed there during timing signal T2

when I= 0, and T3 when I= 1 (see Fig.).



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Continued

AND to AC: pair wise AND to bits in AC and

the memory word specified by the effective

addressD0T4: DR M[AR]

D0T5: AC AC AND DR, SC 0

Output of the operation decoder = 0



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Continued

ADD to AC: adds the content of the

memory word specified by the effective

address to the value of ACD1T4: DR M[AR]

D1T5: AC AC + DR, E Cout , SC 0

Output of the operation decoder = 1 Extended Accumulator



45/196

Continued

LDA: Load a memory word from a specified

effective address to AC

D2T4: DR M[AR]

D2T5: AC DR, SC 0

See Fig on slide 26: no direct path from the bus to AC:

memory word is first read into DR whose content is then

transferred into AC.



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Continued

STA: store the content of AC into the

memory word specified by the effective

addressD3T4: M[AR] AC , SC 0



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Continued

BUN: Branch unconditionally transfers the program tothe instruction specified by the effective address. The next

instruction is fetched and executed from the memory

address given by the new value in PC

D4T4:PC

AR , SC

0 BSA: Branch and save return address this instruction is

useful for branching to a portion of a program called a

subroutine or procedure

M[AR] PC, PC AR + 1

address of the next address of the 1st

instruction in sequence instruction in the

(return address) subroutine



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BSA instruction The BSA instruction performs the function

usually referred to as a subroutine call.

The indirect BUN instruction at the end ofthe subroutine performs the functionreferred as a subroutine return.

In most commercial computers, the returnaddress associated with the subroutine isstored in either a processor register of in aportion of memory called a stack.A stack is a data structure that works on the principle of

Last In First Out (LIFO). This means that the last item puton the stack is the first item that can be taken off, like aphysical stack of plates. A stack-based computer system isone that is based on the use of stacks, rather than beingregister based.



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Continued

The BSA instruction must be executedwith a sequence of two microoperations:

D5T4: M[AR] PC, AR AR + 1

D5T5: PC AR, SC 0

Timing signalT

4 initiates a memory writeoperation, places the content ofPContothe bus, and enables the INR input ofAR.

Memory write operation is completed and ARisincremented by the time the next clock transition occurs.

The bus is used at T5 to transfer the content or ARto PC.



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ISZ instruction

ISZ: Increment the word specified by the effective address, and ifincremented value is equal to 0, PC is incremented by 1

D6T4: DR M[AR]

D6T5: DR DR + 1

D6T6: M[AR] DR, if (DR = 0) then

(PC

PC

+1), SC

0

Programmer usually stores a negative number (in 2s

complement) in the memory word. Repeated increments willeventually clear the memory word to 0. At that time PC isincremented by one in order to skip the next instruction in the

program => can be used to create loops .



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Continued

Flow chart showing microoperations for the

seven memory-reference instructions is shown

in Fig in the next slide.



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I/O Instructions

Input Output devices

Transmitter and Receiver Interface

INPR + FGI

OUTR + FGO

Monitor Receiver OUTR

Keyboard Transmitter

AC

INPR

FGO

FGI



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Input Output Instructions

p: SC


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Interrupt Cycle

R

Fetch and Decode Save return Address

M[0] PC

EXECUTE IEN

FGI

FGO

Branch to Location 1

PC 1

R 1

10

0

1

0

1

0

1

IEN 0

R 0

Interrupt CycleInstruction Cycle



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Central Processing Unit (CPU)

It is the part of the computer that performs

bulk of data-processing operation.

It is made up of 3 major parts as shown

below :

Control

Register

ArithmeticLogic Unit(ALU)



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Components of the CPU

The Register set stores intermediate data used

during the execution of the instructions.

The Arithmetic Logic Unit (ALU) performs the

required micro-operations for executing the

instructions.

The Control Unit supervises the transfer of

information among the registers and instructsthe ALU as to which operation to perform.



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Stack Organization

A stack is a storage device for storing information in such a

manner that the item stored last is the first item retrieved(LIFO last-in, first-out).

The stack is a memory unit with an address register called a

stack pointer (SP), which always points at the top item in thestack.

The two operations of a stack are the insertion (push) anddeletion (pop) of items.

Push-operation increments the SP and pull-operationdecrements the SP.



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Stack Organization (contd)

Stack can reside ina portion of a large

memory unit or itcan be organized asa collection of afinite number of(fast) registers.

Fig here shows anorganization of 64-word register stack.



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Operations on Stack

Push (performed if stack is not full i.e.ifFULL = 0):



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Operations on Stack

Pop (performed if stack is not empty i.e.ifEMTY = 0):



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Stack implemented in the Computer

Memory Stack can also be implemented with RAM attached to a CPU:

a portion of memory is assigned to a stack operation

a processor register is used as a stack pointer

Fig. next shows how a portion of memory partitioned into three

segments: program, data, and stack.

Most computer do not provide hardware for checking stack

overflow or underflow

if registers are used to store the upper limit (e.g. 3000) and the lowerlimit (e.g. 4000), then after push SP can be compared against the upperlimit register, and after pull against the lower limit register.

The advantage of the memory stack is that CPU can refer it

without having to specify an address: the address in always in

SP and automatically updated during a push or pop instruction.



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Utility of using Stack(Evaluating

Arithmetic Expressions)

A stack is effective for evaluating arithmeticexpressions.

Arithmetic operations are usually written in infixnotation: each operator resides between the operands,

e. g.:(A * B) + (C * D), where * denotes

multiplication:

A * B and C * D has to be computed and stored.

after the two products, sum (A * B) + (C * D) is computed

there is no straight forward way todetermine the next operation that isperformed.



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Continued

Arithmetic expressions can be presented in prefixnotation (also referred to as Polish notation byPolish mathematician Lukasiewicz): operators are

placed before the operands.

The postfix notation (reverse Polish notation(RPN) ) places the operator after the operand.

E. g.:

A + B , infix notation

+AB , prefix notation

AB+ , postfix notation (RPN)



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Continued

The reverse Polish notation suits of stackmanipulation.

E. g. the expressionA * B + C * D

is written in RPN asAB* CD*+

and is evaluated by scanning from left to right:when operator is found, the operation is performedby using operands on the left side of the operator.The operator and operands are replaced by the result

of operation. The scan is continued and theprocedure is repeated for every operator:



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Continued1

. * is found2. Take the two operands from left: A and B3. compute P = A * B4. replace operands and operator with the result => PCD*+5. continue scan6. * is found7. Take the two operands from left: C and D

8. compute Q = C * D9. replace operands and operator with the result => PQ+10. continue scan11. + is found12. take the two operands from left: P and Q13. compute R = P + Q

14. replace operands and operator with the result: R15. continue scan: no more operators => stop; R is the result of evaluation.



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Conversion of Expressions from Infix

to RPN The conversion from infix to RPN must take into

consideration the operational hierarchy of infix notation:1. first perform arithmetic inside inner parentheses

2. then inside outer parentheses

3. perform multiplication and division before addition andsubtraction.

E .g.: (A + B)*[ C*( D + E) + F] becomes

AB+ DE+ C* F+* which is computed:

1. P = A+ B => PDE+ C* F+*

2. Q = D+ E => PQC* F+*

3. R = Q * C => PRF+*

4. S = R+ F => PS*

5. T = P* S

T represents the result: T = AB+ DE+ C* F+*



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Continued

RPN is the most efficient method known for evaluatingarithmetic expressions.

Used e. g. in electronic calculators.

Stack is useful for evaluating arithmetic expressions inRPN operands are pushed into the stack in the order of appearance

(in RPN)

the topmost operands are popped from the stack and used forthe operation

The result is pushed to replace the popped operands Most compilers convert all arithmetic expressions into

Polish notation: efficient translation of arithmeticexpressions into machine language instructions.



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Continued

E. g.: (3* 4)+( 5* 6) => 34* 56*+



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Instruction Formats

The typical fields found in instruction formatsare:1. Operation code specifying the operation: add,

subtract,complement, etc.

2. Address field designating a memory address or aregister

3. Mode field for specifying the way for determiningthe effective address of an operand.

The number of address fields in the instruction

format of a computer depends on the internalorganization of its registers.



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Continued

E.g.: MIPS (a RISC microprocessor architecture developed by MIPS

Computer Systems Inc.)

Register-Register

Register-immediate

Jump/Call



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Three-Address Instruction

Computers may have instructions of several differentlengths containing varying number of addresses.

E.g. three-address instructions : This instructionformat can use each address field to specify either a

processor register or a memory word. (A+B)*(C+D):ADD R1, A, B R1 M[A] + M[B]

ADD R2, C, D R2 M[C] + M[D]

MUL X, R1, R2 M[X] R1 * R2 Advantage of this format is that it results in short programs

when evaluating arithmetic expressions. Disadvantage is that the binary-coded instructions require too

many bits to specify three addresses.



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Two-Address Instruction

E.g. two-address instructions: Here also each address fieldcan specify either a processor register or a memory word.Program for the previous example

MOV R1, A R1 M[A]

ADD R1, B R1 R1+ M[B]MOV R2, C R2 M[C]

ADD R2, D R2 R2+ M[D]

MUL R1, R2 R 1 R1 * R2

MOV X, R1 M[X] R1

The first symbol listed in an instruction is assumed to be both asource and the destination where the result of the operation istransferred.



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One-Address Instruction

One-Address Instruction use an implied accumulator (AC). Here we

assume that Ac contains the result of the last operation.

LOAD A AC M[A]

ADD B AC AC +M[B]

STORE T M[T] ACLOAD C AC M[C]

ADD D AC AC + M[D]

MUL T AC AC *M[T]

STORE X M[X] AC



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Zero-Address Instruction

A stack-organized computer does not use an address field for theinstructions ADD and MUL. The PUSH and POP instructions, however, needan address field to specify the operand that communicates with the stack.The name zero-address is given to this type of instructions because of theabsence of an address field in them.

PUSH A TOS A

PUSH B TOS B

ADD TOS (A + B)

PUSH C TOS C

PUSH D TOS D

ADD TOS (C + D)

MUL TOS (C + D) * (A + B)

POP X M[X] TOS


Addressing Modes


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Addressing Modes

The addressing mode specifies a rule for interpreting or

modifying the address field of the instruction before theoperand is actually referenced.

Addressing modes are used:1. To provide programming versatility for the user:

pointers to memory, counters for loop control,indexing data, etc.

2. To reduce the number of bits in the addressingfield of the instruction.

The decoding phase of an instruction cycle determinesthe addressing mode(s) and the locations (registersand/or memory locations) of operands.

Depending on the CPU, an instruction can have morethan one address field, and each address field may beassociated with its own particular addressing mode.



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Different types of Addressing Mode Implied mode: The operands are implicitly specified by

the instruction, e.g.: complement accumulator.

Immediate mode: The operand is specified in theinstruction (in operand field). Can be used e.g. to initializeregister to constant value (=immediate operand).

Register mode: Operands are in registers that residewithin the CPU. The particular register is selected with theregister field of the instruction.

Register indirect mode: The content of a register specifies

the address of the operand in memory. Autoincrement or autodecrement mode: Similar to

register indirect mode but the content of the register isautomatically incremented/decremented after data access.



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Different types of Addressing Mode

Impliedmode: The operands are implicitly specified by theinstruction, e.g.: complement accumulator.

Immediatemode: The operand is specified in theinstruction (in operand field). Can be used e.g. to initialize

register to constant value (=immediate operand).



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Continued

Direct/Absolutemode: The operand is in either a RF register

or a MM location, whose address is explicitly given in the

instruction. I.e., the EA of the operand is given in the

instruction.



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Continued

Indirect mode: The EA of the operand is in the register, or MM

location, whose address is given in the instruction.


C ti d


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Continued

Indexmode: The EA of the operand is generated by adding a constant

value (given in the instruction) to the content of a register (specified inthe instruction). This is used to address elements of an array . Thestarting address of is the constant and the index is contained in the

register. Element can be addressed by this mode with different index .


C ti d


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Continued

Relativemode: Similar to index mode except the register is the PC. This is

used to address an operand in an MM location whose address is specifiedrelative to the current instruction. The EA is obtained by adding a constant(offset, or the displacement from current position to the location of theoperand, can be negative) and the content of PC. The constant is eitherexplicitly given in the instruction by the assembly programmer, or calculatedby the assembler based on the knowledge of the MM locations of theprogram and the desired operand.



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Continued

Baseregisteraddressingmode: The content of a base register isadded to the address part of the instruction to obtain the effective

address. The address part of the instruction gives thedisplacement relative to the base address.

EA = address part of instruction + content of CPUregister


P C t l


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Program Control

Program flow can be altered by

instructions that modify the

value of the program counter:

important feature of a digital

computer provides a control

over the program flow and

capability for branching to

different program segments.

Typical program control

instructions:

Name Mnemonic

Branch BR

Jump JMPSkip SKP

Call CALL

Return RET

Compare(

by

subtracting)

CMP

Test ( by TST2/13/2012 86Er. KAPIL PRASHAR

Continued


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Continued

Branch and jump instructions may be conditional or unconditional

An unconditional branch instruction causes a branch to the specific

address without any conditions, e.g.: JMP DisplayGreeting

The conditional branch specifies a condition, e.g. branch if zero: only when the

condition is met, the program counter is loaded with the branch address, e.g.:



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Continued

Compare and test instructions can be used

in setting conditions for subsequent

conditional branch instructions

Compare performs an arithmeticsubtraction: result is not saved only

status bit conditions are set as a result of

operation.

Similarly test performs logical AND of two

operands and updates certain status bits.



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Continued

The status register stores the values of the statusbits (status register is composed of the statusbits).

Bits of the status register are modified as a resultof an operation performed in the ALU.

Status bits also known as CONDITION-CODE bitsor FLAG bits



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Continued

E.g. (8-bit ALU with a 4-bit status register):



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Continued

Status bits can be checked after ALU operationto determine certain relationships that existbetween the values of A and B

V indicates overflow i.e. for 8-bit ALU the resultis greater than 127 or less than -127. If Z is set, the result is zero: we can use e.g. XOR operation to compare tonumbers (the result is zero iff A = B) and Zindicates the result of comparison.A single bit in A can be checked with a maskthat contains 1 in that particular bit position(others being 0s) and by using AND operation.



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Continued C

onditional branch instructions use the status bits forchecking conditions for branching:



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Subroutine Call

For subroutine calls, different computers can use a differenttemporary location for storing the return address

some computers use the first memory location of the subroutine(like the Basic Computer).

some store the return address in a fixed memory location.

some computers use a processor register.

stack memory is yet another possibility (the most efficient way):

when a succession of subroutines is called (nested calls), thesequential return addresses can be pushed into the stack. Thereturn from subroutine instruction pops the return address (andassigns to program counter) from the top of the stack: we alwayshave the return address for the last called subroutine.



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Continued

Subroutine call (stack based) microoperations:SP SP 1 Decrement stack pointerM[SP] PC Push contentofPC ontothe

stack

PC effectiveaddress Transfercontroltothesubroutine

.. and return:PC M[SP] Pop stackandtransferto PCSP SP + 1 Increment stack pointer

By using subroutine stack each return address (innested calls) can be pushed into the stack without

destroying any previous values e.g. in basic computer a recursive subroutine call would destroy theprevious return address stored in the first memory location of thesubroutine.



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Program Interrupt

Program interrupt refers to the transfer ofprogram control from a currently runningprogram to another service program as aresult of an external or internal generated

request otherwise similar to subroutine call, except:1. The interrupt is (usually) initiated by an internal of external signal

rather than an execution of an instruction (software interrupts areexceptions).

2. The address of the interrupt service program (routine) isdetermined by hardware rather than the address field of aninstruction: the CPU must possess some form of HW procedure forselecting a branch address servicing the interrupt.

3. Interrupt routine stores all the information (not just PC) necessaryto recover the state of the CPU prior the return from the interruptroutine.


C ti d


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Continued

After the interrupt routine the CPU must return exactlythe same state that is was when the interrupt occurred.

The state of the CPU at the end of the execute cycle (theinterrupt is recognized in this phase) is determined from:

1. The content of PC

2. The content of all processor registers3. The content of status conditions

status bits (program status word PSW) stored in a separatestatus register.

contains status information about the state of the CPU: bits

from ALU operation, interrupt enable bits, and CPU operationmode (system mode, user mode), for example.


Continued


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Some computer store only program counter (and PSW) priorentering to an interrupt routine the interrupt routine must take care of storing and restoring the

CPU status.

CPU does not respond to an interrupt until the end of aninstruction execution

in an interrupt is pending control goes to a interrupt cycle. contents of PC and PSW are pushed onto stack.

the branch address is transferred to PC and new PSW is loaded intothe status register.

the interrupt routine can now be executed starting from the branchaddress (which may contain a branch instruction to a user defined

service routine). the last instruction of the interrupt routine is a return from

interrupt: the stack is popped to retrieve PWS to status register andreturn address to PC => CPU state is restored and the interruptedprogram can proceed like nothing had happen.



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Interrupt Types

1. External interrupts from I/O, timing, or any other external source.

e.g.: I/O device requesting new data, elapsed time of an event, powerfailure, etc.

2. Internal interrupts (traps) from illegal or erroneous use of an instruction or data.

e.g.: overflow, division by zero, invalid operation code, stack overflow,and protection violation.

usually occur as a result of a premature termination of the instructionexecution: the service program determines the corrective measure to betaken (e.g. terminates the program).

3. Software interrupts initiated by an instruction (rather than HW signals)

a special call instruction that behaves like an interrupt.

can be used by a programmer to initiate an interrupt routine at anydesired point in the program.

can be used for accessing operating system services, for example.2/13/2012 98Er. KAPIL PRASHAR


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Control Unit

It is a part of the CPU.

Its purpose is to issue control signals that provide control

inputs for the multiplexers in the common bus, control

inputs in processor register, and microoperations for theaccumulator.

Two major types control organizations are there:

hardwired control & microprogrammed control.


Hardwired & Microprogrammed


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Hardwired & Microprogrammed

Control In the hardwired organization, the control signals are generated by

hardware using logic design techniques, the control unit is said to

be hardwired.

In the microprogrammed organization, the control information is

stored in a control memory. The control memory is programmed

to initiate the required sequence of microoperations. The principle

of microprogramming is an elegant and systematic method for

controlling the microoperation sequences in a digital computer.


C i d


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Continued

The control function that specifies amicrooperation is a binary variable. When it is inactive state, the corresponding microoperation isexecuted. A control variable in the opposite binary

state, does not change the state of the registers inthe system. The control variables at any given timecan be represented by a string of 1s and 0s calledthe control word.

In a bus-organized system, the control signals thatspecify microoperations are groups of bits thatselect the paths in multiplexers, decoders, andALU.2/13/2012 101Er. KAPIL PRASHAR

Basic Concepts of Microprogramming:


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Basic Concepts ofMicroprogramming:

Control word (CW): A word with each bit for one of the controlsignals. Each step of the instruction execution is represented by acontrol word with all of the bits corresponding to the control signalsneeded for the step set to one.

Microinstruction: Each step in a sequence of steps in the executionof a certain machine instruction is considered as a microinstruction,and it is represented by a control word. All of the bitscorresponding to the control signals that need to be asserted in thisstep are set to 1, and all others are set to 0 (horizontal

organization).



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Continued

Microprogram: Composed of a sequence ofmicroinstructions corresponding to the sequence of steps

in the execution of a given machine instruction.

Since alteration of microprogram are not needed once thecontrol unit is in operation, the control memory can be a

read-only memory (ROM).

Dynamic Microprogramming



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Control Memory

A computer that employs amicroprogrammed control unit will havetwo separate memories: a main memoryand a control memory.

The content of main memory may alterwhen the data are manipulated andevery time that the program is changed.

The control memory holds a fixedmicroprogram that cannot be altered bythe occasional user.


Mi g d t l it


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Microprogrammed control unit


Continued


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Continued SequencerorNext-addressgenerator

Used to generate the address of the next microinstruction to be retrievedfrom the control memory.

ControlAddressRegister

(CAR) Holds the address of the microinstruction generated by the

sequencer; provides address inputs to the control memory.

ControlMemory

(CM) Usually a ROM; holds the control words which make up the

microprogram for the MCU.

ControlDataRegister(pipeline register)

(CDR) Holds the control word being retrieved presently; used to

generate/propagate control function values to the MCU.

Because the CAR and CDR are registers, they can be used and modified inparallel. Thus, the CDR can be causing the execution of a collection of micro-ops atthesametime that it's being used to generate the next address (via the

sequencer) for the CAR.2/13/2012 106Er. KAPIL PRASHAR

Sequencing


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q g

Each machine instruction is executed through the application of a

sequence of microinstructions. Clearly, we must be able to sequencethese; the collection of microinstructions which implements aparticular machine instruction is called a routine.

The MCU typically determines the address of the firstmicroinstruction which implements a machine instruction based onthat instruction's opcode. Upon machine power-up, the CAR should

contain the address of the first microinstruction to be executed. The MCU must be able to execute microinstructions sequentially (e.g.,

within routines), but must also be able to ``branch'' to othermicroinstructions as required; hence, the need for a sequencer.

The microinstructions executed in sequence can be found sequentiallyin the CM, or can be found by branching to another location within

the CM. Sequential retrieval of microinstructions can be done bysimply incrementing the current CAR contents; branching requiresdetermining the desired CW address, and loading that into the CAR.


Microprogramming Vs Hardwired


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p g g

Control Hardwired:

composed of combinatorial and sequentialcircuits that generate complete timing thatcorresponds with execution of each instruction.

time-consuming and expensive to design

difficult to modify

but fast


Continued


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Continued

Microprogrammed:

Design is simpler problem of timing each instruction isbroken down. Microinstruction cycle handles timing in asimple and systematic way.

easier to modify

slower than hardwired control

In the microprogrammed control, any required changesor modifications can be done by updating themicroprogram in control memory. Once the hardwareconfiguration is established, there should be no need forfurther hardware or wiring changes.



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RISC/CISC

Instruction set determines the way that machinelanguage programs are constructed.

Early computers had small and simple

instruction sets in order to minimize the(expensive) hardware needed for theirimplementation.

Today many computers have instructions that

include 100 to 200 instructions variety of data types

large number of addressing modes


RISC/CISC


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RISC/CISC Complex instruction set computer (CISC) has complex hardware and large

instruction set: functions from software to hardware.

In contrast, reduced instruction set computer (RISC) uses fewer and simplerinstructions which can be executed faster within the CPU.

RISC chips require fewer transistors (than CISC), which makes them cheaper todesign and produce.

There is still considerable controversy among experts about the ultimate valueof RISC architectures

Its proponents argue that RISC machines are both cheaper and faster, and aretherefore the machines of the future.

Skeptics note that by making the hardware simpler, RISC architectures put agreater burden on the software. They argue that this is not worth the trouble

because conventional microprocessors are becoming increasingly fast andcheap anyway.



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Characteristics of CISC architecture:


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Characteristics of CISC architecture:

1. A large instruction set.

2. Instructions that perform special tasks and

are used infrequently.3. A large variety of addressing modes (5-20

different modes).

4. Variable-length instruction formats.

5. Instructions that manipulate operands inmemory.


Characteristics of RISC architecture:


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Characteristics of RISC architecture:

1. Relatively few instructions mostly register-to-register operations

2. Relatively few addressing modes (because of 1)

3. Memory access limited to load and store instructions.

4. All operations done within the register of the CPU.

5. Fixed-length, easily decoded instruction format aligned to word

boundaries simplifies control logic.

6. Single-cycle instruction execution

fetch, decode, and execute phases for two to three instructionsoverlap: pipelining.

Memory references may take more clock cycles.

7. Hardwired rather than microprogrammed control faster


Oth RISC h t i ti


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Other RISC characteristics:

1. A large number of register useful for storing intermediate results and for optimizing operand

references: much faster than memory references.

most frequent accessed operands are kept in registers.

2. Use of overlapped register windows to speed-up procedure call

and return.3. Efficient instruction pipeline

4. Compiler support for efficient translation of high-level languageprograms into machine language programs.

A characteristic of some RISC processors is their use ofoverlapped register windows to provide the passing ofparameters and avoid need for saving and restoring register

values: speeds up procedure calls and returns.


Input/Output Devices


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p / p

When using a computer the text of programs, commands to the

computer and data for processing have to be entered. Alsoinformation has to be returned from the computer to the user. Thisinteraction requires the use of input and output devices.

The most common input devices used by the computer are thekeyboard and the mouse. The keyboard allows the entry of textualinformation while the mouse allows the selection of a point on the

screen by moving a screen cursor to the point and pressing a mousebutton. Using the mouse in this way allows the selection from menuson the screen etc. and is the basic method of communicating withmany current computing systems. Alternative devices to the mouseare tracker balls, light pens and touch sensitive screens.

The most common output device is a monitor which is usually a

Cathode Ray Tube device which can display text and graphics. If hard-copy output is required then some form of printer is used.


Keyboard


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Keyboard

A computer keyboard is a peripheral modeled after thetypewriter keyboard.

Keyboards are designed for the input of text andcharacters, and also to control the operation of thecomputer.

Physically, computer keyboards are an arrangement ofrectangular or near-rectangular buttons, or "keys".Keyboards typically have characters engraved or printedon the keys; in most cases, each press of a keycorresponds to a single written symbol. However, toproduce some symbols requires pressing and holding

several keys simultaneously, or in sequence; other keys donot produce any symbol, but instead affect the operationof the computer, or the keyboard itself.


Mouse


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Mouse The mouse is a device that allows to control the

movement of the insertion point on the screen.

The operator places the palm of the hand over the mouseand moves it across a mouse pad, which provides tractionfor the rolling ball inside the device. Movement of the ball

determines the location of the I beam on the computerscreen. When the operator clicks the mouse the I beambecomes an insertion point which indicates the area youare working on the screen. You can also click the mouseand activate icons or drag to move objects and select text.


M it


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Monitor

A monitor's front is called a screen with a cathode raytube (CRT) attached to the screen.

The CRT contains an electronic gun that sends an

electronic beam to a phosphorescent screen in front of

the tube. To produce a pattern on the screen, a grid inside the CRT

receives a variable voltage that causes the beam to hit the

screen and make it glow at selected spots.


Printer


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Printer

Provide a permanent record on paper of computer outputdata or text.

Three basic types of printers are there :

Daisywheel : contains a wheel with the character placed along the

circumference. To print a character, the wheel rotates to the proper

position and an energized magnet then presses the letter against theribbon.

Dot matrix : contains a set of dots along the printing mechanism. Each

dot can be printed or not depending on the specific character that are

printed on the line.

Laser printer : uses a rotating photographic drum that is used toimprint the character images. The pattern is then transferred onto the

paper in same manner as a copying machine.


M ti t


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Magnetic tape

Are used mostly for storing files of data. Access is sequential

and consists of records that can be accessed one after

another as the tape moves along a stationary read-write

mechanism.

It is one of the cheapest and slowest method for storage andhas the advantage that tapes can be removed when not in

use.


M ti di k


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Magnetic disks

Have high-speed rotational surfaces coated with magnetic

material. Access is achieved by moving a read-write

mechanism to a track in the magnetized surface.

Disks are used mainly for bulk storage of programs and data.


Input Output Interface


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Input-Output Interface

There are three ways that computer buses can be used tocommunicate with memory and I/O:

1. Use two separate buses, one for memory andother for I/O.

2. Use a common bus for memory and I/O but

have separate control lines for each isolatedI/O configuration.

3. Use one common bus for memory and I/Owith common control lines: memory mappedI/O.

Follow this link for more study material:

http://www.ustudy.in/ce/arch/u2


Continued


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Continued

Some computers use one common bus to transferinformation between memory or I/O devices and theCPU

Isolated I/O configuration CPU has distinct input and output instructions

(e.g. IN, OU

T) address associated with the I/O instruction is

place into the common address bus

I/O read/write signal is enabled for initiating datatransfer between CPU and selected register of anI/O device.

Distinct read/write lines for I/O and memory.


Memory-mapped I/O


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one set of read and write signals for I/O and memory

no way to make difference between memory access and I/Oaccess => memory and I/O devices share the available address

space.

no distinct I/O instructions: same instructions are used to

manipulate memory words and I/O data.


Example of I/O Interface


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Continued


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The interface registers communicate with the CPU through

the bi-directional data bus.

Address bus is used to select the interface unit and the

register.

External circuit must be provided externally to generate

chip select (CS) signal (e.g. from address). Register select inputs are usually connected to the two

least significant lines of the address bus.

The content of the selected register is transferred to CPU

when the I/O read signal is enabled. CPU transfers data to a selected register when I/O write is

enabled.


Asynchronous Data Transfer


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Asynchronous Data Transfer If the registers in the I/O interface share a

common clock with CPU, the transfer betweenthe two units are said to be synchronous.

In most cases the internal timing in each unitis independent from the other in that eachunit uses its own private clock => units are saidto be asynchronous.

Asynchronous data transfer requires

communication signals to be transmittedbetween the communicating units to indicatethe time at which data is being transmitted.


Continued


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One way is to use strobe signal

one of the unit indicates to the other unit when

the transfer occurs:


Continued


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Another way is to use handshaking

data is acknowledged by the receiving unit:sender knows whether the data has beensuccessfully received or not


Continued


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..destination initiated transfer using handshake


Continued


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Handshaking allows arbitrary delays fromone state to the next and permits each unit

to respond at its own data rate.

If one unit is faulty, the data transfer cannot be

completed timeout can be used to detect this kind of error.

internal timer is used to measure time: if other unit does not

respond within a given time period, the unit assumes that an

error has occurred.


Continued


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The transfer of data can be parallel or serial

parallel transfer is fast but requires many wires: used for shortdistances and when speed is important.

serial transfer is slower but requires only one pair of conductors.

A serial asynchronous data transmission technique usedin many interactive terminals employs special bits that are

inserted at both ends of the character code each character consists of three parts

1. a start bit

2. the character bits (data)

3. ..and stop bits

when transmitter is idle the data line remains at highstate (logic 1).


Continued


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the first bit, called start bit, is always a 0 and is used to indicate the

beginning of a character (data). The last bit called stop bit is always a 1.

A transmitted character can be detected by the receiver fromknowledge of transmission rules:

1. When data is not being send, the line is kept in the 1-state.

2. The initiation of data transmission is detected from the start bit,which is always 0.

3. The data bits always follow the start bit.

4. After the last bit of the data transmitted, a stop bit is detectedwhen the line returns to the 1-state for at least one bit time

line remains at 1-state until next start bit.

the receiver knows the transfer rate and number of data bits: it canexamine the line at proper times and receive valid bits.


Continued


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E.g.: asynchronous serial transmission (8data bits, 2 stop bits):


Continued


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Continued

Baudrate is defined as the rate at which serial information istransmitted and is equivalent to the data transfer in bits persecond: assume 10 characters per second, i.e.10 * 11bits/second (start + 8 data + 2stop), => baudrate is 110.


Modes of Transfer


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Modes of Transfer

Data transfer between the central computer and I/O

devices may be handled in a variety of modes.

1. Programmed I/O

2. Interrupt-initiated I/O

3. Direct memory access (DMA).


Programmed I/O


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Programmed I/O

Each data item transfer is initiated by an instructionin the program.

Peripheral to CPU and CPU to Memory or vice versa.

Transferring data under program control requiresconstant monitoring of the peripheral by the CPU.

Once the data transfer is initiated, the CPU isrequired to monitor the interface to see when atransfer can again be made.


Interrupt-initiated I/O


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Programmed I/O is time consuming method since it keeps the CPU ina loop until the I/O unit indicates that it is ready for data transfer.

It can be avoided by using an interrupt facility and special commandsto inform the interfaces to issue an interrupt request signal when the

data are available from the device. In the meantime CPU can go withprocessing other programs.

When the interface that keeps monitoring the device finds it ready, itgenerates an interrupt signal and the CPU then stops its task andbranches to a service program to process the I/O transfer and thenreturn to the task it was performing.


Direct Memory Access


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In DMA, the interface transfers data into and out of the memory

unit through the memory bus.

CPU initiates the transfer by supplying the interface with the starting

address and the number of words needed to be transferred. And

then proceeds to execute other task.

After the transfer is made, the DMA requests memory cycles

through the memory bus.

After memory controller grants the request the DMA transfer the

data directly into memory.


DMA


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The CPU and the DMA controller cannot use the system bus atthe same time, so some way must be found to share the busbetween them. One of two methods is normally used.

1. Burst mode

The DMA controller transfers blocks of data by halting the CPU and

controlling the system bus for the duration of the transfer. The transfer

will be as quick as the weakest link in the I/O module/bus/memorychain, as data does not pass through the CPU, but the CPU must still behalted while the transfer takes place.

2. Cycle stealing

The DMA controller transfers data one word at a time, by using the busduring a part of an instruction cycle when the CPU is not using it, or bypausing the CPU for a single clock cycle on each instruction. This mayslow the CPU down slightly overall, but will still be very efficient.



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The connection between the DMA controller and othercomponents in a computer system for DMA transfer isshown in figure.


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shown in figure.


DMA Transfer


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The DMA request line is used to request a DMA transfer. The bus request (BR) signal is used by the DMA controller to request the CPU to

relinquish control of the buses.

The CPU activates the bus grant (BG) output to inform the external DMA that itsbuses are in a high-impedance state (so that they can be used in the DMAtransfer.)

The address bus is used to address the DMA controller and memory at given

location The Device select (DS) and register select (RS) lines are activated by addressing the

DMA controller.

The RD and WR lines are used to specify either a read (RD) or write (WR) operationon the given memory location.

The DMA acknowledge line is set when the system is ready to initiate data transfer.

The data bus is used to transfer data between the I/O device and memory. When the last word of data in the DMA transfer is transferred, the DMA controller

informs the termination of the transfer to the CPU by means of the interrupt line.


Channel I/O


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/

This is a system traditionally used on

mainframe computers, but is becoming

more common on smaller systems. It is an

extension of the DMA concept, where theDMA controller becomes a full-scale

computer system itself which handles all

communication with the I/O modules.


Memory System


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y y

Memory is Internal storage area in thecomputer. The term memoryidentifies datastorage that comes in the form of chips, andthe word storage is used for memory thatexists on tapes or disks. Moreover, the termmemoryis usually used as a shorthand for

physical memory, which refers to the actual

chips capable of holding data. Somecomputers also use virtual memory, whichexpands physical memory onto a hard disk.


Different types of memory


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yp y

1. Main memory

2. Auxiliary memory

3. Associative memory

4. Virtual memory

5. Cache memory


Memory Hierarchy


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Hierarchy diagram

Magnetictapes

Magneticdisks

IO Processor

CPU

Mainmemory

Cachememory


Continued


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The memory hierarchy system consists of all

storage devices employed in a computersystem from the slow but high capacityauxiliary memory to a relatively faster mainmemory, to an even smaller and faster cache

memory accessible to the high speedprocessing logic.

At the bottom of the hierarchy are therelatively slow magnetic tapes used to storeremovable files.

Next are the magnetic disks used as backupstorage.


Continued


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The main memory occupies a central position by being able to

communicate directly with the CPU and with auxiliary memorydevices through an I/O processor. When programs not residing in

main memory are needed by the CPU, they are brought in from

auxiliary memory. Programs not currently needed in main memory

are transferred into auxiliary memory to provide space for currently

used programs and data.

Cache is a very high speed memory. It increase the speed of

processing by making current programs and data available to the CPU

at a rapid rate.

Cache is employed in the computer system to to compensate for the

speed differential between main memory access time and processor

logic which is usually very fast.


Memory Management


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y g

A programs machine language code must be in thecomputers main memory in order to execute. Assuring

that at least the portion of code to be executed is in

memory when a processor is assigned to a process is the

job of the memory manager of the operating system.

This task is complicated by two other aspects of modern

computing systems:

The first is multiprogramming.

The second aspect is the need to allow the programmer to use a

range of program addresses which may be larger, perhaps

significantly larger than the range of memory locations actually

available.


Multiprogramming


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Multiprogramming mean that several (at least two) processes can be

active within the system during any particular time interval. These multiple active processes result from various jobs entering and

leaving the system in an unpredictable manner. Pieces, or blocks, ofmemory are allocated to these processes when they enter the system,and are subsequently freed when the process leaves the system.Therefore, at any given moment, the computers memory, viewed as awhole, consists of a part of blocks, some allocated to processes active

at that moment, and others free and available to a new process whichmay, at any time, enter the system.

In general, then , programs designed to execute in thismultiprogramming environment must be compiled so that they canexecute from any block of storage available at the the time of theprograms execution. Such program are called relocatable programs,

and the idea of placing them into any currently available block ofstorage is called relocation.


2nd Aspect


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The second aspect of modern computing systems affectingmemory management is the need to allow theprogrammer to use a range of program addresses whichmay be larger, perhaps significantly larger than the rangeof memory locations actually available. That is, we want toprovide the programmer with a virtual memory, withcharacteristics (especially size) different from actualmemory, and provide it in a way that is invisible to theprogrammer. This is accomplished by extending the actualmemory with secondary memory such as disk. Providingan efficiently operating virtual memory is another task for

the memory management facility.


Relocation


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Relocation of currently active programs is called dynamic relocation. If

a currently executing process could be relocated, both the computersresponse time and resource utilization could be improved.

Actual implementation of dynamic relocation is not trivial. The

compiler can not possibly assign the correct addresses because a

program must be complied before it can be loaded and executed.

Thus, program relocation, especially dynamic relocation the movingaround of currently active processes must be done by the operating

systems memory management facility.

Given the needs for multiprogramming and virtual memory, and

having the mechanism of dynamic relocation, it is time to take a

serious look at how one might design the actual memory manger.


Actual memory management Creating and maintain an environment which will sustain both


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Creating and maintain an environment which will sustain bothmultiprogramming and virtual memory consists basically of designing a

memory management program which will facilitate the timely movement ofblocks of program code into portions of main memory when they are aboutto be executed, and out of main memory to secondary memory (disk) whenthey are no longer needed.

There are basically three approaches to this problem.

In the fist approach, called swapping, all of the code for a particularprocess is transferred into main storage prior to dispatching the

processor to the process. When the process becomes blocked or its timeslice used up, the entire block of code is again swapped out to secondarystorage to be replaced by the block of code representing the next processto assume control of the processor, and so on. This approach, whilereasonable when the size of main memory is limited, obviously causes asubstantial execution delay overhead during the swapping itself. Thisoverhead cost can sometimes be ameliorated by alternative approaches,which move parts of the code for processes rather than code for entireprocesses.


ContinuedTh th t h t ti


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The other two approaches are segmentation

and paging. Both recognize the fact that onlythat portion of a process code which is aboutto execute actually needs to be in main storageat any particular time.

These approaches have two major advantages

over swapping. First, if just a part of a currently executing process

needs to be in main memory at a given time, then itfollows that parts of more process can besimultaneously in main store, and thus a greater

degree of multiprogramming can be facilitated inthe system. The term degree of multiprogrammingrefers to the number of processes currently activewithin the system.


Continued


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The second advantage of segmentation or paging is

that the capability to move just part of programs

allows part of a program to be loaded into memory

and executed, and then be replaced by another partto be requiring a very large amount of memory,

perhaps in total, more than the capacity of the

computers main store. But this would be, then, an

implementation of virtual memory, as it has been

described above.


Continued


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Segmentation and paging differ from one another primarily in the waythe code for a particular process is divided.

In segmentation, a program code is divided into number of variablesized blocks corresponding to the logical structure of the program,such as procedures, functions and data segments.

Paging, on the other hand, divides the program code into fixed blocks,called pages.

It is evident that the more logical subdivision of segmentation makes

program linking easier, while the fixed blocks of paging, being eachinterchangeable with the other, makes memory management easier.

In either case, since portions of programs code are being movedaround during a programs execution, something like a hardwarerelocation register will be needed to compute actual addresses inorder to avoid unacceptable slowdown in program execution times.


Main Memory (RAM)


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The memory unit that communicates directly with theCPU is called the mainmemory.

It is a relatively large and fast memory to store programsand data during the computer operation.

The principal technology used for the main memory is

based on semiconductor integrated circuits. Integratedcircuits RAM (Random Access Memory) is a read / writememory. Data can be read from or written into thememory in a random access mode. However, it is a volatiledevice. Data will be lost if power is off.

There are two basic types of RAM in use today, dynamicRAM and StaticRAM.


Dynamic RAM


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Dynamic RAMs(DRAM) are designed for high capacity,moderate speeds, and low power consumption. Their

memory cells are basically charge-storage capacitors with

driver transistors. The presence or absence of charge in a

capacitor is interpreted by the sense line of the RAM as 1

or 0.

The charge in a capacitor has tendency to discharge itself,

therefore dynamic RAMs are required periodic charging to

maintain the data stored. This periodic charging is called

refreshing.


Static RAM


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Static RAMs(SRAM) are made of flip-flops andlogic gates. Since a flip-flop is a bistableelements, it can be used to store the binaryvalues. Operations of flip-flops are fast and do

not require refreshing. However, due to the unit complexity, the

capacity of static RAM is low compared withdynamic RAM. For the same reason, power

consumption and the cost of unit storage arehigh, too.


Comparison of the different

characteristics between dynamic & static


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RAMs.

PARAMETER DRAM SRAM

Power Consumption Low High

Capacity High Low

Price Cheap Expensive

Refreshing Required Not required

Speed Slow Fast


More types of RAM


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yp

SDRAM (synchronous dynamic RAM) :

SDRAM can handle bus speeds of up to 100 MHz, and theseare fast approaching. SDRAM is synchronized with the system

clock itself, a technical feat that has eluded PC engineers untilnow. SDRAM technology allows two pages of memory to beopened simultaneously


More types of RAM


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DDR (Double Data Rate SDRAM)

DDR basically doubles the rate of data transfer of standardSDRAM by transferring data on the up and down tick of aclock cycle. DDR memory operating at 333MHz actuallyoperates at 166MHz * 2 (aka PC333 / PC2700) or 133MHz*2(PC266 / PC2100). DDR is a 2.5 volt technology that uses 184pins in its DIMMs. It is incompatible with SDRAM physically,but uses a similar parallel bus, making it easier to implementthan RDRAM, which is a different technology.


Read Only Memory (ROM)


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Read Only Memories (ROM) are those inwhich the data is permanently programmedeither at the time of manufacture or by theuser prior to the memory being installed. They

are non-volatile memories. Still, they arerandom access devices.

There are different types of ROMs. The readonlyrefers to the applications at the end

users view. Writing the information into theROM is required prior to use.


Types of ROM


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1. Standard ROMs : Standard ROMs are programmed by the

manufacturer.Users can only read the data or execute programs

in the ROM. Usually, standard ROMs store certain standard

applications for general user

applications.

2. Programmable ROMs : Programmable ROMs (PROM) can be

programmed permanently by the user or distributor using special

equipment. They can only be programmed once. Before the data

is written into the PROM, users should verify the correctness of

the contents.


Types of ROM (Cont)


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3. Erasable Programmable ROMs : Erasable programmable ROMs(EPROM) can be programmed and erased by the user for manytimes. Erasure is carried out by shining high intensity ultra-violetlight through a special transparent window at the top of the

memory IC. Erasing and writing to the ROM are assisted by aspecial device called EPROM writer.

4. Electrically Erasable Programmable ROMs : Electrically erasableprogrammable ROMs (EEPROM) are similar to the EPROM.

Instead of erasure of entire chip, user can erase a single bitelectrically in one operation. Again, the operations require aspecial equipment.


Auxiliary Memory


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Devices that provide backup storage. When information not residing in main memory is

required by the CPU, they are brought in from auxiliarymemory

Programs not currently needed in main memory are

transferred to auxiliary memory to provide space forcurrently used programs and data.

Most common auxiliary memory devices used in computersystems are magnetic disks and tapes.

Other components used, but not as frequently, are

magnetic drums, magnetic bubble memory, and opticaldisks.


Magnetic disks


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Is a circular plate constructed of metal orplastic coated with magnetized material.

Often both sides of the disks are used andseveral disks may be stacked on one spindlewith read/write heads available on eachsurface .

Bits are stored in the magnetized surface inspots along concentric circles called tracks.

the tracks are commonly divided into sections

called sectors. In most systems, the minimumquantity of information which can betransferred is a sector.


Continued


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In units using single read/write head for eachdisk surface, the track address bits are used by

a mechanical assembly to move the head into

the specified track position before reading orwriting.

In other disk systems, separate read/write

heads are provided for each track in each

surface.


Magnetic Disk


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Continued


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A disk system is addressed by address bits thatspecify the disk number, the disk surface, thesector number and the track within the sector.

After the read/write heads are positioned inthe specified track, the system has to waituntil the rotating disk reaches the specifiedsector under the read/write head.

Information transfer is very fast once thebeginning of a s

csa complete

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