cs 213 lecture 10: multiprocessor 3: directory organization

22
CS252/Patterson Lec 12.1 2/28/01 CS 213 Lecture 10: Multiprocessor 3: Directory Organization

Upload: werner

Post on 12-Jan-2016

40 views

Category:

Documents


0 download

DESCRIPTION

CS 213 Lecture 10: Multiprocessor 3: Directory Organization. Larger MPs. Separate Memory per Processor Local or Remote access via memory controller 1 Cache Coherency solution: non-cached pages Alternative: directory per cache that tracks state of every block in every cache - PowerPoint PPT Presentation

TRANSCRIPT

Page 1: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.1

2/28/01

CS 213

Lecture 10: Multiprocessor 3: Directory

Organization

Page 2: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.2

2/28/01

Larger MPs• Separate Memory per Processor• Local or Remote access via memory controller• 1 Cache Coherency solution: non-cached pages • Alternative: directory per cache that tracks state of

every block in every cache– Which caches have a copies of block, dirty vs. clean, ...

• Info per memory block vs. per cache block?– PLUS: In memory => simpler protocol (centralized/one location)– MINUS: In memory => directory is ƒ(memory size) vs. ƒ(cache size)

• Prevent directory as bottleneck? distribute directory entries with memory, each keeping track of which Procs have copies of their blocks

Page 3: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.3

2/28/01

Organizing Directories

Centralized Distributed

HierarchicalFlat

Memory-based Cache-based

Directory Schemes

How to find source ofdirectory information

How to locate copies

Page 4: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.4

2/28/01

How to Find Directory Information

• centralized memory and directory - easy: go to it

– but not scalable

• distributed memory and directory– flat schemes

» directory distributed with memory: at the home

» location based on address (hashing): network xaction sent directly to home

– hierarchical schemes» ??

Page 5: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.5

2/28/01

Distributed Directory MPs

Page 6: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.6

2/28/01

How Is Location of Copies Stored?

– vary a lot– different storage overheads and performance

characteristics

– Memory-based schemes» info about copies stored all at the home with the

memory block» Dash, Alewife , SGI Origin, Flash

– Cache-based schemes» info about copies distributed among copies

themselves• each copy points to next

» Scalable Coherent Interface (SCI: IEEE standard)

Page 7: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.7

2/28/01

Flat, Memory-based Schemes• info about copies colocated with block

at the home– just like centralized scheme, except distributed

• Performance Scaling– traffic on a write: proportional to number of

sharers– latency on write: can issue invalidations to

sharers in parallel

• Storage overhead– simplest representation: full bit vector, i.e. one

presence bit per node– storage overhead doesn’t scale well with P; 64-

byte line implies» 64 nodes: 12.7% ovhd.» 256 nodes: 50% ovhd.; 1024 nodes: 200%

ovhd.– for M memory blocks in memory, storage

overhead is proportional to P*M

P

M

Page 8: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.8

2/28/01

Implementing a Directory

• Directory has a table to track which processors have data in the shared state (usually bit vector, 1 if processor has copy). Also, distinguish between shared/exclusive when present in only one processor by another column.

• We assume operations atomic, but they are not; reality is much harder; must avoid deadlock when run out of buffers in network (see Appendix E)

• Optimizations:– read miss or write miss in Exclusive: send

data directly to requestor from owner vs. 1st to memory and then from memory to requestor

Page 9: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.9

2/28/01

Page 10: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.10

2/28/01

Directory Protocol

• Similar to Snoopy Protocol: Three states– Shared: ≥ 1 or more processors have data, memory

is up-to-date– Uncached (no processor has data; not valid in any

cache)– Exclusive: 1 processor (owner) has data;

memory may be out-of-date

• Keep the protocol simple:– Writes to non-exclusive data

=> write miss– Processor blocks until access completes– Assume messages received

and acted upon in order sent

Page 11: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.11

2/28/01

Directory Protocol

• No bus and don’t want to broadcast:– interconnect no longer single arbitration point– all messages have explicit responses

• Terms: typically 3 processors involved– Local node where a request originates– Home node where the memory location

of an address resides– Remote node has a copy of a cache

block, whether exclusive or shared

• Example messages on next slide: P = processor number, A = address

Page 12: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.12

2/28/01

Directory Protocol MessagesMessage type Source Destination Msg Content

Read miss Local cache Home directory P, A– Processor P reads data at address A;

make P a read sharer and arrange to send data back Write miss Local cache Home directory P, A

– Processor P writes data at address A; make P the exclusive owner and arrange to send data back

Invalidate Home directory Remote caches A– Invalidate a shared copy at address A.

Fetch Home directory Remote cache A– Fetch the block at address A and send it to its home directory

Fetch/Invalidate Home directory Remote cache A– Fetch the block at address A and send it to its home directory;

invalidate the block in the cacheData value reply Home directory Local cache Data

– Return a data value from the home memory (read miss response)

Data write-back Remote cache Home directory A, Data– Write-back a data value for address A (invalidate response)

Page 13: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.13

2/28/01

State Transition Diagram for an Individual Cache Block in a

Directory Based System

• States identical to snoopy case; transactions very similar.

• Transitions caused by read misses, write misses, invalidates, data fetch requests

• Generates read miss & write miss msg to home directory.

• Write misses that were broadcast on the bus for snooping => explicit invalidate & data fetch requests.

• Note: on a write, a cache block is bigger, so need to read the full cache block

Page 14: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.14

2/28/01

CPU -Cache State Machine

• State machinefor CPU requestsfor each memory block

• Invalid stateif in memory

Fetch/Invalidatesend Data Write Back message

to home directory

Invalidate

InvalidShared

(read/only)

Exclusive(read/writ)

CPU Read

CPU Read hit

Send Read Missmessage

CPU Write: Send Write Miss msg to h.d.

CPU Write:Send Write Miss messageto home directory

CPU read hitCPU write hit

Fetch: send Data Write Back message to home directory

CPU read miss:Send Read Miss

CPU write miss:send Data Write Back message and Write Miss to home directory

CPU read miss: send Data Write Back message and read miss to home directory

Page 15: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.15

2/28/01

State Transition Diagram for the Directory

• Same states & structure as the transition diagram for an individual cache

• 2 actions: update of directory state & send msgs to satisfy requests

• Tracks all copies of memory block.

• Also indicates an action that updates the sharing set, Sharers, as well as sending a message.

Page 16: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.16

2/28/01

Directory State Machine

• State machinefor Directory requests for each memory block

• Uncached stateif in memory

Data Write Back:Sharers = {}

(Write back block)

UncachedShared

(read only)

Exclusive(read/writ)

Read miss:Sharers = {P}send Data Value Reply

Write Miss: send Invalidate to Sharers;then Sharers = {P};send Data Value Reply msg

Write Miss:Sharers = {P}; send Data Value Replymsg

Read miss:Sharers += {P}; send Fetch;send Data Value Replymsg to remote cache(Write back block)

Read miss: Sharers += {P};send Data Value Reply

Write Miss:Sharers = {P}; send Fetch/Invalidate;send Data Value Replymsg to remote cache

Page 17: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.17

2/28/01

Example Directory Protocol• Message sent to directory causes two actions:

– Update the directory– More messages to satisfy request

• Block is in Uncached state: the copy in memory is the current value; only possible requests for that block are:

– Read miss: requesting processor sent data from memory &requestor made only sharing node; state of block made Shared.

– Write miss: requesting processor is sent the value & becomes the Sharing node. The block is made Exclusive to indicate that the only valid copy is cached. Sharers indicates the identity of the owner.

• Block is Shared => the memory value is up-to-date:– Read miss: requesting processor is sent back the data from memory &

requesting processor is added to the sharing set.– Write miss: requesting processor is sent the value. All processors in

the set Sharers are sent invalidate messages, & Sharers is set to identity of requesting processor. The state of the block is made Exclusive.

Page 18: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.18

2/28/01

Example Directory Protocol• Block is Exclusive: current value of the block is

held in the cache of the processor identified by the set Sharers (the owner) => three possible directory requests:

– Read miss: owner processor receives data fetch message from home directory, causing state of block in owner’s cache to transition to Shared and causes owner to send data to directory, where it is written to memory & sent back to requesting processor. Identity of requesting processor is added to set Sharers, which still contains the identity of the processor that was the owner (since it still has a readable copy). State is shared.

– Data write-back: owner processor is replacing the block and hence must write it back, making memory copy up-to-date (the home directory essentially becomes the owner), the block is now Uncached, and the Sharer set is empty.

Page 19: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.19

2/28/01

Example Directory Protocol Contd.

– Write miss: block has a new owner. A message is sent to old owner causing the cache to send the value of the block to the directory from which it is sent to the requesting processor, which becomes the new owner. Sharers is set to identity of new owner, and state of block is made Exclusive.

Cache to Cache Transfer: Can occur with a remote read or write miss. Idea: Transfer block directly from the cache with exclusive copy to the requesting cache. Why go through directory? Rather inform directory after the block is transferred => 3 transfers over the IN instead of 4.

Page 20: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.20

2/28/01

Basic Directory Transactions

P

A M/D

C

P

A M/D

C

P

A M/D

C

Read requestto directory

Reply withowner identity

Read req.to owner

DataReply

Revision messageto directory

1.

2.

3.

4a.

4b.

P

A M/D

CP

A M/D

C

P

A M/D

C

RdEx requestto directory

Reply withsharers identity

Inval. req.to sharer

1.

2.

P

A M/D

C

Inval. req.to sharer

Inval. ack

Inval. ack

3a. 3b.

4a. 4b.

Requestor

Node withdirty copy

Directory nodefor block

Requestor

Directory node

Sharer Sharer

(a) Read miss to a block in dirty state (b) Write miss to a block with two sharers

Page 21: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.21

2/28/01

Protocol Enhancements for Latency

• Forwarding messages: memory-based protocols

L H R

1: req

2:reply

3:intervention

4a:revise

4b:response

L H R

1: req 2:intervention

3:response4:reply

L H R

1: req 2:intervention

3b:response

3a:revise

(a) Strict request-reply (a) Intervention forwarding

(a) Reply forwarding

Intervention is like a req,but issued in reaction to req. and sent to cache, rather than memory.

Page 22: CS 213 Lecture 10:   Multiprocessor 3: Directory Organization

CS252/PattersonLec 12.22

2/28/01

Assume Network latency = 25 cycles