cpre 583 reconfigurable computing lecture 4: 9/02/2011 (vhdl overview 2 )
DESCRIPTION
CPRE 583 Reconfigurable Computing Lecture 4: 9/02/2011 (VHDL Overview 2 ). Instructor: Dr. Phillip Jones ([email protected]) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA. http://class.ece.iastate.edu/cpre583/. VHDL questions. Questions From Last Lecture?. - PowerPoint PPT PresentationTRANSCRIPT
1 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
CPRE 583Reconfigurable Computing
Lecture 4: 9/02/2011(VHDL Overview 2 )
Instructor: Dr. Phillip Jones([email protected])
Reconfigurable Computing LaboratoryIowa State University
Ames, Iowa, USA
http://class.ece.iastate.edu/cpre583/
2 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• VHDL questions
Questions From Last Lecture?
3 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• VHDL questions
Questions From Last Lecture?
4 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• HW1 due next Friday
• MP1 will be released Friday night.
• Common tools issue: You may need to set the path to vsim in ise
• If you are new to VHDL or need a refresher, then READ the Shock and Awe VHDL tutorial. Feel free to ask me questions if you need any further clarification on any topics
Announcements/Reminders
5 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• Detailed in class VHDL example
• An intro to MP1
• A demo for getting started with MP1
Overview
6 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• A better understanding of how to describe hardware structures using VHDL
What you should learn
7 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
VHDL: IF and CASE constructs• IF THEN ELSE can be mapped to a 2:1
Multiplexer (Mux)
2:1Mux
sel = b“0”
4
44
x”C”
x”D”
in_0
in_1x”C”
IF (sel = ‘0’) THEN out_1 <= in_0;ELSE out_1 <= in_1END IF;
out_1
8 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
VHDL: IF and CASE constructs
4:1Mux
sel = b“10”
4444
2
4
x”C”
x”D”
x”2”x”7”
in_0
in_1
in_2
in_3
x”7”
• Mapping a CASE statement to a 4:1 Mux
out_1
CASE sel is WHEN “00” => out_1 <= in_0;WHEN “01” => out_1 <= in_1;WHEN “10” => out_1 <= in_2;WHEN “11” => out_1 <= in_3WHEN OTHERS => out_1 <= in_0;END CASE; Why do we need others here?
9 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
std_logic, std_logic_vector• Very common data types
• std_logic– Single bit value– Values: U, X, 0, 1, Z, W, H, L, -– Example: signal A : std_logic;
• A <= ‘1’;• Std_logic_vector: is an array of std_logic
– Example: signal A : std_logic_vector (4 downto 0);• A <= x“00Z001”
10 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• We will used counting events (e.g. part of MP2 as a motivating example)
Detailed VHDL design exercises
11 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
12 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
IP src
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
13 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
IP dest IP src
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
14 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
src port IP dest IP src
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
15 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
dest port src port IP dest IP src
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
16 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
length dest port src port IP dest IP src
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
17 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
Data 1 length dest port src port IP dest IP src
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
18 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
Data 2 Data 1 length dest port src port IP dest IP src
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
19 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
Data 3 Data 2 Data 1 length dest port src port IP dest
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
20 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
Send Alert
Data 3 Data 2 Data 1 length dest port src port IP dest
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
21 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
Send Alert
r o C length dest port src port IP dest
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
22 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
Send Alert
n r o C length dest port src port
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
23 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
Send Alert
! n r o C length dest port
FSM + Management
logic
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
24 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Streaming Network application (MP2)
FSM + Management
logic
Send Alert
Modify Packet
! n r o C length dest port
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
25 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Architecture
Alert FSM
Alert
Register & CounterManagement
Packet InputProcess
Packet OutputProcess
2:1Mux
corn_cnt
outputsel
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
position
Packet Length
Draw out logic, and data flow!!!
26 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Architecture
Alert FSM
Alert
Register & CounterManagement
Packet InputProcess
Packet OutputProcess
2:1Mux
corn_cnt
outputsel
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
position
Packet Length
27 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• Alert signal when the pattern “corn!” is detected– Z = {Alert}
Alert FSM Design
“c”/0
c o r n
“o”/0 “r”/0
Start
!
“n”/0
“!”/1others/0
others/0
others/0others/0
28 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• Alert signal when the pattern “corn!” is detected• Output Packet’s Length
– Z = {Alert,length_vld,pack_length}– X = {vld,input} : Note “?” is don’t care
Alert FSM Design
“c”/0
c o r n
“o”/0 “r”/0
Start
!
“n”/0
“!”/1others/0
others/0
others/0others/0
29 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• Alert signal when the pattern “corn!” is detected• Output Packet’s Length
– Z = {Alert,length_vld,pack_length}– X = {vld,input} : Note “?” is don’t care
Alert FSM Design
1,“c”/0,0,0
c o r n
1,“o”/0,0,0 1,“r”/0,0,0
Start
!
1,“n”/0,0,0
1,“!”/1,0,01,others/0,0,0
1,others/0,0,0
1,others/0,0,01,others/0,0,0
StartIP
IPH_2
1,”?”/0,0,0
IPH_5
1,”?”/0,0,0UDPports
UDPlength
1,”?”/0,0,0
1,”?”/0,1,length
30 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Architecture
Alert FSM
Alert
Register & CounterManagement
Packet InputProcess
Packet OutputProcess
2:1Mux
corn_cnt
outputsel
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
position
Packet Length
31 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
• Register & Counter Components• Design of Manager
Register & Counter Manager
32 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Register and Counter Components
4:1Mux
DFF8 count
+ 8 8
Counter
inc_val
0set_value
sel(reset,load,inc)
resetloadinc
3:1Mux DFF
8 reg_val8
Register
0set_value
sel(reset,load)reset
load
33 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Practice: Write VHDL(process for each)
4:1Mux
DFF8 count
+ 8 8
Counter
inc_val
0set_value
sel(reset,load,inc)
resetloadinc
3:1Mux DFF
8 reg_val8
Register
0set_value
sel(reset,load)
resetload
CASE sel is WHEN “00” | “11”=> out_1 <= in_0;WHEN “01” => out_1 <= in_1;
WHEN OTHERS => out_1 <= in_0;END CASE;
Name : process(clk)begin if(clk’event and clk=‘1’) then logic here end if;end process Name
34 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Register VHDL
3:1Mux DFF
8 reg_val8
Register
0set_value
sel(reset,load)
reset
load
Name : process(clk)begin if(clk’event and clk=‘1’) then CASE reset&load is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if;end process Name
35 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Register VHDL
3:1Mux DFF
8 reg_val8
Register
0set_value
sel(reset,load)
reset
load
Name : process(clk)begin if(clk’event and clk=‘1’) then CASE sel is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if;end process Name
sel <= reset&load;
36 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Counter VHDLName : process(clk)begin if(clk’event and clk=‘1’) then CASE reset&load&inc is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if;end process Name
4:1Mux
DFF8 count
+ 8 8
Counter
inc_val
0set_value
sel(reset,load,inc)
resetloadinc
37 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Counter VHDLName : process(clk)begin if(clk’event and clk=‘1’) then CASE sel is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if;end process Namesel <= reset&load&inc;
4:1Mux
DFF8 count
+ 8 8
Counter
inc_val
0set_value
sel(reset,load,inc)
resetloadinc
38 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Architecture
Alert FSM
Alert
Register & CounterManagement
Packet InputProcess
Packet OutputProcess
2:1Mux
corn_cnt
outputsel
• To count and insert counts into data flow we need a few more control signals
position
Packet Length
39 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Architecture
Alert FSM
Alert
Register & CounterManagement
Packet InputProcess
Packet OutputProcess
2:1Mux
corn_cnt
outputsel
• To count and insert counts into data flow we need a few more control signals
position
Packet Lengthlength_vld
reset
data_vlddata
reset
Packet_length
40 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Architecture
Alert FSM
Alert
Register & CounterManagement
Packet InputProcess
Packet OutputProcess
2:1Mux
corn_cnt
outputsel
• Use the control signals and the modules we just built to implement the “Register & Counter” Management module.
position
Packet Lengthlength_vld
reset
data_vlddata
reset
Packet_length
41 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Register and Counter Manger (Exercise)
Alert
Packet_Length
length_vld
corn_cnt
Packet_Length_reg
Counter
reset
inc
resetload
Register
set_value
set_value
load reset
inc_val
Counterinc
resetload
set_value
inc_valposition
Valid_data
42 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Register and Counter Manger (Exercise)
Alert
Packet_Length
length_vld
corn_cnt
Packet_Length_reg
Counter
reset
inc
resetload
Register
set_value
set_value
load reset
inc_val
Counterinc
resetload
set_value
inc_valposition
Valid_data
43 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Register and Counter Manger
Alert
Packet_Length
length_vld
corn_cnt
Packet_Length_reg
Counter
reset
inc
resetload
Register
0set_value0
set_value
load reset
inc_val1
Counterinc
resetload0
set_value0
inc_val1position
Valid_data
44 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Architecture
Alert FSM
Alert
Register & CounterManagement
Packet InputProcess
Packet OutputProcess
2:1Mux
corn_cnt
outputsel
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
position
Packet Lengthlength_vld
reset
data_vlddata
reset
Packet_length
45 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Architecture
Alert FSM
Alert
Register & CounterManagement
Packet InputProcess
Packet OutputProcess
2:1Mux
corn_cnt
outputsel
• Place the number of detections in last byte of payload
position
Packet Lengthlength_vld
reset
data_vlddata
reset
Packet_length
46 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Output sel
2:1MuxData_from_input
corn_cnt 1
0
Data_to_output
sel
Comparator
Packet_length
Position
Comparator outputs 1 if inputs match
47 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Output sel: VHDL
2:1MuxData_from_input
corn_cnt 1
0
Data_to_output
sel
Comparator
Packet_length
Position
Comparator outputs 1 if inputs match
NOT in a process!Data_to_output <= corn_cnt when (Packet_length = Position) else Data_from_input
48 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Architecture
Alert FSM
Alert
Register & CounterManagement
Packet InputProcess
Packet OutputProcess
2:1Mux
corn_cnt
outputsel
• Detect patterns in payload (e.g. “Corn!”)• Place the number of detections in last byte
of payload
position
Packet Lengthlength_vld
reset
data_vlddata
reset
Packet_length
49 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Modify corn! counter for Multiple matches
Alert
corn_cntCounter
reset
inc
reset
load0
set_value0
inc_val1
50 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Modify corn! counter for Multiple matches
Alt_0
corn_cntCounter
reset
inc
reset
load0
set_value0
inc_val1
Alt_1Alt_2Alt_3
51 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Modify corn! counter for Multiple matches
Alt_0
corn_cntCounter
reset
inc
reset
load0
set_value0
inc_val1
Alt_1Alt_2Alt_3
52 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Modify corn! counter for Multiple matches
Alt_0
corn_cntCounter
reset
inc
reset
load0
set_value0
inc_val1
Alt_1Alt_2Alt_3
OR
53 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Modify corn! counter for Multiple charactersAlt_0
corn_cntCounter
reset
inc
reset
load0
set_value0
inc_val
Alt_1Alt_2Alt_3
OR
4:1Mux
sel(Alt0,Alt1, Alt2,Alt3)
4321
NOT in a process!Alt_merge <= Alt0 & Alt1 & Alt2 & Alt3;inc_val <= 4 when (Alt_merge = “1111”) 3 when (Alt_merge = “0111” or Alt_merge = “1011” ...) 2 when (Alt_merge = “0011” or Alt_merge = “0110” ...)
else 0
54 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Modify corn! counter for Multiple matches
Alt_0
corn_cntCounter
reset
inc
reset
load0
set_value0
inc_val1
Alt_1Alt_2Alt_3
OR
55 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Modify corn! counter for Multiple matches
Alt_0
corn_cntCounter
reset
inc
reset
load0
set_value0
inc_val1
Alt_1Alt_2Alt_3
OR
56 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
MP1 overview
• Download a hardware design to the FPGA– Echo application
• Make a few simple modifications to the base project
• Perform in flight calculations during the echoing of data between a PC and FPGA over a serial connection
57 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
MP1: Make sure base project works
FPGA
PC SerialUART Echo.vhd
58 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
MP1: Delay data by 5 clock cycles
FPGA
PC SerialUART
Echo.vhd(delay 5 clks)
59 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
MP1: Convert lower case to upper case
FPGA
PC SerialUART
Echo.vhd(Modify to
capitalize only (a-z))
60 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
MP1: In flight addition
FPGA
PC SerialUART
Echo.vhd(add consecutive
numeric keystrokes)
61 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
MP1: Getting started demo
FPGA
PC SerialUART
Echo.vhd
62 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
State Machine design next Friday
63 - CPRE 583 (Reconfigurable Computing): VHDL overview 2 Iowa State University (Ames)
Questions/Comments/Concerns
• Take 5 minutes and write down VHDL clarifications you would to hear next Lecture– From lecture– Or From Shock and Awe tutorial