Coordinate Based Tracking System

Group: OX

Overview

Current Status of Project

• CDR:

Main Board Schematics

Obtain Main board parts

Motor board schematics

Assemble microcontroller board

Get processor running

Schematics

• Microcontroller Power Circuit

• Reset Circuit

• Microcontroller Circuit

• Memory

Microcontroller Power Circuit

Reset Circuit

Micrcontroller Circuit

Memory

RS232 Interfaces

Test Program for HC11

Software Flow

• Sources interrupting Microcontroller– On board serial port– Off board UART– Nintendo ControllerThe on board serial port will be interrupted by

our monitor program, and will be used to execute programs

The Nintendo Controller will be used for controlling the software flow.

Software Flow Cont.

External Instructions

• These external instructions will be received and sent using an off-board UART using RS-232.

User Movement

Preloaded Sequences

• Sequences making the motors direct in various shapes such as squares, triangles, ellipses will be generated from the processor and sent to the motor controllers.

Polling the Motor Controllers

• The motor control IC’s will have to be polled to determine if the motor has reached desired location

• This will best be implemented by sending the motor X and Y coordinates and waiting for idle state.

• This will take the major bandwidth of the system.

Xilinx XCS10

FPGA Progress

• Memory Map Logic

• NES Controller Logic

Memory Map

• 32 Kbytes EPROM

• 32 Kbytes RAM

• 10 bytes Peripherals– LCD

– Motor[X]

– Motor[Y]

– NES Controller

– UART

– ISR Pointer

Memory Map Logic

Interrupt Service Routine (ISR) Pointer

Problem:• Several Devices need external interrupt• Only one non-maskable external pin in HC11

Solution:• Implement ISR Pointer in FPGA• Pointer Register in Memory map• Read pointer as it was memory from the FPGA

Peripheral Timing

• NES needs special signals to provide push button mechanism

• Enable (E) on LCD needs to pulse after LCD address has been put on the Bus.

NES Controller

• Needs special signals provided by FPGA logic

• Will be memory mapped to address 0005H

• Can be read as normal memory

NES Controller Timing Diagram

Signal Name Period Frequency Clock Ticks (Approx)

Global Clock 125ns 8.00 MHzPulse 12us 83.3 KHz 96 (Global Clock)Latch 12ns (High) 60Hz 1024 (Pulse)

NES Controller Logic

Logic to Create Pulse and Latch Signals

NES Controller Logic Cont.

Logic to read in data from NES Controller

Overall Logic

The HCTL1000

• Why are we using it?– Made for the job

– Varying control options

– Closed Feedback loop

– Easily Programmed

Schematic for HCTL1000

HCTL Block Diagram

Using the HCTL

• Setup Registers – Commutator (5 reg)

– Control Mode (1 reg)

• Send Commutator positions (1 reg)– Feedback makes sure

its in position

The Commutator

• Four phase output– Reduced to two phase

output

• Programmable for Half step– Run phases with different

offset

• Steps with PWM– Pulse time and width

programmable for varying mode operation

The Schematic (again)

Feedback and the Filter

• Digital feedback for filter control– Accepts distance change, filters PWM

• 3 Registers for filter parameters– Gain, Pole, and Zero

• Used in position control mode

HEDM5605 #J06

• The Feedback for the HCTL1000

• 1024 Counts per rotation– Much higher than

required specifications

• Dual phase output– Set register on HCTL

to read properly

Allegro: 3964 Dual Full-Bridge PWM Motor Driver

How an H-Bridge works:

Forward mode, switches A and D closed. Reverse mode, switches B and C closed.

* H-Bridge is the mechanical equivalent of a DPDT Switch.

Functional Block Diagram

HCTL1100 #2

OPTO ISOLATOR2

1

54

12

R13

15k

R = 2.7k

C13

1u

<- ground plane changes ->

R13

15k

C13

1u

A2964SB Dual Bridge PWM Motor Driver

OUT 1B1

sense12

out 1A3

Load Supply4

GND5

GND6

GND16

GND15

Logic Supply17

out 2A18

sense219

OUT 2B20

Vref(in)7

RC18

Phase19

ENABLE110

ENABLE211

Phase212

RC213

Vref(out)14

nc nc

ncnc

RS 1RS 1

U15

Stepper Motor

A1

A2

B1

B2

OPTICAL ENCODER

GND1

INDEX2

A CHANNEL3

B CHANNEL5

+5 V4

+5V

12

3

12

3

Address Bus Low

Global_CK

U9

HCTL1100

INIT13

EXTCLK34

MC018

MC119

MC220

MC321

MC422

MC523

MC624

MC725

PHA26

PHB27

PHC28

PHD29

PROF12

PULSE16

SIGN17

CHA31

CHB30

INDEX33

AD0/DB02

AD1/DB13

AD2/DB24

AD3/DB35

AD4/DB46

AD5/DB57

DB68

DB79

ALE38

LIMIT14

RST36

R/W37

OE40

STOP15

SYNC1

CS39

OFFPAGELEFT-L

/OEChip ResetHC11 R/W

Decode Logic

+5V+5V

RS

1

RS 1

RA

1.58K RB

8.25K

+5V+5V

OPTO ISOLATOR

21

54

OPTO ISOLATOR

21

54

Motor Control with 3964

A Mount for Stepper Motors

Added Components

Our Mount for Stepper Motors

Objective Timeline

• CDR:

Main Board Schematics

Obtain Main board parts

Motor board schematics

Assemble microcontroller board

Get processor running

• Milestone 1: 

Obtain Motor Board

Assemble Motor board

Finish and test microcontroller hardware

Implement Game Pad interface

Objective Timeline (Cont)

• Milestone 2:

Monitor program running

Implement interface with motors

Real Time Embedded system PC104+ module

 

• Expo:

Run Demo modes for the laser

Receive XY and control laser

Calibrate stepper motors for tracking

Timeline