converters theme wp3.1: design tools and modelling · •silicon carbide (sic) mosfets –various...
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Converters Theme WP3.1: Design Tools and Modelling
Dr Ian Laird, Dr Xibo Yuan
University of Bristol
6/7/2016
Work Package Aims
• “Understand fundamentally the inter-relationships between size, efficiency, EMI etc., and to develop design methods and tools that enable multi-objective design optimisation.”
• “Devise and validate converter architectures with higher voltage capability, higher efficiency and greater over-load capability, which anticipate the impact of new device technologies.”
• Holistic design of wide bandgap device based converters
2
Motivation: Holistic Design
• Converter design variables are highly interconnected – Switching frequency →
Switching losses → Cooling requirement (heatsink/fan/cold plate)
– Switching frequency → Current & voltage ripples → Inductor & capacitor design
– Switching frequency / Modulation scheme → Harmonics → EMI filter design
• Manual part-by-part selection will lead to sub-optimal designs and trial and error
• An automated holistic design tool is required
3
High Power
Density
DC-link Capacitor
EMI Filter
Line Filter
Heatsink Device Loss
Model
Motivation: Wide Bandgap Devices
• Conventional multi-kW, 3-phase, Si-IGBT converters – Vo = 380 V → fs ≤ 50 kHz
– Large passives (70-80% of total volume)
• Higher fs would drive down the total volume
• Silicon carbide (SiC) MOSFETs – Various ultra high frequency converters that maintain high
efficiency (≥ 98%) have been achieved
• Higher frequency doesn’t always mean smaller volume
– “Passives-Heatsink tension”
• How much benefit is there in using wide bandgap?
• What is the optimal switching frequency?
4
Project Focus
• Work at University of Bristol has focussed on design trade-offs and optimisation of a 3-phase inverter utilising SiC MOSFETs
CDCVDC
Q1
Q4 Q6 Q2
Q5Q3
ab
cN
LΔI LDM LCM
CDM CCM
5
COMPONENT MODELLING
6
• Total loss per device: 𝑃𝑙𝑜𝑠𝑠 = 𝑃𝑄 + 𝑃𝐷 + 𝑃𝑜𝑛 + 𝑃𝑜𝑓𝑓 + 𝑃𝑟𝑟
• Conduction losses:
𝑃𝑄 =1
8+
𝑀
3𝜋cos 𝜃 𝑅𝑑𝑠(𝑜𝑛)𝐼 𝑑
2
𝑃𝐷 =1
8−
𝑀
3𝜋cos 𝜃 𝑅𝐷(𝑜𝑛)𝐼 𝑑
2
• Switching losses:
𝑃𝑥 = 𝑓𝑠
𝑉𝑑𝑐
𝑉𝐶𝐶
𝐴0(𝑥)
2+
𝐵0(𝑥)
𝜋𝐼 𝑑 +
𝐶0(𝑥)
4𝐼 𝑑
2
SiC MOSFET Loss Model
0 50 100 150 200 250 300 350 40090
91
92
93
94
95
96
97
98
99
100
fs (kHz)
Effic
iency (
%)
C2M0025120D
C2M0040120D
C2M0080120D
C2M0160120D
C2M0280120D
7
Heatsink Design
• Heatsink maximum thermal resistance:
𝑅𝑡ℎ,𝑠𝑎 =𝑇𝑗 − 𝑇𝑎 − 𝑅𝑡ℎ,𝑗𝑐𝑃𝑙𝑜𝑠𝑠
𝑛𝑃𝑙𝑜𝑠𝑠
• Natural / forced convection adjustment factor:
𝐴𝐹𝑛 = 𝑎𝑇 ∙ ∆𝑇2 + 𝑏𝑇 ∙ ∆𝑇 + 𝑐𝑇
𝐴𝐹𝑓 = 𝑎𝑣 ∙ 𝑣5 + 𝑏𝑣 ∙ 𝑣4 + 𝑐𝑣 ∙ 𝑣3 + 𝑑𝑣 ∙ 𝑣2 + 𝑒𝑣 ∙ 𝑣 + 𝑓𝑣
• Heatsink adjusted nominal thermal resistance
𝑅𝑡ℎ,𝑎𝑑𝑗 = 𝐴𝐹𝑛/𝑓 ∙ 𝑅𝑡ℎ,𝑛𝑜𝑚
• Heatsink length:
𝐿 =𝑅𝑡ℎ,𝑠𝑎
𝑎𝐿 ∙ 𝑅𝑡ℎ,𝑎𝑑𝑗
𝑏𝐿
8
Heatsink Design
0 50 100 150 200 250 300 350 4000
50
100
150
200
250
300
fs (kHz)
LH
S (
mm
)
000EK*
000EM
0K267
0K278
Heatsink extrusion length Heatsink volume envelope
Minimum heatsink length
Maximum heatsink length
9
0 50 100 150 200 250 300 350 4000
500
1000
1500
fs (kHz)
VH
S (
cm
2)
000EK*
000EM
0K267
0K278
• Line inductor based on ripple current requirements. DC link capacitor design varies depending on capacitor technology e.g. film, electrolytic
• DM and CM harmonics:
𝑉𝐷𝑀(𝑚,𝑛) =4𝑉𝑑𝑐
3𝜋𝑋(𝑚,𝑛) sin 𝑛
𝜋
3
𝑉𝐶𝑀(𝑚,𝑛) =2𝑉𝑑𝑐
3𝜋𝑋(𝑚,𝑛) 1 + 2 cos 𝑛
2𝜋
3
where 𝑋(𝑚,𝑛) =1
𝑚𝐽𝑛 𝑚
𝜋
2𝑀 sin 𝑚 + 𝑛
𝜋
2
• Filter impedance:
𝑍𝐿𝐶𝐿 𝜔(𝑚,𝑛) = 𝜔(𝑚,𝑛) 𝐿1 + 𝐿2
𝜔(𝑚,𝑛)2 − 𝜔𝑐𝑜
2
𝜔𝑐𝑜2
• Required resonant frequency:
𝜔𝑟𝑒𝑠 ≤ 𝜔(𝑚,𝑛)
𝜔(𝑚,𝑛) 𝐿1 + 𝐿2 𝐼𝑙𝑖𝑚
𝜔(𝑚,𝑛) 𝐿1 + 𝐿2 𝐼𝑙𝑖𝑚 + 𝑉𝑙𝑁(𝑚,𝑛)
Passives Design
50 100 150 200 250 300 350 4000
200
400
600
800
1000
1200
Switching frequency (kHz)
Passiv
es v
olu
me e
nvelo
pe (
cm
3)
Total
dI
DM
CM
Cdc
10
OPTIMISATION TOOL FRAMEWORK
11
Overview of Optimisation Framework
• User or algorithm defines:
– Specifications (e.g. input & output voltage, power rating)
– Constraints (e.g. maximum current & voltage ripples)
– Objectives (e.g. volume, mass)
– Design variables (e.g. devices, cores, switching frequency)
• Restrict each design variable to a discrete set of values
Enumerate the designs within the solution space. Denote the index of each possible solution as s ϵ S = 1, 2, …, |S|,
where |S| is the total number of possible designs
Define solution dependent constraints
Compute steady-state operating values
Constraints satisfied?
Compute cost J(s)
J(s) < J(s*)?
J(s*) = J(s), s* = s
START
END
s = |S|?
s = s + 1
No
No
No
s = 1
Yes
Yes
Yes
Initiate J(s*) = ∞ , s* =
12
Overview of Optimisation Framework
• Combine the design variables to form every possible design within the solution space
• For each design – Check its feasibility
– If feasible calculate the “cost” (J) based on the objective
• Choose the design with the lowest cost
• Successful but inefficient
Enumerate the designs within the solution space. Denote the index of each possible solution as s ϵ S = 1, 2, …, |S|,
where |S| is the total number of possible designs
Define solution dependent constraints
Compute steady-state operating values
Constraints satisfied?
Compute cost J(s)
J(s) < J(s*)?
J(s*) = J(s), s* = s
START
END
s = |S|?
s = s + 1
No
No
No
s = 1
Yes
Yes
Yes
Initiate J(s*) = ∞ , s* =
13
Strategies for Computational Efficiency
• Nested loop structure
• Cost function: 𝐽 = 𝑓(𝑎, 𝑏, 𝑐, 𝑑)
• Constraints: 𝑔(𝑎, 𝑏, 𝑐, 𝑑) ≤ 𝐺
• 4 Variables, 10 options = 104 = 10,000 designs
(a) (b) (c)
b ϵ b1, b2, …, bNb
c ϵ c1, c2, …, cNc
d ϵ d1, d2, …, dNd
a ϵ a1, a2, …, aNab ϵ b1, b2, …, bNb
c ϵ c1, c2, …, cNc
d ϵ d1, d2, …, dNd
a ϵ a1, a2, …, aNa
b ϵ b1, b2, …, bNb
c ϵ c1, c2, …, cNc
d ϵ d1, d2, …, dNd
a ϵ a1, a2, …, aNa
Laird, I, Scoltock, J, Forsyth, A & Yuan, X, 2016, ‘A Unified Framework for Computationally Efficient Power Converter Design Optimisation’ in the 8th IET International Conference on Power Electronics, Machines and Drives (PEMD 2016)
14
Strategies for Computational Efficiency
• Separating out parent and child variables
• Cost function: 𝐽 = 𝑓1 𝑎, 𝑏 + 𝑓2(𝑎, 𝑐, 𝑑)
• Constraints: 𝑔𝑚 𝑎, 𝑏 ≤ 𝐺𝑚, 𝑔𝑛 𝑎, 𝑐, 𝑑 ≤ 𝐺𝑛
• Designs: 10(10+102) = 1,100 (89% reduction)
(a) (b) (c)
b ϵ b1, b2, …, bNb
c ϵ c1, c2, …, cNc
d ϵ d1, d2, …, dNd
a ϵ a1, a2, …, aNab ϵ b1, b2, …, bNb
c ϵ c1, c2, …, cNc
d ϵ d1, d2, …, dNd
a ϵ a1, a2, …, aNa
b ϵ b1, b2, …, bNb
c ϵ c1, c2, …, cNc
d ϵ d1, d2, …, dNd
a ϵ a1, a2, …, aNa
Laird, I, Scoltock, J, Forsyth, A & Yuan, X, 2016, ‘A Unified Framework for Computationally Efficient Power Converter Design Optimisation’ in the 8th IET International Conference on Power Electronics, Machines and Drives (PEMD 2016)
15
Strategies for Computational Efficiency
• Decoupling into sub-problems
• Cost function: 𝐽 = 𝑓1 𝑎, 𝑏 + 𝑓2(𝑐, 𝑑)
• Constraints: 𝑔𝑚(𝑎, 𝑏) ≤ 𝐺𝑚, 𝑔𝑛(𝑐, 𝑑) ≤ 𝐺𝑛
• Designs: 102 + 102 = 200 (98% reduction)
(a) (b) (c)
b ϵ b1, b2, …, bNb
c ϵ c1, c2, …, cNc
d ϵ d1, d2, …, dNd
a ϵ a1, a2, …, aNab ϵ b1, b2, …, bNb
c ϵ c1, c2, …, cNc
d ϵ d1, d2, …, dNd
a ϵ a1, a2, …, aNa
b ϵ b1, b2, …, bNb
c ϵ c1, c2, …, cNc
d ϵ d1, d2, …, dNd
a ϵ a1, a2, …, aNa
Laird, I, Scoltock, J, Forsyth, A & Yuan, X, 2016, ‘A Unified Framework for Computationally Efficient Power Converter Design Optimisation’ in the 8th IET International Conference on Power Electronics, Machines and Drives (PEMD 2016)
16
Design Constraints
Quantity Constraint
Efficiency 98 %
Output phase current ripple 10 %
DC link voltage ripple 0.5 %
Device junction temperature 125 °C
EMI limit standard DO-160E category L, M and H
Cooling method Natural convection
CDCVDC
Q1
Q4 Q6 Q2
Q5Q3
ab
cN
LΔI LDM LCM
CDM CCM
17
Major Design Variables
Design variable Potential values / Component database
Device type Cree C2M MOSFETs (5 in total)
Switch frequency 10, 11, …, 300 kHz
Line and DM inductor core type Ferroxcube gapped double ETD cores (7 in total)
CM inductor core type TDK/EPCOS & Ferroxcube toroids (44 in total)
DM capacitor type Kemet & Vishay X1 class film (21 in total)
CM capacitor type Kemet, TDK, & Vishay Y2 class film (68 in total)
DC link capacitor type AVX, Kemet & Vishay DC film (36 total)
Heatsink types Aavid thermalloy (14 in total)
18
Optimised Values
Design variable Optimal value
Device type C2M0040120D
Switch frequency 63 kHz
Line inductor ETD59/31/22, 71 turns, 2.4 mm gap
DM inductor ETD29/16/10, 18 turns, 0.6 mm gap
CM inductor TX36/23/15-3E5, 9 turns
DM capacitor 474R3220(1)A1(2), 8 in parallel
CM capacitor B32024A3224M, 2 in parallel
DC link capacitor MKP1848 530 094K2
Heatsink 000EK*, 40.15 mm
Total 2.2 x 1012 designs Separating out parent and
child variables reduces to 224,822 designs
99.9% reduction Total volume = 1.427 L
19
658 cm3
46%
212 cm3
15%
63.2 cm3
4%
12 cm3
< 1%
482 cm3
34%
Line
DM
CM
Cdc
Heatsink
Si – SiC Comparison
SiC MOSFET Volume-Optimised Design
Si IGBT Volume-Optimised Design
Target efficiency = 98% Switching frequency = 63 kHz Total volume = 1427.2 cm3
Target efficiency = 97% Switching frequency = 8 kHz Total volume = 4396.3 cm3
20
658 cm3
46%
212 cm3
15%
63.2 cm3
4%
12 cm3
< 1%
482 cm3
34%
Line
DM
CM
Cdc
Heatsink
2.73e+03 cm3
62%
43.6 cm3
< 1%
13.7 cm3
< 1%
349 cm3
8%
1.26e+03 cm3
29%
EXPERIMENTAL WORK
21
• Double pulse tests carried out on Cree C2M0040120D (1200 V, 60 A) devices
• Test setup: – Single phase-leg of a 2-level,
3 phase converter
– 600 V DC link
– Modular +20/-5 V gate drives
– C2M0040120D devices used on both high and low side
SiC MOSFET Switching Characterisation
22
• Low Lparasitic: Current measured with PEM CWT Rogowski Coils
• High Lparasitic: ≈5 cm of track added for current measurement with a Keysight N2783B probe
SiC MOSFET Switching Characterisation
Time (ns)
Voltage (
V)
0 100 200 300 400 500 600 700 800 900 1000-100
0
100
200
300
400
500
600
700
800
0 100 200 300 400 500 600 700 800 900 1000-5
0
5
10
15
20
25
30
35
40
Curr
ent
(A)
Time (ns)
Voltage (
V)
0 100 200 300 400 500 600 700 800 900 1000-100
0
100
200
300
400
500
600
700
0 100 200 300 400 500 600 700 800 900 1000-5
0
5
10
15
20
25
30
35
Curr
ent
(A)
0 5 10 15 20 25 30 35 40 45 50-500
0
500
1000
1500
2000
2500
3000
3500
4000
4500
ID (A)
Sw
itchin
g e
nerg
y (
J)
Turn off (Low Lparasitic
)
Turn on (Low Lparasitic
)
Turn off (High Lparasitic
)
Turn on (High Lparasitic
)
Low Lparasitic
High Lparasitic
23
Heatsink Measurements
24
0
20
40
60
80
100
120
140
160
0 1 2 3 4 5 6 7 8
Tem
per
ature
(°C
)
Position from heatsink centre
50W 75W 100W 100W (fan assisted)
0 71 2 3 4 5 6
Heatsink Measurements
25
96
96.5
97
97.5
98
98.5
99
99.5
100
0 20 40 60 80 100 120 140
Eff
icie
ncy
(%
)
Frequency (kHz)
Simulation Thermal superposition
Parameter Value
Device thermal resistance 1.084 °C/W
Pad thermal resistance 0.0680 °C/W
Heatsink thermal resistance 0.7016 °C/W
Affect of device losses on efficiency
Output Filter Experimental Setup
• Modular setup to allow for testing a range of different components and circuits
• The full DM filter consists of the line filter and the DM filter specific components
• The full CM filter consists of the line filter and the CM filter specific components
Devices, Drivers, Heatsink & DC link
Line filter DM filter specific
CM filter specific
26
Continuous Operation Waveforms
Operating conditions: • VDC = 600 V • fs = 60 kHz • M = 0.94 • RL = 25 Ω
Experimental results: • Vi = 599.32 V • Ii = 7.482 A • Pi = 4.482 kW • Vo = 194.65 V • Io = 7.503 A • Po = 4.3812 kW • Efficiency = 97.75 %
27
EMI Harmonic Spectrum
101
102
103
104
105
106
0
50
100
150
Frequency (Hz)
Am
plit
ude (
dB
A
)
DM noise
DO-160E limit
101
102
103
104
105
106
0
50
100
150
Frequency (Hz)
Am
plit
ude (
dB
A
)
CM noise
DO-160E limit
28
Differential mode spectrum Common mode spectrum
Challenges & Future Work
• Further loss modelling – High frequency inductors
– Thermal spreading in heatsinks
– Better EMI spectrum prediction
– Further breakdown of device switching losses
• Using design optimisation tool to compare: – Device technologies (SiC MOSFET, SiC BJT, GaN HEMT)
– Topologies (Multi-level, Interleaving)
• Optimising the geometry and physical design – Links to virtual prototyping work
29
Thank you for your attention