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    Lab Manual

    Control Systems (EEE325)

    2nd

    Edition

    August 2011

    Department of Electrical Engineering,

    COMSATS Institute of Information Technology (CIIT),

    Islamabad

    Name: _________________________________Year: __________________________________

    Batch: _________________________________

    Roll No: ________________________________

    Majors: BCE BTE

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    Experiment 1

    Introduction to PLCs and Implementation of

    Combinational Logic through Ladder Logic

    Objectives:

    To understand the basics of PLCs and their programming using ladder logic.

    Equipment/Tools required:

    Trilogi PLC, PC with Trilogi software, connecting leads etc.

    Introduction:

    A programmable logic controller (PLC) is a specialized computer used to

    control machines and processes. It uses a programmable memory to store instructions

    and execute specific functions that include on/off control, timing, counting,

    sequencing, Arithmetic and data handling. The design of most PLCs is similar to that

    of other computers. Basically, the PLC is an assembly of solid-state digital logic

    elements designed to make logical decisions and provide outputs. Programmable

    logic controllers are used for the control and operation of manufacturing process

    equipment and machinery.

    The programmable logic controller is basically a computer designed for use in

    machine control. It has been designed to operate in the industrial environment and is

    equipped with special input/output interfaces and a control programming language.

    Initially the PLC was used to replace relay logic, but its ever-increasing range of

    functions means that it is found in many and more complex applications. Because the

    structure of a PLC is based on the same principles as those employed in computer

    architecture. It is capable not only of performing relay switching tasks but also of

    performing other applications such as counting, calculating, comparing and the

    processing of analog signals.

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    Parts of PLC:

    A typical PLC can be divided into following parts: (Figure 1.1)

    Central processing unit (CPU).

    Input/Output (l/O) section. Power supply. Programming device.

    Fig. 1.1 Parts of PLC

    PLC Scan Cycle:

    During each operating cycle, the processor reads all the inputs, takes thesevalues and energizes or de-energizes the outputs according to the user program. This

    process is known as a scan. A typical PLC scan is shown in Figure 1.2 in which PLC

    scan I/O and program. Since inputs may change continuously so PLC must carry on

    this process continuously. The PLC scan time specification indicates how fast the

    controller can react to changes in inputs. Scan time varies with program content and

    length. The time required to make a single scan can vary from about 1ms to 20ms.

    Fig. 1.2 PLC scan cycle

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    PLC Programm

    According to Int

    standard, PLC can b

    Ladder diagr Function Blo Statement lis Structured te Sequential fu

    Ladder Diagra

    Ladder Diag

    similar to the relay

    function of the lad

    conditions. This co

    ladder rung. In gen

    contact instructions,

    the coil symbol.

    Contacts and C

    Normally ONormally op

    Normally ClNormally cl

    Coil

    3

    ng:

    ernational Electrotechnical Commission (IE

    programmed using following five different

    am (logic).

    ck Diagrams (FBDs).

    ts.

    xt languages.

    nction charts.

    s:

    ram is graphical depiction of a process

    ladder logic schemes that were replaced

    er logic diagram program is to control ou

    trol is accomplished through the use of wh

    ral, a rung consists of a set of input condi

    and an output instruction at the end of the r

    ils:

    en

    n contact and is short circuited when energi

    sed

    sed contact and is converted to open circuit

    ) 61131-3/EN 6131

    languages:

    ith rungs of logic,

    by PLCs. The main

    puts based on input

    at is referred to as a

    ions, represented by

    ng is represented by

    ed.

    hen energized.

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    Implementation of AND, OR and NOT Gates using Trilogi:

    Fig. 1.3 Gates implementation

    Lab. Tasks:

    Lab Task No 1:Create a three input NAND Gate and three inputs NOR Gate.

    Lab Task No 2 (Mixer process control problem):o A mixer motor is used to automatically stir the liquid in a tank when the

    temperature and pressure reach preset values. In addition, direct manual

    operation of the motor is provided by means of a separate pushbutton station.

    The process is monitored with temperature and pressure sensors switches that

    close their respective contacts when conditions reach their preset values.

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    o Additionally the change requires that the manual pushbutton control should bepermitted to operate at any pressure but not unless the specified temperature

    setting has been reached.

    Fig. 1.4 Mixer process control

    Lab Task No 3 (Filling operation):

    A continuous filling operation requires boxes moving on a conveyor to be

    automatically positioned and filled. The operation sequence is as follows:

    o The conveyor starts when the START button is momentarily pressed and Stopwhen the STOP button is momentarily pressed.

    o When the process is operating it energize the RUN status light.o When the process stops it energize the STANDBY status light.o When box reaches right edge and sensed by PHOTOSENSOR, the conveyor

    stops and energizes the STANDBY light.

    o When the box is in position and the conveyor is stopped. The SOLENOIDvalve opens and allows box to be filled. Filling stops, when LEVEL sensor

    goes true.

    o When the box is full. The FULL light should remain energized until the boxclear o the PHOTOSENSOR.

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    Fig. 1.5 Filling operation

    Note: START: NO contacts

    STOP: NC contacts

    Level switch, Photo switch: NO contacts

    Home Tasks:

    1. Implement Flip-Flop using both NAND and NOR Gates.Truth Table of NOR Gate

    Table 1.1 NOR truth table

    S R Q Q1 0 1 0

    0 0 1 0

    0 1 0 1

    0 0 0 1

    1 1 0 0

    Truth Table of NAND Gate

    Table 1.2 NAND truth table

    S R Q Q1 0 0 1

    1 1 0 1

    0 1 1 0

    1 1 1 0

    0 0 1 1

    2. Implement 3 to 8 line decoder.