computer organisation part 4

BASIC COMPUTER ORGANISATION

God’s Organisation

Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com

CPU

I/OMEMORY

TRIODE

Buses :

A Bus (Address Bus)

D Bus (Data Bus)

C Bus (control Bus)

System Buses (Collection of A,B,C)

Note : Primary Memory directly addressable by CPU

Secondary Memory not directly addressable by CPU


RAM ROM

IOC

I/P 1

O/P 1

I/P 2

I/P n

O/P m

O/P 2

.

.

.

.

.

.

Memory

FLAG

TIMING &CONTROL

IR

SPPC

VGPR

INTERFACE

I/O

ALU

ACC


Bus Convention :

A/B Bus C Bus

Exchange of Information :

Unidirectional

Note :I / O Control : South BridgeMemory Control : North Bridge

Note :Memory which can be change itself is known as register.

Note :Every CPU is microprocessor, But every microprocessor is not CPU


Transformation mechanism that transforms the given input into a desired O/P is typically called a PROCESS

Entity that perform these task (transformation) is typically called PROCESSOR

The method followed where processor is performing a process is typically called PROCESSING

(Process is being processed by processor is PROCESSING)

Role of Flags : 2 flags are affected when we go for A – B and they are Z (Zero) and B (Borrow).

Z B0 0 A>B0 1 A<B1 0 A=B1 1 X

Z . B + Z . B = S1 Z . B = S2


Role of Register : Pentium processor contains only 4 register(Register is nothing but a scratch pad memory)

x = y + z

According to programming language:

MOV R0 , yMOV R1 , zADD R0 , R1

MOV x , R0

Translated by Compiler

L Value

R Value

=

x +

zy

This is Parse Tree Or Syntax Tree

Note : Accumulator is represented by ( R0 / A )

( Most General Purpose Register )


Role of Special Purpose Register (SPR):Program Counter / Instruction Counter( It holds address of next instruction to be executed )

100

PC

101

101

Next Instruction’s address is in PC now, instruction at that address is read out and put it in Instruction Register. (Click any where to move)

This all process is maintained by Operating System

Instruction Register

Stack Pointer ( It can not contain address of any empty location and when it not point to any thing than it contain NULL )


Role of Instruction Register (IR):

.

.

.

100100

Machine Operation (M.O.) + (M.O.) + (M.O.) + (M.O.) + . . . = Macro Operation(Micro Operation) ( 1 Instruction Execution )

1. Fetching of Instruction

2. Decoding of Instruction ( What to do ? )

3. Fetching of Data ( if any )

4. Execution

5 Stores Result

Machine Operations


Instruction and Addressing Mode :

ADD A , B

OperandOperation

1. Zero Addressing Instruction

2. One Addressing Instruction

3. Two Addressing Instruction

4. Three Addressing Instruction

1. Zero Register Processor (C.P.U) OR

Stack Oriented Computer OR

Zero Register Organised C.P.U Not a single GPR is available not even ACC

2. Single Register Processor Only one Register ACC

3. General Register Organisation More than one register ( ACC + many other register )

Classification


3 Address Instruction



Given Equation : X = ( A * B ) + ( C * D )

MUL R1 , A B MUL R2 , C DADD X , R1 R2

MOV R1 , AMOV R1 , BMOV R2 , CMOV R2 , DMOV R1 , R2MOV X , R1

MUL A , BMUL C , DADD A , CMOV X , A In this case we will loose value of A and C therefore not feasible

LOAD A ( R0 A )MUL B ( R0 R0 * B )STORE T1LOAD CMUL DADD T1STORE X

Note : Implicit operand is ACC / A / R0



PUSH A

PUSH B

MUL

A

A

B

A * B

PUSH C

PUSH D

A * B

C

A * B

C

D

MUL

C * D

A * B

ADD

(A*B) + (C*D)

STORE X

(A*B) + (C*D)(Calculated)

X(in Memory)


Instruction Construction :

OPERATOR DESTINATION / SOURCE 1 SOURCE 2

0 ADD1 SUB

00 R001 R110 R211 M

1 2 2 5 bits

TYPE OPERATOR DESTINATION / SOURCE 1 SOURCE 2

0 ARITHEMATIC1 LOGICAL

00 ADD / AND01 SUB / OR10 MUL / XOR11 DIV / NOT

000 R0

001 R1

010 R2

. .

. .

. .

111 R7Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com

Addressing Mode :

Instruction( How you are getting data )

MemoryOperand

RegisterOperand

Input OutputOperand

Operand OR Operator

Direct Indirect

Register-Register Indirect

Register-Memory Indirect

Memory-Memory Indirect

Memory-Register Indirect

Immediate


1. ADD[6] Direct Pointer

(The address of operand is available in instruction (ORIGINAL WORKING))

At location 6 (0110) , we are having address 9 (1001) of operand (1001011101).

2. Add 6 Immediate

(Data is part of instruction , data is not in any register or memory)

Here, data is available is Instruction, 6 (0110) is itself is data

3. IADD[6] Indirect

(Pointer)

At location 6 (0110) , we are having address 9 (1001), of memory location which is having address of operand (1001011101).It means it

is concept of pointer to pointer

0110 1001

1001 1001011101

0110

1001

1100

1100

1001011101

1001


Implied Mode : ( operand is at CPU’s register )

CMA Compliment ACC.STC Set Carry

Immediate Mode :( data is part of Instruction )

ADD 6 Add 6 to Accumulator

Register Mode : ( Operand is available in GPR )

ADD B A A + BADD A , B A A + B ADD R1 R0 R0 + R1

Register Indirect Mode :

IADD B A A + [M]B

the content of Memory Mwhose address is given by register Bmust be Added to A


Memory4096 X 16

PC ( Program Counter )

I OPR

E

MAR

MBR

AC

1 2 3 . . . . . .16

1 2 3 . . . . . .16

1 2 3 . . . . . .16

1 2 3 . . . 12

1 1 2 3

1


BUSESCPU CPU

MAINMEMORY

NORTH BRIDGE

AGP

SOUTHBRIDGE

VIDEOBUS

LOCAL VIDEO MEMORY

MONITOR

DVD

IOAPIC

SUPERI/O

BIOS

IRC

HDDCD

ROM

SOUNDCHIP

SCSIETHERNET

ISA BUS

ADIC BUS

FSB

HOST PORT

PORTAGP POINT

PCI SLOT

IDE

USB

ISASLOT

FDD

RPINTER

COM 1

COM 2

KB

MOUSE

INTERRUPT

PCI BUS


PRIMITIVE BUS ARCHITECTURE

The drawback of this technique is that a double side bus is needed

PROCESSOR MEMORY

I/O

O/P

CONTROL

1

2


SHARED BUS ARCHITECTURE

PROCESSORI/O I/O I/O MEMORY

BACKPLANE BUS

Different i/o has different data transmission protocol

and also having different speed (mismatch) for that,

and this is all burden taken care by one device

Shared Bus typically called Backplane Bus


2 Leveled Architecture

The previously said bus system is also having disadvantage of CPU Overheads,to remove this we have two type of Level Architecture :

1. 2 Leveled Architecture2. 3 Leveled Architecture

Processor Memory

BusAdaptor

BusAdaptor

Processor Memory Bus(PMB)

BusAdaptor

I/O BusI/O Bus

I/O Bus

Note : Conflicts and Mismatch can be taken care by Bus Adaptor now this not burden for CPUKrishna Kumar Bohra (KKB), MCA LMCST

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3 Leveled Architecture

Processor Memory

MBA

Processor Memory Bus(PMB)

BA

BA

Backplane Bus

Note : PMB is not directly connected to I/O, rather connected to MBA


Proprietaryand

rest all are Free

TransferVideo camera

To PC


BUS TRANSFER :

1. Strobe Method

2. Handshake Method

1. Strobe Method : (source initiated)

SU DU

Timing Diagram

Block Diagram

Valid DataData

Strobe

t1 t2 t3 t4Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com

1. Strobe Method : (destination initiated)

SU DU

Timing DiagramValid Data

Data

Strobe

Block Diagram


2. Handshaking Method : ( Source Initiated )

Block Diagram

SU DUData Bus

DAV

DAC

SU DU

Click for Every Action

DAV DAC01 01

Data Valid Data Accept


Valid DataData

Timing Diagram

Place Data on BUSEnable DAV

Accept DataEnable DAC

Disable DAV

Disable DAV

DAV

DAC


2. Handshaking Method : ( Destination Initiated )

SU DU

Block Diagram

Data Bus

DAV

RFD

SU DU

Click for Every Action

DAV DAC0 01

Data Valid Data Accept

Ready to Accept Data

1


Place Data on BUSEnable DAV

Ready to accept DataEnable DAC

Disable DAV

Accept Data from Enable DAC

Valid Data

Data

Timing Diagram


Bus Scheduling :

1. Daisy Chaining

2. Polling

3. Independent

Daisy Chaining

Bus ControlUnit

(BCU)

U1 U2 Un. . .Bus Grant

Bus Request

Bus BusyBUS


Bus ControlUnit

(BCU)

U1 U2 Un. . .Bus Grant

Bus Request

Bus BusyBUS

Case 1: U1 is requesting for BUS

Case 2: U2 is requesting for BUS

Case 3: Un is requesting for BUS

.

.

.

Note: (Sequential processing)Therefore Un have lowest priority and U1 have highest priority.If U1 leave then only other gets the chance.(as shown in diagram)

U1 grab the Bus


Polling

Bus ControlUnit

(BCU)

U1 U2 Un

Poll count

BR

BB

8 devices : 3 poll count16 devices : 4 poll count

000 001 111. . .


Independent

Bus ControlUnit

(BCU)

U1 U2 Un

Poll count

. . .


Booth Algorithm :(Using 2’s compliment)

STOP

START

A=0, QN-1=0M=MULTIPLECANDQ=MULTIPLIERCOUNT =N

Q0QN-1

Arithmetic Shift RightA Q QN-1

COUNT=N

COUNT =0?

A=A+MA=A-M

=10 =01

Yes

No

=11=00


Multiplication Algorithm :(Using Signed Magnitude)

START

As = Qs + BsQs = Qs + BsA = 0 , E = 0SC = n - 1

QN-1=?

SHR EA QSC=SC-1

SC=?

EA=A+B

=1

=0

Not 0

=1

STOP

MULTIPICAND BMULTIPLIER Q

Bs

As Qs

E A Q QN


Division Algorithm :

Basic Steps:

“A trial division” is made by subtracting the y register from Accumulator after the subtraction one of the following is executed

1. if Result is – ve the divisor will not go so a ZERO is placed in rightmost bit of the B register and Accumulator is restored. The combined B register and Accumulator are shifted Left.

2. if Result of subtraction is + ve or Zero, then the trail division is succeeded. The Accumulator and B register both are shifted left and then 1 is placed in the right most bit of B.


CBest of LuckKrishna Kumar Bohra (KKB), MCA LMCST

www.selectall.wordpress.com

computer organisation part 4

Technology

cpukrishna kumar bohra

mca lmcstwww

cpu secondary memory

o control

primary memory

fora b

south bridgememory control

desired op