computer essentials syllabus - uam

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Subject: Computer Essentials Code: 17816 Institution: Escuela Politécnica Superior Degree: Computer Science and Engineering Level: Graduate Type: Core Course ECTS: 6

COMPUTER ESSENTIALS SYLLABUS

This syllabus for the subject Computer Essentials (FCO), approved for the 2014-2015 school year at the Central Board and published in its final form on the website of the Escuela Politécnica Superior before the registration period, has the character of a contract with the student.

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1. SUBJECT

Computer Essentials

1.1. Course number

17816

1.2. Course area

Computer Engineering

1.3. Course type

Core course

1.4. Course level

Graduate

1.5. Year

1º

1.6. Semester

1º

1.7. Credit allotment

6

1.8. Prerequisites

No prerequisites are needed to attend this course.

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1.9. Minimum attendance requirement

Two itineraries are possible, one with mandatory attendance and one without it.

Each student must choose one of them at the beginning of the course. Each itinerary

has a different evaluation method.

MANDATORY ATTENDANCE ITINERARY AND NO MANDATORY ATTENDANCE FOR THEORY CONTENTS

In both of them the classes’ attendance is not mandatory but strongly recommended.

VERY IMPORTANT:

Activities like tests, exams and special exercises can be done during the lectures and

the obtained marks will be used for the final mark. No attending these classes

implies zero points at the activity.

MANDATORY ATTENDANCE ITINERARY FOR PRACTICAL CONTENTS (LABORATORY)

In the mandatory attendance itinerary the student must attend all the practical

classes and present the results reports of the proposed practices.

For justified reasons, the student may miss up to 2 practice sessions (4 hours), but

the presentation of the results report is compulsory. In the case of reaching a larger

number of absences or non-presenting any of the reports requested, will be excluded

from the mandatory attendance itinerary.

MANDATORY ATTENDANCE ITINERARY FOR PRACTICAL CONTENTS (LABORATORY)

The classes’ attendance is not mandatory but strongly recommended. Students

should pass a practical exam when the subject finishes.

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1.10. Faculty data

Susana Holgado González-Guerrero (Coordinadora) Departamento de Tecnología Electrónica y de las Comunicaciones Escuela Politécnica Superior Office: C Building. Nº: 229 Tel.: +34 91 497 2265 e-mail: [email protected] Web site: http://arantxa.ii.uam.es/~sholgado/ Office hours: Flexible. Please, contact previously by e-mail.

Guillermo González de Rivera Peces Departamento de Tecnología Electrónica y de las Comunicaciones Escuela Politécnica Superior Office: C Building. Nº: 233 Tel.: +34 91 497 2262 e-mail: [email protected] Web site: http://arantxa.ii.uam.es/~gdrivera/ Office hours: Flexible. Please, contact previously by e-mail.

Javier Garrido Salas Departamento de Tecnología Electrónica y de las Comunicaciones Escuela Politécnica Superior OfficeC Building. Nº: 238 Tel.: +34 91 497 2254 e-mail: [email protected] Web site: http://arantxa.ii.uam.es/~jgarrido/ Office hours: Flexible. Please, contact previously by e-mail.

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1.11. Course objectives

Basic analysis and construction techniques are learnt in this course. The training obtained in this subject is crucial to facilitate the study of more complicated designs in subsequent courses. The basic units of information used for operation in digital circuits are studied, learning the most basic operations used in digital design, along with their properties. It also explores the complex operational elements immediately above the most basic for the design of a digital circuit. The most basic data storage units along with the fundamentals of the construction of some basic sequential circuits are learnt. At the end of the course the student should be able to build logic functions efficiently as well as using the operating elements of complexity immediately above. The student should also be able of analysing and building a basic sequential circuit in an efficiently way. The competences acquired in this course are: Basic: B5: Knowledge of the structure, organization, working and interconnection of computer systems, the basics of programming and its application to engineering problems. Common: C9: Capacity to know, understand and evaluate the organization and architecture of computers and the basic components included in them. Specific: IC1: Capacity to design and implement digital systems, including computers, microprocessor based systems and communication systems.

At the end of each unit, the student should be capable of:

SPECIFIC OBJECTIVES BY CHAPTER

CHAPTER 1.- Data types and its digital representation

1.1. Given a natural number, represented in some basis, obtain its representation on any other basis.

1.2. Write an integer (positive or negative) in sign-magnitude representation, and two’s complement. Justify the benefits of two’s complement representation against the sign-magnitude representation.

1.3. Represent a given number in floating point.

1.4. Be able to perform the operations of addition, subtraction, multiplication and division with both positive and negative binary numbers.

1.5. Recognize and use the different codes for detection and error correction.

CHAPTER 2. - Boolean Algebra and Logic Design.

2.1. Define with you own words the following concepts: digit, bit, variable binary logic, logic function and truth table.

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2.2. Define and be able to apply the properties and basic theorems of Boolean algebra.

2.3. Be able to draw the symbol, specify the truth table and express the logical operation that implements each of the following gates: NOT, AND, OR, NAND, NOR and XOR, with two or more inputs.

2.4. Be able, from the truth table of a function, to write the logical expression of that function as a sum of minterms and a product of maxterms, and draw the logic diagram of the circuit.

2.5. Be able to simplify a function using Karnaugh maps.

CHAPTER 3. - Combinational components.

3.1.

Define combinational logic circuit. Draw the symbol, specify the truth table, provide a logical expression of each output, draw the internal logic diagram using basic gates and describe with your own words the functionality of the combinational elements: decoder, multiplexer, priority encoder, magnitude comparator, half-adder, full adder.

3.2. Obtain, from a truth table, the represented combinational circuit. Get the truth table of a combinational circuit from its logical schema.

3.3. Be able to use decoders and multiplexers as logic function generators.

3.4. Define arithmetic and logic unit. Design a simple arithmetic logic unit.

3.5. Define and use ripple-carry adders and carry look-ahead adders.

3.6. Define what a bus is and be able to explain its use.

CHAPTER 4. - Basic blocks of sequential logic.

4.1. Define the concept of bistable and clock signal. Be able to define and distinguish the concepts of latch and edge-triggered bistable (flip-flop).

4.2. Define and explain the operation of the latches SR, JK and D associated with the concepts of memory, current and next state, asynchronous inputs and clock signal.

4.3.

Define the different flip-flops (JK, D and T) and draw the symbol used in logic diagrams to represent them. Use your own words to express their functionality. Express its functionality through the transition tables (next state truth table) and output.

4.4. Draw the timing diagram of the output signal, Q, of a flip-flop from the timing diagram of the input signal and the clock signal.

CHAPTER 5.- Sequential circuits.

5.1. Use your own words to express what a sequential circuit is and the differences between a combinational and a sequential circuit.

5.2. Define what a register is. Design and be capable of using shift registers. Show the performance of those registers using timing diagrams.

5.3. Define, design and use counters. Check the operation of a counter using a timing diagram.

5.4. Be able to define and distinguish Moore and Mealy designs.

5.5. Perform Moore and Mealy sequential designs.

CHAPTER 6.- Memory components.

6.1. Define random access memory. Be able to explain its operation.

6.2. Recognize, define and use read-only memories.

6.3. Be able to calculate the bits capacity of a memory.

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1.12. Course contents

1. Data types and its digital representation 1.1. Binary numeral system. Conversion between systems. 1.2. Sum of binary numbers. 1.3. Representation of both positive and negative integers. 1.4. Two’s complement operations. 1.5. Representation of real numbers. Fixed-point and floating-point numbers. 1.6. Other binary codes: BCD y ASCII. 1.7. Error codes.

1.7.1. Hamming distance 1.7.2. Parity codes 1.7.3. CRC codes

2. Boolean Algebra and Logic Design. 2.1. Properties and basic theorems of Boolean algebra.

2.1.1. Boolean operations and expresions. 2.1.2. Laws and rules of Boolean algebra. 2.1.3. DeMorgan’s theorems.

2.2. Digital logic gates. 2.2.1. Boolean expresions and truth table. 2.2.2. Extension to multiple inputs. 2.2.3. Functional enable. 2.2.4. Gates implementation.

2.3. Karnaugh maps. 2.3.1. Minimizing a sum of products using the Karnaugh map. 2.3.2. Minimization of a product of sums using the Karnaugh map.

3. Combinational circuits. 3.1. Basic combinational logic circuits: decoder, multiplexer, priority encoder,

magnitude comparator, semi-adder, full adder. 3.2. Combinational logic implementation. 3.3. Decoders and Multiplexers as function generators. 3.4. Ripple-carry adders and carry look-ahead adders. 3.5. Arithmetic and Logic Unit (ALU). 3.6. Buses.

4. Basic elements of the sequential logic. 4.1. Latches

4.1.1. Types of latches. 4.2. Flip-Flops.

4.2.1. Types of Flip-Flops. 4.3. Timing diagrams.

5. Sequential circuits. 5.1. Sequential logic analysis. 5.2. Registers.

5.2.1. Shift registers. 5.3. Finite States Machines.

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5.4. Counters. 5.4.1. Ring counter. 5.4.2. Other synchronous counters.

5.5. Moore and Mealy circuits. Minimization of states.

6. Memory components. 6.1. Random Access Memories (RAM)

6.1.1. Structure of a semiconductor RAM. Size. 6.1.2. Volatile memories. 6.1.3. Organization of internal memory in one and two dimensions. 6.1.4. Dynamic RAM. Refresh.

6.2. Read Only Memories (ROM). 6.2.1. Programmable ROM (PROM) and erasable (EPROM) 6.2.2. Using ROM as functions generator.

1.13. Course bibliography

Basic:

1. Fundamentos de Sistemas Digitales. Thomas L. Floyd. Prentice Hall. 9ª Ed. 2006.

Secondary:

2. Digital Design and Computer Architecture. David Money Harris y Sarah L. Harris. Morgan Kaufmann. 2007.

3. Fundamentos de diseño lógico y de computadoras. M. Morris Mano y Charles R. Kime. Prentice Hall. 3ª Ed. 2005.

4. Sistemas Digitales. Principios y Aplicaciones. Tocci y Widmer. Prentice Hall. 8ª Ed. 2003.

5. Sistemas Digitales y Tecnología de Computadores. J. García Zubía, I. Angulo Martínez, J.M. Angulo Usategui. Thomson. 2ª Ed. 2007.

6. Fundamentos de Diseño Lógico. Charles H. Roth. Thomson. 5ª Ed.2004.

7. Sistemas Digitales. A. Lloris Ruíz, A. Prieto Espinosa, L. Parrilla Roure. McGraw-Hill. 2003.

8. Electrónica Digital. L. Cuesta, A. Gil Padilla, F. Remiro. Serie Schaum. McGraw-Hill. 2000.

MC.5041803

Texto escrito a máquina

Bibliography available at the library’s catalogue (click here)

MC.5041803


MC.5041803


http://biblos.uam.es/uhtbin/cgisirsi/X/FILOSOFIA/Y/28/4943/X

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2. TEACHING METHODS

The methodology used in the development of teaching includes the following types of activities: *Theory: Lecturer Activity:

Lectures with exercises. Presentations are in electronic format, complemented by the use of the blackboard.

Student Activity:

Classroom Activity: Note-taking. Active participation in class responding to the raised issues. Exercises solving during the classes. Home Activity: Preparation of notes. Studying the material and completing the raised questionnaires in the Virtual Campus of the subject.

*Tutorials (in the classroom): Lecturer Activity:

Tutoring the whole classroom or in small groups of students in order to solve common doubts planted by students individually or in groups, arising from questions / exercises / problems identified in class for this purpose and guidance regarding the conduct thereof.

Student Activity: Classroom Activity: Approach individual or group concerns and possible solutions approach to the proposed tasks. Home Activity: Study proposed tasks and discussion of proposed solutions within the group.

*Practice: Lecturer Activity:

Assign a practice to each workgroup and explain the practice at the beginning of the practice session. Monitor the workgroups in the laboratory. Deliver of the practice statement in the laboratory. The expository method is used both in tutorials and laboratory with each group. The resources used are: laboratory software installed at computers and the laboratory hardware: protoboards, integrated circuits and cables to implement and simulate the proposed circuits

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Student Activity: Classroom Activity: Initial approach, prior to the development of practical, from the information contained in the statement. At the end of the practice a brief report will be delivered to the teacher, showing the design and the simulation performed. The students will be asked about their work in order to qualify them individually. Also the designed circuits must be implemented in a protoboard, showing the teacher their correct operation. Home Activity: Work in the practice statement and raise its optimal resolution. Write a practice report including the implemented design and its simulation and a diagram of the practical assembly.

2.1. Student workload

2.2. Evaluation Methods and Final Rating Estimation

a. The both parts, theory and practice, are evaluated on 10 points.

The subject final rating is estimated using the theory and practice ratings, according the following equation:

Final Rating: 0,4*Practice + 0,6*Theory

b. To pass the subject is mandatory to obtain a rating bigger or equal to 5 points, both theory and practice. Otherwise, the final rating will be obtained using:

Final Rating: (0,4*Min(5,Practice) + 0,6*Min(5,Theory))

Students who do not desire to follow the ITINERARY WITH COMPULSORY ATTENDANCE

must communicate by e-mail to their theory professor his intention, before the

ordinary final exam.

Hours Percentage

Classroom Theory (3h x14 semanas) 42 h (28%)

78 h (52%)

Practice (2h x13 semanas) 26 h (17%)

Programmed tutorials during the semester 4 h (3%)

Ordinary written final exam 3 h (2%)

Ordinary written extraordinary exam 3 h (2%)

Home Regulated weekly study (3 hours x 14 weeks) 42 h (28%)

72 h (48%) Ordinary final exam preparation 12 h (8%)

Extraordinary final exam preparation 18 h (12%)

Total workload: 25 hours x 6 ECTS 150 h

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1. For students who decide the itinerary with COMPULSARY attendance (CA) their ratings will be obtained with the following equation:

a. The theory rating will be calculated as follow:

a.1 The weighted average of the three partial exams and the rest of the other evaluable activities during the course.

Theory Rating = CA_Rating= 0,2*Exam1 + 0,35*Exam2 + 0,3*Exam3 + 0,15*Other_activities

a.2 The final exam rating (100%).

Theory Rating = Final exam rating

Partial written tests will be conducted during school hours and will consist of the evaluation of the objectives to be achieved by students during the units that make up each part, as well as the units included in the previous partial.

The rating of less than 3.5 points in any of the three partial exams, is the exclusion of the method of the compulsory attendance itinerary.

In addition to the written test, the rating of each part is obtained by evaluation of other activities that preferentially focus on the objectives to be achieved by students in the different periods of the course.

The final exam will be a written exam about the whole subject contents

The written tests will include both theoretical issues and troubleshooting.

A student may to improve the compulsory attendance itinerary rating by presenting the final exam. In this case the following weighting will be considered:

Theory Rating = 0,4*CA_Rating + 0,6*Final_exam_rating

b. The final practice rating is the weighted sum of the rating of the practices carried

out during the course.

To pass the practical part, students must attend all practical clases. With justified reasons, a student may miss up two practice sessions (4 hours), and must submit reports. Otherwise, the student must perform a practice exam consisting of a practice of greater complexity than those carried out in the laboratory.

The rating of the practical part will consider the quality of the designs and the level of results. Also assess the validity of the results obtained in each of the sections that have been set for implementation in practice scripts.

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2. For students who choose an itinerary without COMPULSORY ATTENDANCE, rating will be obtained as follows:

a. The rating of the theory part is:

The ordinary final exam rating (100%).

The final exam will be written and the contents will cover all the objectives to be achieved by students in the full course. This exam may include theoretical issues and problems.

b. The rating for the practice part is the one obtained on a single exam that will evaluate the concepts developed in the labs for students of compulsory attendance itinerary.

For both, COMPULSORY and NOT COMPULSORY attendance:

The theory qualification is conserved (validated) only for the same academic year.

The practice qualification is conserved (validated) for the extraordinary final exam in the same academic year and provided that the qualification obtained is equal to or greater than 6.0 points, for the two calls the following year.

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2.3. Schedule

Week Classroom

Home Theory Practice (laboratory)

1ª Unit 1 Studying the proposed materials on U1.

Problems solving on chapter U1.

2ª Unit 1

Practice 0a: Protoboard


Problems solving on chapter U2. 4ª Unit 2

Practice 0b: Tutorial ISE-Xilinx Tutorial

5ª Unit 3

Practice 1: ISE Design

Studying the proposed materials on U3.


6ª Unit 3

7ª Unit 3 Practice 2: Design and implementation of combinational digital circuits using multiplexers and decoders

8ª Unit 4 Studying the proposed materials on U4

Problems solving on chapter U4. 9ª Unit 4 Practice 3:

Design and implementation of sequential digital systems: counters 10ª Unit 5

Studying the proposed materials on U5.


11ª Unit 5

Practice 4: Overall design of digital systems. Development Project

12ª Unit 5


Problems solving on chapter U6. 14ª Exercises

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computer essentials syllabus - uam

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